OpenCores
URL https://opencores.org/ocsvn/g729a_codec/g729a_codec/trunk

Subversion Repositories g729a_codec

[/] [g729a_codec/] [trunk/] [SYN/] [ALTERA/] [g729a_selftest_syn.tcl] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 madsilicon 
# Copyright (C) 1991-2009 Altera Corporation
2 
# Your use of Altera Corporation's design tools, logic functions
3 
# and other software and tools, and its AMPP partner logic
4 
# functions, and any output files from any of the foregoing
5 
# (including device programming or simulation files), and any
6 
# associated documentation or information are expressly subject
7 
# to the terms and conditions of the Altera Program License
8 
# Subscription Agreement, Altera MegaCore Function License
9 
# Agreement, or other applicable license agreement, including,
10 
# without limitation, that your use is for the sole purpose of
11 
# programming logic devices manufactured by Altera and sold by
12 
# Altera or its authorized distributors.  Please refer to the
13 
# applicable agreement for further details.
14 
 
15 
# Quartus II: Generate Tcl File for Project
16 
# File: g729a_selftest_syn.tcl
17 
# Generated on: Sat Nov 02 09:44:58 2013
18 
 
19 
# Load Quartus II Tcl Project package
20 
package require ::quartus::project
21 
 
22 
set need_to_close_project 0
23 
set make_assignments 1
24 
 
25 
# Check that the right project is open
26 
if {[is_project_open]} {
27 
        if {[string compare $quartus(project) "g729a_selftest_syn"]} {
28 
                puts "Project g729a_selftest_syn is not open"
29 
                set make_assignments 0
30 
        }
31 
} else {
32 
        # Only open if not already open
33 
        if {[project_exists g729a_selftest_syn]} {
34 
                project_open -revision g729a_syn g729a_selftest_syn
35 
        } else {
36 
                project_new -revision g729a_syn g729a_selftest_syn
37 
        }
38 
        set need_to_close_project 1
39 
}
40 
 
41 
# Make assignments
42 
if {$make_assignments} {
43 
        set_global_assignment -name FAMILY "Cyclone III"
44 
        set_global_assignment -name DEVICE EP3C25F324C8
45 
        set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
46 
        set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:32:18  OCTOBER 15, 2013"
47 
        set_global_assignment -name LAST_QUARTUS_VERSION 9.1
48 
        set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
49 
        set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
50 
        set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
51 
        set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
52 
        set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
53 
        set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
54 
        set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
55 
        set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
56 
        set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
57 
        set_global_assignment -name MISC_FILE "g729a_syn.dpf"
58 
        set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
59 
        set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
60 
        set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
61 
        set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
62 
        set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
63 
        set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
64 
        set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
65 
        set_global_assignment -name VHDL_FILE G729A_codec_selftest.vhd
66 
        set_global_assignment -name VHDL_FILE G729A_asip_roms_mif.vhd
67 
        set_global_assignment -name VHDL_FILE G729A_asip_adder_f.vhd
68 
        set_global_assignment -name VHDL_FILE G729A_asip_addsub_pipeb.vhd
69 
        set_global_assignment -name VHDL_FILE G729A_asip_arith_pkg.vhd
70 
        set_global_assignment -name VHDL_FILE G729A_asip_basic_pkg.vhd
71 
        set_global_assignment -name VHDL_FILE G729A_asip_bjxlog.vhd
72 
        set_global_assignment -name VHDL_FILE G729A_asip_cfg_pkg.vhd
73 
        set_global_assignment -name VHDL_FILE G729A_asip_cpu_2w_p6.vhd
74 
        set_global_assignment -name VHDL_FILE G729A_asip_ftchlog_2w.vhd
75 
        set_global_assignment -name VHDL_FILE G729A_asip_fwdlog_2w_p6.vhd
76 
        set_global_assignment -name VHDL_FILE G729A_asip_idec.vhd
77 
        set_global_assignment -name VHDL_FILE G729A_asip_idec_2w.vhd
78 
        set_global_assignment -name VHDL_FILE G729A_asip_idec_2w_pkg.vhd
79 
        set_global_assignment -name VHDL_FILE G729A_asip_idec_pkg.vhd
80 
        set_global_assignment -name VHDL_FILE G729A_asip_ifq.vhd
81 
        set_global_assignment -name VHDL_FILE G729A_asip_lcstk.vhd
82 
        set_global_assignment -name VHDL_FILE G729A_asip_lcstklog_2w.vhd
83 
        set_global_assignment -name VHDL_FILE G729A_asip_lcstklog_ix.vhd
84 
        set_global_assignment -name VHDL_FILE G729A_asip_logic.vhd
85 
        set_global_assignment -name VHDL_FILE G729A_asip_lsu.vhd
86 
        set_global_assignment -name VHDL_FILE G729A_asip_lu.vhd
87 
        set_global_assignment -name VHDL_FILE G729A_asip_mulu_pipeb.vhd
88 
        set_global_assignment -name VHDL_FILE G729A_asip_op_pkg.vhd
89 
        set_global_assignment -name VHDL_FILE G729A_asip_pipe_a_2w.vhd
90 
        set_global_assignment -name VHDL_FILE G729A_asip_pipe_b.vhd
91 
        set_global_assignment -name VHDL_FILE G729A_asip_pkg.vhd
92 
        set_global_assignment -name VHDL_FILE G729A_asip_pstllog_2w_p6.vhd
93 
        set_global_assignment -name VHDL_FILE G729A_asip_pxlog.vhd
94 
        set_global_assignment -name VHDL_FILE G729A_asip_rams.vhd
95 
        set_global_assignment -name VHDL_FILE G729A_asip_regfile_16x16_2w.vhd
96 
        set_global_assignment -name VHDL_FILE G729A_asip_shftu.vhd
97 
        set_global_assignment -name VHDL_FILE G729A_asip_spc.vhd
98 
        set_global_assignment -name VHDL_FILE G729A_asip_top_2w.vhd
99 
        set_global_assignment -name VHDL_FILE G729A_codec_intf_pkg.vhd
100 
        set_global_assignment -name VHDL_FILE G729A_codec_sdp.vhd
101 
        set_global_assignment -name SDC_FILE ext_clk.sdc
102 
        set_global_assignment -name BDF_FILE g729a_syn.bdf
103 
        set_global_assignment -name SEARCH_PATH ../../vhdl
104 
        set_global_assignment -name SEARCH_PATH western/
105 
        set_global_assignment -name SEARCH_PATH tcl/
106 
        set_global_assignment -name SEARCH_PATH hdlc/code/
107 
        set_location_assignment PIN_V9 -to 50MHZ
108 
        set_location_assignment PIN_N2 -to CPU_RESET_N
109 
        set_location_assignment PIN_P13 -to LED0
110 
        set_location_assignment PIN_P12 -to LED1
111 
        set_location_assignment PIN_N12 -to LED2
112 
        set_location_assignment PIN_N9 -to LED3
113 
        set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
114 
 
115 
        # Commit assignments
116 
        export_assignments
117 
 
118 
        # Close project
119 
        if {$need_to_close_project} {
120 
                project_close
121 
        }
122 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.