URL https://opencores.org/ocsvn/g729a_codec/g729a_codec/trunk

Subversion Repositories g729a_codec

[/] [g729a_codec/] [trunk/] [VHDL/] [G729A_asip_idec_2w.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2013 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- Instruction decoder (stage 1)
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library work;
use work.G729A_ASIP_PKG.all;
use work.G729A_ASIP_IDEC_2W_PKG.all;
use work.G729A_ASIP_OP_PKG.all;
 
entity G729A_ASIP_IDEC1_2W is
  port(
    INSTR_i : in std_logic_vector(ILEN-1 downto 0);
 
    OPB_IMM_o : out std_logic;
    OPB_o : out LDWORD_T;
    DEC_INSTR_o : out DEC_INSTR_T
  );
end G729A_ASIP_IDEC1_2W;
 
architecture ARC of G729A_ASIP_IDEC1_2W is
 
  function EXTS16(V : std_logic_vector) return signed is
    variable S : signed(SDLEN-1 downto 0);
  begin
    S(V'HIGH downto 0) := to_signed(V);
    S(SDLEN-1 downto V'HIGH+1) := (others => V(V'HIGH));
    return(S);
  end function;
 
  function EXTS32(V : std_logic_vector) return signed is
    variable S : signed(LDLEN-1 downto 0);
  begin
    S(V'HIGH downto 0) := to_signed(V);
    S(LDLEN-1 downto V'HIGH+1) := (others => V(V'HIGH));
    return(S);
  end function;
 
  signal OP1 : integer range 0 to 16-1;
  signal OP2 : integer range 0 to 16-1;
  signal OP2_RRR : integer range 0 to 256-1;
  signal RD,RA,RB,RDF : RID_T;
  signal IMNMC : INST_MNEMONIC_T;
  signal WRD,RRA,RRB : std_logic;
  signal LD,LA,LB : std_logic;
  signal IMM : signed(16-1 downto 0);
  signal ALU_OP : ALU_OP_T;
  signal BJ_OP : BJ_OP_T;
  signal LS_OP : LS_OP_T;
  signal WOVF : std_logic;
  signal WACC : std_logic;
  signal IMM8 : std_logic_vector(8-1 downto 0);
  signal IMM12,IMM12_S : std_logic_vector(12-1 downto 0);
  signal IMM16,IMM16_S : std_logic_vector(16-1 downto 0);
  signal P0_ONLY : std_logic;
 
begin
 
  -- instruction subfields extraction
  process(INSTR_i)
    variable B0,B1,B2,B3,B4,B5 : std_logic_vector(4-1 downto 0);
    variable TMP : std_logic_vector(8-1 downto 0);
  begin
    B0 := INSTR_i(4*1-1 downto 4*0);
    B1 := INSTR_i(4*2-1 downto 4*1);
    B2 := INSTR_i(4*3-1 downto 4*2);
    B3 := INSTR_i(4*4-1 downto 4*3);
    B4 := INSTR_i(4*5-1 downto 4*4);
    B5 := INSTR_i(4*6-1 downto 4*5);
 
    -- major opcode
    OP1 <= to_integer(to_unsigned(B5));
 
    -- minor opcode
    OP2 <= to_integer(to_unsigned(B0));
 
    -- minor opcode for RRR type instructions
 
    -- WARNING: this extra step is needed to
    --insure correct ordering!
 
    TMP := (B1 & B0);
 
    OP2_RRR <= to_integer(to_unsigned(TMP));
 
    -- register identifiers
    RD <= to_integer(to_unsigned(B4));
    --RD2 <= to_integer(to_unsigned(B3)); -- for ldpp/stpp
    RA <= to_integer(to_unsigned(B3));
    RB <= to_integer(to_unsigned(B2));
 
    -- immediate operands
    IMM8 <= INSTR_i(12-1 downto 4);
    IMM12 <= INSTR_i(12-1 downto 0);
    IMM12_S <= INSTR_i(20-1 downto 16) & INSTR_i(12-1 downto 4);
    IMM16 <= INSTR_i(16-1 downto 0);
    IMM16_S <= INSTR_i(20-1 downto 4);
 
  end process;
 
  -- instruction mnemonic and operand flags extraction
  process(OP1,OP2,OP2_RRR)
  begin
    WRD <= '0';
    RRA <= '0';
    RRB <= '0';
    LD <= '0';
    LA <= '0';
    LB <= '0';
    ALU_OP <= ALU_NIL;
    BJ_OP <= BJ_NIL;
    LS_OP <= LS_NIL;
    WACC <= '0';
    WOVF <= '0';
    P0_ONLY <= '0';
    case OP1 is
      when 0 =>
        -- RRR instruction
        case OP2_RRR is
          when 0 =>
            -- abs rD,rA
            IMNMC <= IM_ABS;
            WRD <= '1';
            RRA <= '1';
            ALU_OP <= ALU_ABS;
          when 1 =>
            -- labs rD,rA
            IMNMC <= IM_LABS;
            WRD <= '1';
            RRA <= '1';
            LD <= '1';
            LA <= '1';
            ALU_OP <= ALU_LABS;
          when 2 =>
            -- add rD,rA,rB
            IMNMC <= IM_ADD;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_ADD;
          when 3 =>
            -- ladd rD,rA,rB
            IMNMC <= IM_LADD;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            LA <= '1';
            LB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LADD;
          when 4 =>
            -- neg rD,rA
            IMNMC <= IM_NEG;
            WRD <= '1';
            RRA <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_NEG;
          when 5 =>
            -- lneg rD,rA
            IMNMC <= IM_LNEG;
            WRD <= '1';
            RRA <= '1';
            LD <= '1';
            LA <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LNEG;
          when 6 =>
            -- sub rD,rA,rB
            IMNMC <= IM_SUB;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_SUB;
          when 7 =>
            -- lsub rD,rA,rB
            IMNMC <= IM_LSUB;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            LA <= '1';
            LB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LSUB;
          when 8 =>
            -- lext rD,rA
            IMNMC <= IM_LEXT;
            WRD <= '1';
            RRA <= '1';
            LD <= '1';
            LA <= '1';
            ALU_OP <= ALU_LEXT;
          when 9 =>
            -- rnd rD,rA
            IMNMC <= IM_RND;
            WRD <= '1';
            RRA <= '1';
            --LD <= '1';
            LA <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_RND;
          when 10 =>
            -- mul rD,rA,rB
            IMNMC <= IM_MUL;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_MUL;
          when 11 =>
            -- lmul rD,rA,rB
            IMNMC <= IM_LMUL;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            --LA <= '1';
            --LB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LMUL;
          when 12 =>
            -- mula rD,rA,rB
            IMNMC <= IM_MULA;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            ALU_OP <= ALU_MULA;
          when 13 =>
            -- shl rD,rA,rB
            IMNMC <= IM_SHL;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_SHL;
          when 14 =>
            -- lshl rD,rA,rB
            IMNMC <= IM_LSHL;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            LA <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LSHL;
          when 15 =>
            -- shr rD,rA,rB
            IMNMC <= IM_SHR;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            ALU_OP <= ALU_SHR;
          when 16 =>
            --lshr rD,rA,rB
            IMNMC <= IM_LSHR;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            LA <= '1';
            ALU_OP <= ALU_LSHR;
          when 17 =>
            -- nrms rD,rA
            IMNMC <= IM_NRMS;
            WRD <= '1';
            RRA <= '1';
            ALU_OP <= ALU_NRMS;
          when 18 =>
            -- nrml rD,rA
            IMNMC <= IM_NRML;
            WRD <= '1';
            RRA <= '1';
            LA <= '1';
            ALU_OP <= ALU_NRML;
          when 19 =>
            -- lmac rD,rA,rB
            IMNMC <= IM_LMAC;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            WACC <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LMAC;
            --SC <= '0';
          when 20 =>
            -- lmsu rD,rA,rB
            IMNMC <= IM_LMSU;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            WACC <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LMSU;
            --SC <= '0';
          when 21 =>
            -- mulr rD,rA,rB
            IMNMC <= IM_MULR;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_MULR;
            --SC <= '0';
          --when 22 =>
          --  -- m32 rD,rA,rB
          --  IMNMC <= IM_M32;
          --  WRD <= '1';
          --  RRA <= '1';
          --  RRB <= '1';
          --  LD <= '1';
          --  LA <= '1';
          --  LB <= '1';
          --  WOVF <= '1';
          --  ALU_OP <= ALU_M32;
          --  --SC <= '0';
          when 23 =>
            -- m3216 rD,rA,rB
            IMNMC <= IM_M3216;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            LD <= '1';
            LA <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_M3216;
            --SC <= '0';
          when 24 =>
            -- and rD,rA,rB
            IMNMC <= IM_AND;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            ALU_OP <= ALU_AND;
          when 25 =>
            -- or rD,rA,rB
            IMNMC <= IM_OR;
            WRD <= '1';
            RRA <= '1';
            RRB <= '1';
            ALU_OP <= ALU_OR;
          when 26 =>
            -- jmp rA
            IMNMC <= IM_JMP;
            RRA <= '1';
            BJ_OP <= BJ_JR;
            P0_ONLY <= '1';
          when 27 =>
            -- jmp rD,rA
            IMNMC <= IM_JMPL;
            WRD <= '1';
            RRA <= '1';
            BJ_OP <= BJ_JRL;
            ALU_OP <= ALU_MOVA;
            P0_ONLY <= '1';
          when 29 =>
            -- halt
            IMNMC <= IM_HALT;
            P0_ONLY <= '1';
          when 30 =>
            -- llcr rA
            IMNMC <= IM_LLCR;
            RRA <= '1';
            P0_ONLY <= '1';
          when 31 =>
            -- lclr
            IMNMC <= IM_LCLR;
            P0_ONLY <= '1';
          when 32 =>
            -- rovf rD
            IMNMC <= IM_ROVF;
            WRD <= '1';
            ALU_OP <= ALU_ROVF;
          when 33 =>
            -- covf
            IMNMC <= IM_COVF;
            WOVF <= '1';
            ALU_OP <= ALU_COVF;
          when 34 =>
            -- racc rD
            IMNMC <= IM_RACC;
            WRD <= '1';
            LD <= '1';
            ALU_OP <= ALU_RACC;
          when 35 =>
            -- wacc rA
            IMNMC <= IM_WACC;
            RRA <= '1';
            LA <= '1';
            WACC <= '1';
            ALU_OP <= ALU_MOVA; --ALU_WACC;
          when 36 =>
            -- nop
            IMNMC <= IM_NOP;
          when 37 =>
            -- pxon
            IMNMC <= IM_PXON;
            P0_ONLY <= '1';
          when 38 =>
            -- pxoff
            IMNMC <= IM_PXOFF;
            P0_ONLY <= '1';
          when others =>
            IMNMC <= IM_BAD_INSTR;
        end case;
 
      when 1 =>
        -- addi rD,rA,imm12
        IMNMC <= IM_ADDI;
        WRD <= '1';
        RRA <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_ADD;
 
      when 2 =>
        -- laddi rD,rA,imm12
        IMNMC <= IM_LADDI;
        WRD <= '1';
        RRA <= '1';
        LD <= '1';
        LA <= '1';
        LB <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_LADD;
 
      when 3 =>
        -- subi rD,rA,imm12
        IMNMC <= IM_SUBI;
        WRD <= '1';
        RRA <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_SUB;
 
      when 4 =>
        -- lsubi rD,rA,imm12
        IMNMC <= IM_LSUBI;
        WRD <= '1';
        RRA <= '1';
        LD <= '1';
        LA <= '1';
        LB <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_LSUB;
 
      when 5 =>
        -- muli rD,rA,imm12
        IMNMC <= IM_MULI;
        WRD <= '1';
        RRA <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_MUL;
 
      when 6 =>
        -- lmuli rD,rA,imm12
        IMNMC <= IM_LMULI;
        WRD <= '1';
        RRA <= '1';
        LD <= '1';
        --LA <= '1';
        --LB <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_LMUL;
 
      when 7 =>
        -- lmulai rD,rA,imm12
        IMNMC <= IM_MULAI;
        WRD <= '1';
        RRA <= '1';
        ALU_OP <= ALU_MULA;
 
      when 8 =>
        -- RRI8 instructions
        case OP2 is
          when 0 =>
            -- shli rD,rA,imm8
            IMNMC <= IM_SHLI;
            WRD <= '1';
            RRA <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_SHL;
          when 1 =>
            -- lshli rD,rA,imm8
            IMNMC <= IM_LSHLI;
            WRD <= '1';
            RRA <= '1';
            LD <= '1';
            LA <= '1';
            WOVF <= '1';
            ALU_OP <= ALU_LSHL;
          when 2 =>
            -- shri rD,rA,imm8
            IMNMC <= IM_SHRI;
            WRD <= '1';
            RRA <= '1';
            ALU_OP <= ALU_SHR;
          when 3 =>
            -- lshri rD,rA,imm8
            IMNMC <= IM_LSHRI;
            WRD <= '1';
            RRA <= '1';
            LD <= '1';
            LA <= '1';
            ALU_OP <= ALU_LSHR;
          --when 4 =>
          --  -- andli rD,rA,imm8
          --  IMNMC <= IM_ANDLI;
          --  WRD <= '1';
          --  RRA <= '1';
          --  ALU_OP <= ALU_ANDL;
          --when 5 =>
          --  -- andhi rD,rA,imm8
          --  IMNMC <= IM_ANDHI;
          --  WRD <= '1';
          --  RRA <= '1';
          -- ALU_OP <= ALU_ANDH;
          --when 6 =>
          --  -- orli rD,rA,imm8
          --  IMNMC <= IM_ORLI;
          --  WRD <= '1';
          --  RRA <= '1';
          --  ALU_OP <= ALU_ORL;
          --when 7 =>
          --  -- orhi rD,rA,imm8
          --  IMNMC <= IM_ORHI;
          --  WRD <= '1';
          --  RRA <= '1';
          --  ALU_OP <= ALU_ORH;
          when 8 =>
            -- beq rA,rB,imm8
            IMNMC <= IM_BEQ;
            RRA <= '1';
            RRB <= '1';
            IMNMC <= IM_BEQ;
            BJ_OP <= BJ_BEQ;
            P0_ONLY <= '1';
          when 9 =>
            -- bne rA,rB,imm8
            IMNMC <= IM_BNE;
            RRA <= '1';
            RRB <= '1';
            BJ_OP <= BJ_BNE;
            P0_ONLY <= '1';
          when 10 =>
            -- ld rD,rA,imm8
            IMNMC <= IM_LD;
            WRD <= '1';
            RRA <= '1';
            LS_OP <= LS_LD;
          when 11 =>
            -- st rA,rB,imm8
            IMNMC <= IM_ST;
            RRA <= '1';
            RRB <= '1';
            LS_OP <= LS_ST;
            P0_ONLY <= '1';
          --when 12 =>
          --  -- ldpp rD,rA,imm8
          --  IMNMC <= IM_LDPP;
          --  WRD <= '1';
          --  WRD2 <= '1';
          --  RRA <= '1';
          --  ALU_OP <= ALU_INC;
          --  LS_OP <= LS_LD;
          --  --SC <= '0';
          --when 13 =>
          --  -- stpp rA,rB,imm8
          --  IMNMC <= IM_STPP;
          --  WRD2 <= '1';
          --  RRA <= '1';
          --  RRB <= '1';
          --  ALU_OP <= ALU_INC;
          --  LS_OP <= LS_ST;
          when others =>
            IMNMC <= IM_BAD_INSTR;
        end case;
 
      when 9 =>
        -- lmaci rD,rA,imm12
        IMNMC <= IM_LMACI;
        WRD <= '1';
        RRA <= '1';
        LD <= '1';
        WACC <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_LMAC;
 
      when 10 =>
        -- lmsui rD,rA,imm12
        IMNMC <= IM_LMSUI;
        WRD <= '1';
        RRA <= '1';
        LD <= '1';
        WACC <= '1';
        WOVF <= '1';
        ALU_OP <= ALU_LMSU;
 
      when 11 =>
        -- jmpli rD,imm16
        IMNMC <= IM_JMPLI;
        WRD <= '1';
        BJ_OP <= BJ_JIL;
        ALU_OP <= ALU_MOVA;
        P0_ONLY <= '1';
 
      when 12 =>
        -- RI12 or I16 instruction
        case OP2 is
          when 0 =>
            -- blez rA,imm12
            IMNMC <= IM_BLEZ;
            RRA <= '1';
            BJ_OP <= BJ_BLEZ;
            P0_ONLY <= '1';
          when 1 =>
            -- lblez rA,imm12
            IMNMC <= IM_LBLEZ;
            RRA <= '1';
            LA <= '1';
            BJ_OP <= BJ_LBLEZ;
            P0_ONLY <= '1';
          when 2 =>
            -- bgtz rA,imm12
            IMNMC <= IM_BGTZ;
            RRA <= '1';
            BJ_OP <= BJ_BGTZ;
            P0_ONLY <= '1';
          when 3 =>
            -- lbgtz rA,imm12
            IMNMC <= IM_LBGTZ;
            RRA <= '1';
            LA <= '1';
            BJ_OP <= BJ_LBGTZ;
            P0_ONLY <= '1';
          when 4 =>
            -- bltz rA,imm12
            IMNMC <= IM_BLTZ;
            RRA <= '1';
            BJ_OP <= BJ_BLTZ;
            P0_ONLY <= '1';
          when 5 =>
            -- lbltz rA,imm12
            IMNMC <= IM_LBLTZ;
            RRA <= '1';
            LA <= '1';
            BJ_OP <= BJ_LBLTZ;
            P0_ONLY <= '1';
          when 6 =>
            -- bgez rA,imm12
            IMNMC <= IM_BGEZ;
            RRA <= '1';
            BJ_OP <= BJ_BGEZ;
            P0_ONLY <= '1';
          when 7 =>
            -- lbgez rA,imm12
            IMNMC <= IM_LBGEZ;
            RRA <= '1';
            LA <= '1';
            BJ_OP <= BJ_LBGEZ;
            P0_ONLY <= '1';
          when 8 =>
            -- jmpi imm16
            IMNMC <= IM_JMPI;
            BJ_OP <= BJ_JI;
            P0_ONLY <= '1';
          when 9 =>
            -- llbri imm16
            IMNMC <= IM_LLBRI;
            P0_ONLY <= '1';
          when 10 =>
            -- lleri imm16
            IMNMC <= IM_LLERI;
            P0_ONLY <= '1';
          when 11 =>
            -- llcri imm16
            IMNMC <= IM_LLCRI;
            P0_ONLY <= '1';
          when others =>
            IMNMC <= IM_BAD_INSTR;
        end case;
 
      when 13 =>
        -- movi rD,imm16
        IMNMC <= IM_MOVI;
        WRD <= '1';
        ALU_OP <= ALU_MOVB;
 
      when others =>
        -- invalid instruction
        IMNMC <= IM_BAD_INSTR;
 
    end case;
  end process;
 
  OPB_IMM_o <= '0' when
    (OP1 = 0) or
    ((OP1 = 8) and (OP2 = 8 or OP2 = 9 or OP2 = 11 or OP2 = 13))
    else '1';
 
  -- Operand B selector
  process(OP1,OP2,OP2_RRR,IMM8,IMM12,IMM12_S,IMM16,IMM16_S)
  begin
    case OP1 is
      when 1|2|3|4|5|6|7|9|10 =>
        OPB_o <= EXTS32(IMM12);
      when 8 =>
        OPB_o <= EXTS32(IMM8);
      when 11|13 =>
        OPB_o <= EXTS32(IMM16);
      when 12 =>
        if(OP2 = 8 or OP2 = 9 or OP2 = 10 or OP2 = 11) then
          OPB_o <= EXTS32(IMM16_S);
        else
          OPB_o <= EXTS32(IMM12_S);
        end if;
      when others =>
        OPB_o <= (others => '0');
    end case;
  end process;
 
  IMM <= (others => '0');
 
  -- decoded instruction
  DEC_INSTR_o <= (
    IMNMC,
    WRD,
    RRA,
    RRB,
    RD,
    RA,
    RB,
    IMM,
    LD,
    LA,
    LB,
    ALU_OP,
    BJ_OP,
    LS_OP,
    WOVF,
    WACC,
    P0_ONLY
  );
 
end ARC;

Browse

Tools

Subversion Repositories g729a_codec

[/] [g729a_codec/] [trunk/] [VHDL/] [G729A_asip_idec_2w.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	madsilicon	`-----------------------------------------------------------------`
2			`-- --`
3			`-----------------------------------------------------------------`
4			`-- --`
5			`-- Copyright (C) 2013 Stefano Tonello --`
6			`-- --`
7			`-- This source file may be used and distributed without --`
8			`-- restriction provided that this copyright statement is not --`
9			`-- removed from the file and that any derivative work contains --`
10			`-- the original copyright notice and the associated disclaimer.--`
11			`-- --`
12			-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
13			`-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --`
14			`-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --`
15			`-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --`
16			`-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --`
17			`-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --`
18			`-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --`
19			`-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --`
20			`-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --`
21			`-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --`
22			`-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --`
23			`-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --`
24			`-- POSSIBILITY OF SUCH DAMAGE. --`
25			`-- --`
26			`-----------------------------------------------------------------`
27
28			`---------------------------------------------------------------`
29			`-- Instruction decoder (stage 1)`
30			`---------------------------------------------------------------`
31
32			`library IEEE;`
33			`use IEEE.std_logic_1164.all;`
34			`use IEEE.numeric_std.all;`
35
36			`library work;`
37			`use work.G729A_ASIP_PKG.all;`
38			`use work.G729A_ASIP_IDEC_2W_PKG.all;`
39			`use work.G729A_ASIP_OP_PKG.all;`
40
41			`entity G729A_ASIP_IDEC1_2W is`
42			`port(`
43			`INSTR_i : in std_logic_vector(ILEN-1 downto 0);`
44
45			`OPB_IMM_o : out std_logic;`
46			`OPB_o : out LDWORD_T;`
47			`DEC_INSTR_o : out DEC_INSTR_T`
48			`);`
49			`end G729A_ASIP_IDEC1_2W;`
50
51			`architecture ARC of G729A_ASIP_IDEC1_2W is`
52
53			`function EXTS16(V : std_logic_vector) return signed is`
54			`variable S : signed(SDLEN-1 downto 0);`
55			`begin`
56			`S(V'HIGH downto 0) := to_signed(V);`
57			`S(SDLEN-1 downto V'HIGH+1) := (others => V(V'HIGH));`
58			`return(S);`
59			`end function;`
60
61			`function EXTS32(V : std_logic_vector) return signed is`
62			`variable S : signed(LDLEN-1 downto 0);`
63			`begin`
64			`S(V'HIGH downto 0) := to_signed(V);`
65			`S(LDLEN-1 downto V'HIGH+1) := (others => V(V'HIGH));`
66			`return(S);`
67			`end function;`
68
69			`signal OP1 : integer range 0 to 16-1;`
70			`signal OP2 : integer range 0 to 16-1;`
71			`signal OP2_RRR : integer range 0 to 256-1;`
72			`signal RD,RA,RB,RDF : RID_T;`
73			`signal IMNMC : INST_MNEMONIC_T;`
74			`signal WRD,RRA,RRB : std_logic;`
75			`signal LD,LA,LB : std_logic;`
76			`signal IMM : signed(16-1 downto 0);`
77			`signal ALU_OP : ALU_OP_T;`
78			`signal BJ_OP : BJ_OP_T;`
79			`signal LS_OP : LS_OP_T;`
80			`signal WOVF : std_logic;`
81			`signal WACC : std_logic;`
82			`signal IMM8 : std_logic_vector(8-1 downto 0);`
83			`signal IMM12,IMM12_S : std_logic_vector(12-1 downto 0);`
84			`signal IMM16,IMM16_S : std_logic_vector(16-1 downto 0);`
85			`signal P0_ONLY : std_logic;`
86
87			`begin`
88
89			`-- instruction subfields extraction`
90			`process(INSTR_i)`
91			`variable B0,B1,B2,B3,B4,B5 : std_logic_vector(4-1 downto 0);`
92			`variable TMP : std_logic_vector(8-1 downto 0);`
93			`begin`
94			`B0 := INSTR_i(41-1 downto 40);`
95			`B1 := INSTR_i(42-1 downto 41);`
96			`B2 := INSTR_i(43-1 downto 42);`
97			`B3 := INSTR_i(44-1 downto 43);`
98			`B4 := INSTR_i(45-1 downto 44);`
99			`B5 := INSTR_i(46-1 downto 45);`
100
101			`-- major opcode`
102			`OP1 <= to_integer(to_unsigned(B5));`
103
104			`-- minor opcode`
105			`OP2 <= to_integer(to_unsigned(B0));`
106
107			`-- minor opcode for RRR type instructions`
108
109			`-- WARNING: this extra step is needed to`
110			`--insure correct ordering!`
111
112			`TMP := (B1 & B0);`
113
114			`OP2_RRR <= to_integer(to_unsigned(TMP));`
115
116			`-- register identifiers`
117			`RD <= to_integer(to_unsigned(B4));`
118			`--RD2 <= to_integer(to_unsigned(B3)); -- for ldpp/stpp`
119			`RA <= to_integer(to_unsigned(B3));`
120			`RB <= to_integer(to_unsigned(B2));`
121
122			`-- immediate operands`
123			`IMM8 <= INSTR_i(12-1 downto 4);`
124			`IMM12 <= INSTR_i(12-1 downto 0);`
125			`IMM12_S <= INSTR_i(20-1 downto 16) & INSTR_i(12-1 downto 4);`
126			`IMM16 <= INSTR_i(16-1 downto 0);`
127			`IMM16_S <= INSTR_i(20-1 downto 4);`
128
129			`end process;`
130
131			`-- instruction mnemonic and operand flags extraction`
132			`process(OP1,OP2,OP2_RRR)`
133			`begin`
134			`WRD <= '0';`
135			`RRA <= '0';`
136			`RRB <= '0';`
137			`LD <= '0';`
138			`LA <= '0';`
139			`LB <= '0';`
140			`ALU_OP <= ALU_NIL;`
141			`BJ_OP <= BJ_NIL;`
142			`LS_OP <= LS_NIL;`
143			`WACC <= '0';`
144			`WOVF <= '0';`
145			`P0_ONLY <= '0';`
146			`case OP1 is`
147			`when 0 =>`
148			`-- RRR instruction`
149			`case OP2_RRR is`
150			`when 0 =>`
151			`-- abs rD,rA`
152			`IMNMC <= IM_ABS;`
153			`WRD <= '1';`
154			`RRA <= '1';`
155			`ALU_OP <= ALU_ABS;`
156			`when 1 =>`
157			`-- labs rD,rA`
158			`IMNMC <= IM_LABS;`
159			`WRD <= '1';`
160			`RRA <= '1';`
161			`LD <= '1';`
162			`LA <= '1';`
163			`ALU_OP <= ALU_LABS;`
164			`when 2 =>`
165			`-- add rD,rA,rB`
166			`IMNMC <= IM_ADD;`
167			`WRD <= '1';`
168			`RRA <= '1';`
169			`RRB <= '1';`
170			`WOVF <= '1';`
171			`ALU_OP <= ALU_ADD;`
172			`when 3 =>`
173			`-- ladd rD,rA,rB`
174			`IMNMC <= IM_LADD;`
175			`WRD <= '1';`
176			`RRA <= '1';`
177			`RRB <= '1';`
178			`LD <= '1';`
179			`LA <= '1';`
180			`LB <= '1';`
181			`WOVF <= '1';`
182			`ALU_OP <= ALU_LADD;`
183			`when 4 =>`
184			`-- neg rD,rA`
185			`IMNMC <= IM_NEG;`
186			`WRD <= '1';`
187			`RRA <= '1';`
188			`WOVF <= '1';`
189			`ALU_OP <= ALU_NEG;`
190			`when 5 =>`
191			`-- lneg rD,rA`
192			`IMNMC <= IM_LNEG;`
193			`WRD <= '1';`
194			`RRA <= '1';`
195			`LD <= '1';`
196			`LA <= '1';`
197			`WOVF <= '1';`
198			`ALU_OP <= ALU_LNEG;`
199			`when 6 =>`
200			`-- sub rD,rA,rB`
201			`IMNMC <= IM_SUB;`
202			`WRD <= '1';`
203			`RRA <= '1';`
204			`RRB <= '1';`
205			`WOVF <= '1';`
206			`ALU_OP <= ALU_SUB;`
207			`when 7 =>`
208			`-- lsub rD,rA,rB`
209			`IMNMC <= IM_LSUB;`
210			`WRD <= '1';`
211			`RRA <= '1';`
212			`RRB <= '1';`
213			`LD <= '1';`
214			`LA <= '1';`
215			`LB <= '1';`
216			`WOVF <= '1';`
217			`ALU_OP <= ALU_LSUB;`
218			`when 8 =>`
219			`-- lext rD,rA`
220			`IMNMC <= IM_LEXT;`
221			`WRD <= '1';`
222			`RRA <= '1';`
223			`LD <= '1';`
224			`LA <= '1';`
225			`ALU_OP <= ALU_LEXT;`
226			`when 9 =>`
227			`-- rnd rD,rA`
228			`IMNMC <= IM_RND;`
229			`WRD <= '1';`
230			`RRA <= '1';`
231			`--LD <= '1';`
232			`LA <= '1';`
233			`WOVF <= '1';`
234			`ALU_OP <= ALU_RND;`
235			`when 10 =>`
236			`-- mul rD,rA,rB`
237			`IMNMC <= IM_MUL;`
238			`WRD <= '1';`
239			`RRA <= '1';`
240			`RRB <= '1';`
241			`WOVF <= '1';`
242			`ALU_OP <= ALU_MUL;`
243			`when 11 =>`
244			`-- lmul rD,rA,rB`
245			`IMNMC <= IM_LMUL;`
246			`WRD <= '1';`
247			`RRA <= '1';`
248			`RRB <= '1';`
249			`LD <= '1';`
250			`--LA <= '1';`
251			`--LB <= '1';`
252			`WOVF <= '1';`
253			`ALU_OP <= ALU_LMUL;`
254			`when 12 =>`
255			`-- mula rD,rA,rB`
256			`IMNMC <= IM_MULA;`
257			`WRD <= '1';`
258			`RRA <= '1';`
259			`RRB <= '1';`
260			`ALU_OP <= ALU_MULA;`
261			`when 13 =>`
262			`-- shl rD,rA,rB`
263			`IMNMC <= IM_SHL;`
264			`WRD <= '1';`
265			`RRA <= '1';`
266			`RRB <= '1';`
267			`WOVF <= '1';`
268			`ALU_OP <= ALU_SHL;`
269			`when 14 =>`
270			`-- lshl rD,rA,rB`
271			`IMNMC <= IM_LSHL;`
272			`WRD <= '1';`
273			`RRA <= '1';`
274			`RRB <= '1';`
275			`LD <= '1';`
276			`LA <= '1';`
277			`WOVF <= '1';`
278			`ALU_OP <= ALU_LSHL;`
279			`when 15 =>`
280			`-- shr rD,rA,rB`
281			`IMNMC <= IM_SHR;`
282			`WRD <= '1';`
283			`RRA <= '1';`
284			`RRB <= '1';`
285			`ALU_OP <= ALU_SHR;`
286			`when 16 =>`
287			`--lshr rD,rA,rB`
288			`IMNMC <= IM_LSHR;`
289			`WRD <= '1';`
290			`RRA <= '1';`
291			`RRB <= '1';`
292			`LD <= '1';`
293			`LA <= '1';`
294			`ALU_OP <= ALU_LSHR;`
295			`when 17 =>`
296			`-- nrms rD,rA`
297			`IMNMC <= IM_NRMS;`
298			`WRD <= '1';`
299			`RRA <= '1';`
300			`ALU_OP <= ALU_NRMS;`
301			`when 18 =>`
302			`-- nrml rD,rA`
303			`IMNMC <= IM_NRML;`
304			`WRD <= '1';`
305			`RRA <= '1';`
306			`LA <= '1';`
307			`ALU_OP <= ALU_NRML;`
308			`when 19 =>`
309			`-- lmac rD,rA,rB`
310			`IMNMC <= IM_LMAC;`
311			`WRD <= '1';`
312			`RRA <= '1';`
313			`RRB <= '1';`
314			`LD <= '1';`
315			`WACC <= '1';`
316			`WOVF <= '1';`
317			`ALU_OP <= ALU_LMAC;`
318			`--SC <= '0';`
319			`when 20 =>`
320			`-- lmsu rD,rA,rB`
321			`IMNMC <= IM_LMSU;`
322			`WRD <= '1';`
323			`RRA <= '1';`
324			`RRB <= '1';`
325			`LD <= '1';`
326			`WACC <= '1';`
327			`WOVF <= '1';`
328			`ALU_OP <= ALU_LMSU;`
329			`--SC <= '0';`
330			`when 21 =>`
331			`-- mulr rD,rA,rB`
332			`IMNMC <= IM_MULR;`
333			`WRD <= '1';`
334			`RRA <= '1';`
335			`RRB <= '1';`
336			`WOVF <= '1';`
337			`ALU_OP <= ALU_MULR;`
338			`--SC <= '0';`
339			`--when 22 =>`
340			`-- -- m32 rD,rA,rB`
341			`-- IMNMC <= IM_M32;`
342			`-- WRD <= '1';`
343			`-- RRA <= '1';`
344			`-- RRB <= '1';`
345			`-- LD <= '1';`
346			`-- LA <= '1';`
347			`-- LB <= '1';`
348			`-- WOVF <= '1';`
349			`-- ALU_OP <= ALU_M32;`
350			`-- --SC <= '0';`
351			`when 23 =>`
352			`-- m3216 rD,rA,rB`
353			`IMNMC <= IM_M3216;`
354			`WRD <= '1';`
355			`RRA <= '1';`
356			`RRB <= '1';`
357			`LD <= '1';`
358			`LA <= '1';`
359			`WOVF <= '1';`
360			`ALU_OP <= ALU_M3216;`
361			`--SC <= '0';`
362			`when 24 =>`
363			`-- and rD,rA,rB`
364			`IMNMC <= IM_AND;`
365			`WRD <= '1';`
366			`RRA <= '1';`
367			`RRB <= '1';`
368			`ALU_OP <= ALU_AND;`
369			`when 25 =>`
370			`-- or rD,rA,rB`
371			`IMNMC <= IM_OR;`
372			`WRD <= '1';`
373			`RRA <= '1';`
374			`RRB <= '1';`
375			`ALU_OP <= ALU_OR;`
376			`when 26 =>`
377			`-- jmp rA`
378			`IMNMC <= IM_JMP;`
379			`RRA <= '1';`
380			`BJ_OP <= BJ_JR;`
381			`P0_ONLY <= '1';`
382			`when 27 =>`
383			`-- jmp rD,rA`
384			`IMNMC <= IM_JMPL;`
385			`WRD <= '1';`
386			`RRA <= '1';`
387			`BJ_OP <= BJ_JRL;`
388			`ALU_OP <= ALU_MOVA;`
389			`P0_ONLY <= '1';`
390			`when 29 =>`
391			`-- halt`
392			`IMNMC <= IM_HALT;`
393			`P0_ONLY <= '1';`
394			`when 30 =>`
395			`-- llcr rA`
396			`IMNMC <= IM_LLCR;`
397			`RRA <= '1';`
398			`P0_ONLY <= '1';`
399			`when 31 =>`
400			`-- lclr`
401			`IMNMC <= IM_LCLR;`
402			`P0_ONLY <= '1';`
403			`when 32 =>`
404			`-- rovf rD`
405			`IMNMC <= IM_ROVF;`
406			`WRD <= '1';`
407			`ALU_OP <= ALU_ROVF;`
408			`when 33 =>`
409			`-- covf`
410			`IMNMC <= IM_COVF;`
411			`WOVF <= '1';`
412			`ALU_OP <= ALU_COVF;`
413			`when 34 =>`
414			`-- racc rD`
415			`IMNMC <= IM_RACC;`
416			`WRD <= '1';`
417			`LD <= '1';`
418			`ALU_OP <= ALU_RACC;`
419			`when 35 =>`
420			`-- wacc rA`
421			`IMNMC <= IM_WACC;`
422			`RRA <= '1';`
423			`LA <= '1';`
424			`WACC <= '1';`
425			`ALU_OP <= ALU_MOVA; --ALU_WACC;`
426			`when 36 =>`
427			`-- nop`
428			`IMNMC <= IM_NOP;`
429			`when 37 =>`
430			`-- pxon`
431			`IMNMC <= IM_PXON;`
432			`P0_ONLY <= '1';`
433			`when 38 =>`
434			`-- pxoff`
435			`IMNMC <= IM_PXOFF;`
436			`P0_ONLY <= '1';`
437			`when others =>`
438			`IMNMC <= IM_BAD_INSTR;`
439			`end case;`
440
441			`when 1 =>`
442			`-- addi rD,rA,imm12`
443			`IMNMC <= IM_ADDI;`
444			`WRD <= '1';`
445			`RRA <= '1';`
446			`WOVF <= '1';`
447			`ALU_OP <= ALU_ADD;`
448
449			`when 2 =>`
450			`-- laddi rD,rA,imm12`
451			`IMNMC <= IM_LADDI;`
452			`WRD <= '1';`
453			`RRA <= '1';`
454			`LD <= '1';`
455			`LA <= '1';`
456			`LB <= '1';`
457			`WOVF <= '1';`
458			`ALU_OP <= ALU_LADD;`
459
460			`when 3 =>`
461			`-- subi rD,rA,imm12`
462			`IMNMC <= IM_SUBI;`
463			`WRD <= '1';`
464			`RRA <= '1';`
465			`WOVF <= '1';`
466			`ALU_OP <= ALU_SUB;`
467
468			`when 4 =>`
469			`-- lsubi rD,rA,imm12`
470			`IMNMC <= IM_LSUBI;`
471			`WRD <= '1';`
472			`RRA <= '1';`
473			`LD <= '1';`
474			`LA <= '1';`
475			`LB <= '1';`
476			`WOVF <= '1';`
477			`ALU_OP <= ALU_LSUB;`
478
479			`when 5 =>`
480			`-- muli rD,rA,imm12`
481			`IMNMC <= IM_MULI;`
482			`WRD <= '1';`
483			`RRA <= '1';`
484			`WOVF <= '1';`
485			`ALU_OP <= ALU_MUL;`
486
487			`when 6 =>`
488			`-- lmuli rD,rA,imm12`
489			`IMNMC <= IM_LMULI;`
490			`WRD <= '1';`
491			`RRA <= '1';`
492			`LD <= '1';`
493			`--LA <= '1';`
494			`--LB <= '1';`
495			`WOVF <= '1';`
496			`ALU_OP <= ALU_LMUL;`
497
498			`when 7 =>`
499			`-- lmulai rD,rA,imm12`
500			`IMNMC <= IM_MULAI;`
501			`WRD <= '1';`
502			`RRA <= '1';`
503			`ALU_OP <= ALU_MULA;`
504
505			`when 8 =>`
506			`-- RRI8 instructions`
507			`case OP2 is`
508			`when 0 =>`
509			`-- shli rD,rA,imm8`
510			`IMNMC <= IM_SHLI;`
511			`WRD <= '1';`
512			`RRA <= '1';`
513			`WOVF <= '1';`
514			`ALU_OP <= ALU_SHL;`
515			`when 1 =>`
516			`-- lshli rD,rA,imm8`
517			`IMNMC <= IM_LSHLI;`
518			`WRD <= '1';`
519			`RRA <= '1';`
520			`LD <= '1';`
521			`LA <= '1';`
522			`WOVF <= '1';`
523			`ALU_OP <= ALU_LSHL;`
524			`when 2 =>`
525			`-- shri rD,rA,imm8`
526			`IMNMC <= IM_SHRI;`
527			`WRD <= '1';`
528			`RRA <= '1';`
529			`ALU_OP <= ALU_SHR;`
530			`when 3 =>`
531			`-- lshri rD,rA,imm8`
532			`IMNMC <= IM_LSHRI;`
533			`WRD <= '1';`
534			`RRA <= '1';`
535			`LD <= '1';`
536			`LA <= '1';`
537			`ALU_OP <= ALU_LSHR;`
538			`--when 4 =>`
539			`-- -- andli rD,rA,imm8`
540			`-- IMNMC <= IM_ANDLI;`
541			`-- WRD <= '1';`
542			`-- RRA <= '1';`
543			`-- ALU_OP <= ALU_ANDL;`
544			`--when 5 =>`
545			`-- -- andhi rD,rA,imm8`
546			`-- IMNMC <= IM_ANDHI;`
547			`-- WRD <= '1';`
548			`-- RRA <= '1';`
549			`-- ALU_OP <= ALU_ANDH;`
550			`--when 6 =>`
551			`-- -- orli rD,rA,imm8`
552			`-- IMNMC <= IM_ORLI;`
553			`-- WRD <= '1';`
554			`-- RRA <= '1';`
555			`-- ALU_OP <= ALU_ORL;`
556			`--when 7 =>`
557			`-- -- orhi rD,rA,imm8`
558			`-- IMNMC <= IM_ORHI;`
559			`-- WRD <= '1';`
560			`-- RRA <= '1';`
561			`-- ALU_OP <= ALU_ORH;`
562			`when 8 =>`
563			`-- beq rA,rB,imm8`
564			`IMNMC <= IM_BEQ;`
565			`RRA <= '1';`
566			`RRB <= '1';`
567			`IMNMC <= IM_BEQ;`
568			`BJ_OP <= BJ_BEQ;`
569			`P0_ONLY <= '1';`
570			`when 9 =>`
571			`-- bne rA,rB,imm8`
572			`IMNMC <= IM_BNE;`
573			`RRA <= '1';`
574			`RRB <= '1';`
575			`BJ_OP <= BJ_BNE;`
576			`P0_ONLY <= '1';`
577			`when 10 =>`
578			`-- ld rD,rA,imm8`
579			`IMNMC <= IM_LD;`
580			`WRD <= '1';`
581			`RRA <= '1';`
582			`LS_OP <= LS_LD;`
583			`when 11 =>`
584			`-- st rA,rB,imm8`
585			`IMNMC <= IM_ST;`
586			`RRA <= '1';`
587			`RRB <= '1';`
588			`LS_OP <= LS_ST;`
589			`P0_ONLY <= '1';`
590			`--when 12 =>`
591			`-- -- ldpp rD,rA,imm8`
592			`-- IMNMC <= IM_LDPP;`
593			`-- WRD <= '1';`
594			`-- WRD2 <= '1';`
595			`-- RRA <= '1';`
596			`-- ALU_OP <= ALU_INC;`
597			`-- LS_OP <= LS_LD;`
598			`-- --SC <= '0';`
599			`--when 13 =>`
600			`-- -- stpp rA,rB,imm8`
601			`-- IMNMC <= IM_STPP;`
602			`-- WRD2 <= '1';`
603			`-- RRA <= '1';`
604			`-- RRB <= '1';`
605			`-- ALU_OP <= ALU_INC;`
606			`-- LS_OP <= LS_ST;`
607			`when others =>`
608			`IMNMC <= IM_BAD_INSTR;`
609			`end case;`
610
611			`when 9 =>`
612			`-- lmaci rD,rA,imm12`
613			`IMNMC <= IM_LMACI;`
614			`WRD <= '1';`
615			`RRA <= '1';`
616			`LD <= '1';`
617			`WACC <= '1';`
618			`WOVF <= '1';`
619			`ALU_OP <= ALU_LMAC;`
620
621			`when 10 =>`
622			`-- lmsui rD,rA,imm12`
623			`IMNMC <= IM_LMSUI;`
624			`WRD <= '1';`
625			`RRA <= '1';`
626			`LD <= '1';`
627			`WACC <= '1';`
628			`WOVF <= '1';`
629			`ALU_OP <= ALU_LMSU;`
630
631			`when 11 =>`
632			`-- jmpli rD,imm16`
633			`IMNMC <= IM_JMPLI;`
634			`WRD <= '1';`
635			`BJ_OP <= BJ_JIL;`
636			`ALU_OP <= ALU_MOVA;`
637			`P0_ONLY <= '1';`
638
639			`when 12 =>`
640			`-- RI12 or I16 instruction`
641			`case OP2 is`
642			`when 0 =>`
643			`-- blez rA,imm12`
644			`IMNMC <= IM_BLEZ;`
645			`RRA <= '1';`
646			`BJ_OP <= BJ_BLEZ;`
647			`P0_ONLY <= '1';`
648			`when 1 =>`
649			`-- lblez rA,imm12`
650			`IMNMC <= IM_LBLEZ;`
651			`RRA <= '1';`
652			`LA <= '1';`
653			`BJ_OP <= BJ_LBLEZ;`
654			`P0_ONLY <= '1';`
655			`when 2 =>`
656			`-- bgtz rA,imm12`
657			`IMNMC <= IM_BGTZ;`
658			`RRA <= '1';`
659			`BJ_OP <= BJ_BGTZ;`
660			`P0_ONLY <= '1';`
661			`when 3 =>`
662			`-- lbgtz rA,imm12`
663			`IMNMC <= IM_LBGTZ;`
664			`RRA <= '1';`
665			`LA <= '1';`
666			`BJ_OP <= BJ_LBGTZ;`
667			`P0_ONLY <= '1';`
668			`when 4 =>`
669			`-- bltz rA,imm12`
670			`IMNMC <= IM_BLTZ;`
671			`RRA <= '1';`
672			`BJ_OP <= BJ_BLTZ;`
673			`P0_ONLY <= '1';`
674			`when 5 =>`
675			`-- lbltz rA,imm12`
676			`IMNMC <= IM_LBLTZ;`
677			`RRA <= '1';`
678			`LA <= '1';`
679			`BJ_OP <= BJ_LBLTZ;`
680			`P0_ONLY <= '1';`
681			`when 6 =>`
682			`-- bgez rA,imm12`
683			`IMNMC <= IM_BGEZ;`
684			`RRA <= '1';`
685			`BJ_OP <= BJ_BGEZ;`
686			`P0_ONLY <= '1';`
687			`when 7 =>`
688			`-- lbgez rA,imm12`
689			`IMNMC <= IM_LBGEZ;`
690			`RRA <= '1';`
691			`LA <= '1';`
692			`BJ_OP <= BJ_LBGEZ;`
693			`P0_ONLY <= '1';`
694			`when 8 =>`
695			`-- jmpi imm16`
696			`IMNMC <= IM_JMPI;`
697			`BJ_OP <= BJ_JI;`
698			`P0_ONLY <= '1';`
699			`when 9 =>`
700			`-- llbri imm16`
701			`IMNMC <= IM_LLBRI;`
702			`P0_ONLY <= '1';`
703			`when 10 =>`
704			`-- lleri imm16`
705			`IMNMC <= IM_LLERI;`
706			`P0_ONLY <= '1';`
707			`when 11 =>`
708			`-- llcri imm16`
709			`IMNMC <= IM_LLCRI;`
710			`P0_ONLY <= '1';`
711			`when others =>`
712			`IMNMC <= IM_BAD_INSTR;`
713			`end case;`
714
715			`when 13 =>`
716			`-- movi rD,imm16`
717			`IMNMC <= IM_MOVI;`
718			`WRD <= '1';`
719			`ALU_OP <= ALU_MOVB;`
720
721			`when others =>`
722			`-- invalid instruction`
723			`IMNMC <= IM_BAD_INSTR;`
724
725			`end case;`
726			`end process;`
727
728			`OPB_IMM_o <= '0' when`
729			`(OP1 = 0) or`
730			`((OP1 = 8) and (OP2 = 8 or OP2 = 9 or OP2 = 11 or OP2 = 13))`
731			`else '1';`
732
733			`-- Operand B selector`
734			`process(OP1,OP2,OP2_RRR,IMM8,IMM12,IMM12_S,IMM16,IMM16_S)`
735			`begin`
736			`case OP1 is`
737			`when 1\|2\|3\|4\|5\|6\|7\|9\|10 =>`
738			`OPB_o <= EXTS32(IMM12);`
739			`when 8 =>`
740			`OPB_o <= EXTS32(IMM8);`
741			`when 11\|13 =>`
742			`OPB_o <= EXTS32(IMM16);`
743			`when 12 =>`
744			`if(OP2 = 8 or OP2 = 9 or OP2 = 10 or OP2 = 11) then`
745			`OPB_o <= EXTS32(IMM16_S);`
746			`else`
747			`OPB_o <= EXTS32(IMM12_S);`
748			`end if;`
749			`when others =>`
750			`OPB_o <= (others => '0');`
751			`end case;`
752			`end process;`
753
754			`IMM <= (others => '0');`
755
756			`-- decoded instruction`
757			`DEC_INSTR_o <= (`
758			`IMNMC,`
759			`WRD,`
760			`RRA,`
761			`RRB,`
762			`RD,`
763			`RA,`
764			`RB,`
765			`IMM,`
766			`LD,`
767			`LA,`
768			`LB,`
769			`ALU_OP,`
770			`BJ_OP,`
771			`LS_OP,`
772			`WOVF,`
773			`WACC,`
774			`P0_ONLY`
775			`);`
776
777			`end ARC;`