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axuan25268 |
-------------------------------------------------------------------------------
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-- Title :
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-- Project :
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-------------------------------------------------------------------------------
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-- File : rgmii_mdio.vhd
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-- Author : liyi <alxiuyain@foxmail.com>
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-- Company : OE@HUST
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-- Created : 2012-12-02
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-- Last update: 2012-12-02
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2012 OE@HUST
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2012-12-02 1.0 liyi Created
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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-------------------------------------------------------------------------------
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ENTITY rgmii_mdio IS
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PORT (
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iWbClk : IN STD_LOGIC;
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iRst_n : IN STD_LOGIC;
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---------------------------------------------------------------------------
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-- signals from register file
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---------------------------------------------------------------------------
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iPHYAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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iRegAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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iNoPre : IN STD_LOGIC;
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iData2PHY : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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iClkDiv : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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iRdOp : IN STD_LOGIC;
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iWrOp : IN STD_LOGIC;
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---------------------------------------------------------------------------
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-- signals to register file
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---------------------------------------------------------------------------
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oDataFromPHY : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- data from PHY registers
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oDataFromPHYValid : OUT STD_LOGIC; -- only valid for 1 clock cycle
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oClrRdOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
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oClrWrOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
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oMDIOBusy : OUT STD_LOGIC; -- manegement is busy
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---------------------------------------------------------------------------
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-- Management interface
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---------------------------------------------------------------------------
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iMDI : IN STD_LOGIC;
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oMDHz : OUT STD_LOGIC; -- mdio is in HighZ state
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oMDC : OUT STD_LOGIC
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);
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END ENTITY rgmii_mdio;
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-------------------------------------------------------------------------------
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ARCHITECTURE rtl OF rgmii_mdio IS
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SIGNAL rdPend, wrPend : STD_LOGIC;
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SIGNAL endOp : STD_LOGIC;
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SIGNAL busy : STD_LOGIC;
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SIGNAL sendEn : BOOLEAN; -- Data is output on sendEn. Delay it slightly from the
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--clock to ensure setup and hold timing is met
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SIGNAL receiveEn : BOOLEAN; -- Sample read data just before rising edge of MDC
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BEGIN -- ARCHITECTURE rtl
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-----------------------------------------------------------------------------
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-- receive command from wishbone
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-----------------------------------------------------------------------------
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oMDIOBusy <= busy;
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busy <= wrPend OR rdPend;
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PROCESS (iWbClk, iRst_n) IS
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BEGIN
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IF iRst_n = '0' THEN
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rdPend <= '0';
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wrPend <= '0';
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oClrWrOp <= '0';
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oClrRdOp <= '0';
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ELSIF rising_edge(iWbClk) THEN
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oClrWrOp <= '0';
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oClrRdOp <= '0';
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IF busy = '0' THEN
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IF iRdOp = '1' THEN
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rdPend <= '1';
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oClrRdOp <= '1';
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ELSIF iWrOp = '1' THEN
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wrPend <= '1';
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oClrWrOp <= '1';
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END IF;
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ELSIF endOp = '1' THEN
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rdPend <= '0';
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wrPend <= '0';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- MDC generation
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-----------------------------------------------------------------------------
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mdcGen : BLOCK IS
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SIGNAL mdc : STD_LOGIC;
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SIGNAL mdcClkDiv : INTEGER RANGE 0 TO 127;
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SIGNAL clkDivTmp : INTEGER RANGE 0 TO 126;
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BEGIN -- BLOCK mdc
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oMDC <= mdc;
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clkDivTmp <= 1 WHEN iClkDiv < 4 ELSE (conv_integer(iClkDiv(7 DOWNTO 1))-1);
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sendEn <= mdc = '1' AND mdcClkDiv = 0; -- falling edge send
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receiveEn <= mdc = '0' AND mdcClkDiv = 0; -- rising edge receive
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PROCESS (iWbClk, iRst_n) IS
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BEGIN
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IF iRst_n = '0' THEN
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mdc <= '0';
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mdcClkDiv <= 0;
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ELSIF rising_edge(iWbClk) THEN
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IF mdcClkDiv = 0 THEN
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mdcClkDiv <= clkDivTmp;
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mdc <= NOT mdc;
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ELSE
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mdcClkDiv <= mdcClkDiv - 1;
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END IF;
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END IF;
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END PROCESS;
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END BLOCK mdcGen;
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operation : BLOCK IS
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TYPE state_t IS (PREAMBLE, IDLE, CTRL, WRITE, READ);
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SIGNAL state : state_t;
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SIGNAL bitCnt : INTEGER RANGE 0 TO 31;
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SIGNAL shiftReg : STD_LOGIC_VECTOR(15 DOWNTO 0);
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BEGIN -- BLOCK operation
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PROCESS (iWbClk, iRst_n) IS
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BEGIN
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IF iRst_n = '0' THEN
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oMDHz <= '1';
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state <= PREAMBLE;
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endOp <= '0';
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bitCnt <= 0;
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shiftReg <= (OTHERS => '0');
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oDataFromPHYValid <= '0';
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oDataFromPHY <= (OTHERS => '0');
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ELSIF rising_edge(iWbClk) THEN
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endOp <= '0';
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oDataFromPHYValid <= '0';
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CASE state IS
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WHEN PREAMBLE =>
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IF sendEn THEN
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bitCnt <= bitCnt + 1;
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oMDHz <= '1';
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IF bitCnt = 30 THEN
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state <= IDLE;
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END IF;
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END IF;
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WHEN IDLE =>
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IF sendEn THEN
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IF busy = '1' THEN -- start transaction
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oMDHz <= '0'; -- firstbit of start word
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state <= CTRL;
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bitCnt <= 0;
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shiftReg <= iData2PHY;
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END IF;
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END IF;
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WHEN CTRL =>
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IF sendEn THEN
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bitCnt <= bitCnt + 1;
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CASE bitCnt IS
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WHEN 0 => oMDHz <= '1'; -- second bit of start word
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-- OPCODE. 1 then 0 for read, 0 then 1 for write
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WHEN 1 => oMDHz <= rdPend;
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WHEN 2 => oMDHz <= NOT rdPend;
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-- PHY address
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WHEN 3 => oMDHz <= iPHYAddr(4);
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WHEN 4 => oMDHz <= iPHYAddr(3);
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WHEN 5 => oMDHz <= iPHYAddr(2);
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WHEN 6 => oMDHz <= iPHYAddr(1);
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WHEN 7 => oMDHz <= iPHYAddr(0);
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-- Register address
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WHEN 8 => oMDHz <= iRegAddr(4);
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WHEN 9 => oMDHz <= iRegAddr(3);
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WHEN 10 => oMDHz <= iRegAddr(2);
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WHEN 11 => oMDHz <= iRegAddr(1);
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WHEN 12 => oMDHz <= iRegAddr(0);
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-- TA
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WHEN 13 => oMDHz <= '1';
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WHEN 14 =>
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IF rdPend = '0' THEN
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state <= WRITE;
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oMDHz <= '0';
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bitCnt <= 0;
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END IF;
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WHEN 15 =>
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state <= READ;
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bitCnt <= 0;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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WHEN WRITE =>
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IF sendEn THEN
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oMDHz <= shiftReg(15);
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shiftReg <= shiftReg(14 DOWNTO 0) & '0';
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bitCnt <= bitCnt + 1;
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IF bitCnt = 15 THEN
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endOp <= '1';
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bitCnt <= 0;
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IF iNoPre = '1' THEN
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state <= IDLE;
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ELSE
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state <= PREAMBLE;
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END IF;
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END IF;
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END IF;
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WHEN READ =>
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IF receiveEn THEN
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bitCnt <= bitCnt + 1;
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shiftReg <= shiftReg(14 DOWNTO 0) & iMDI;
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IF bitCnt = 15 THEN
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bitCnt <= 0;
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endOp <= '1';
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oDataFromPHY <= shiftReg(14 DOWNTO 0) & iMDI;
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oDataFromPHYValid <= '1';
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IF iNoPre = '1' THEN
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state <= IDLE;
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ELSE
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state <= PREAMBLE;
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END IF;
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END IF;
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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END BLOCK operation;
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END ARCHITECTURE rtl;
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