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nussgipfel |
-- GECKO3COM IP Core
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--
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-- Copyright (C) 2009 by
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-- ___ ___ _ _
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-- ( _ \ ( __)( ) ( )
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-- | (_) )| ( | |_| | Bern University of Applied Sciences
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-- | _ < | _) | _ | School of Engineering and
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-- | (_) )| | | | | | Information Technology
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-- (____/ (_) (_) (_)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- URL to the project description:
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-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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--------------------------------------------------------------------------------
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--
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-- Author: Christoph Zimmermann
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-- Date of creation: 16:52:52 01/28/2010
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-- Description:
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-- This is the top module for the GECKO3com simple IP core.
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-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
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--
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-- This core provides a simple FIFO and register interface to the
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-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
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--
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-- Look at GECKO3COM_loopback.vhd for an example how to use it.
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--
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-- Target Devices: general
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-- Tool versions: 11.1
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-- Dependencies: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library work;
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use work.GECKO3COM_defines.all;
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entity GECKO3COM_simple_datapath is
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generic (
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BUSWIDTH : integer := 16);
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port (
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i_nReset : in std_logic;
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i_sysclk : in std_logic;
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i_rx_data : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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o_tx_data : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_receive_fifo_rd_en : in std_logic;
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i_receive_fifo_wr_en : in std_logic;
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o_receive_fifo_empty : out std_logic;
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o_receive_fifo_full : out std_logic;
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o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
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i_receive_fifo_reset : in std_logic;
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o_receive_transfersize : out std_logic_vector(31 downto 0);
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i_receive_transfersize_en : in std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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i_receive_counter_load : in std_logic;
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i_receive_counter_en : in std_logic;
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o_receive_counter_zero : out std_logic;
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o_dev_dep_msg_out : out std_logic;
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o_request_dev_dep_msg_in : out std_logic;
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i_btag_reg_en : in std_logic;
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i_nbtag_reg_en : in std_logic;
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o_btag_correct : out std_logic;
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o_eom_bit_detected : out std_logic;
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i_send_fifo_rd_en : in std_logic;
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i_send_fifo_wr_en : in std_logic;
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o_send_fifo_empty : out std_logic;
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o_send_fifo_full : out std_logic;
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i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_send_fifo_reset : in std_logic;
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i_send_transfersize : in std_logic_vector(31 downto 0);
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i_send_transfersize_en : in std_logic;
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i_send_counter_load : in std_logic;
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i_send_counter_en : in std_logic;
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o_send_counter_zero : out std_logic;
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i_send_mux_sel : in std_logic_vector(2 downto 0);
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i_receive_newdata_set : in std_logic;
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o_receive_newdata : out std_logic;
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i_receive_end_of_message_set : in std_logic;
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o_receive_end_of_message : out std_logic;
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i_send_data_request_set : in std_logic;
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o_send_data_request : out std_logic);
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end GECKO3COM_simple_datapath;
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architecture behaviour of GECKO3COM_simple_datapath is
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-----------------------------------------------------------------------------
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-- COMPONENTS
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-----------------------------------------------------------------------------
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component receive_fifo
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generic (
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BUSWIDTH : integer);
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port (
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i_din : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_clk : in std_logic;
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i_rd_en : in std_logic;
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i_rst : in std_logic;
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i_wr_en : in std_logic;
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o_dout : out std_logic_vector(BUSWIDTH-1 downto 0);
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o_empty : out std_logic;
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o_full : out std_logic);
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end component;
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component send_fifo
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generic (
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BUSWIDTH : integer);
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port (
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i_din : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_clk : in std_logic;
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i_rd_en : in std_logic;
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i_rst : in std_logic;
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i_wr_en : in std_logic;
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o_dout : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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o_empty : out std_logic;
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o_full : out std_logic);
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end component;
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-----------------------------------------------------------------------------
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-- interconection signals
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-----------------------------------------------------------------------------
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signal s_receive_transfersize : std_logic_vector(31 downto 0);
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signal s_send_transfersize_reg: std_logic_vector(31 downto 0);
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signal s_receive_transfersize_count: std_logic_vector(31 downto 0);
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signal s_send_transfersize_count: std_logic_vector(31 downto 0);
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signal s_receive_fifo_empty : std_logic;
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signal s_send_fifo_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_btag, s_nbtag : std_logic_vector(7 downto 0);
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begin -- behaviour
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receive_fifo_1 : receive_fifo
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generic map (
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BUSWIDTH => BUSWIDTH)
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port map (
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i_din => i_rx_data,
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i_clk => i_sysclk,
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i_rd_en => i_receive_fifo_rd_en,
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i_rst => i_nReset,
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i_wr_en => i_receive_fifo_wr_en,
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o_dout => o_receive_fifo_data,
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o_empty => s_receive_fifo_empty,
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o_full => o_receive_fifo_full);
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send_fifo_1 : send_fifo
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generic map (
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BUSWIDTH => BUSWIDTH)
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port map (
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i_din => i_send_fifo_data,
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i_clk => i_sysclk,
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i_rd_en => i_send_fifo_rd_en,
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i_rst => i_nReset,
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i_wr_en => i_send_fifo_wr_en,
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o_dout => s_send_fifo_data,
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o_empty => o_send_fifo_empty,
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o_full => o_send_fifo_full);
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o_receive_fifo_empty <= s_receive_fifo_empty;
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-- purpose: process to fill the 32 bit receive_transfersize register with 8
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-- or 16 bit wide input data.
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, i_rx_data, i_receive_transfersize_en
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receive_transfersize: process (i_sysclk, i_nReset)
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begin -- process registers
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_receive_transfersize <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_receive_transfersize_en(0) = '1' then
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s_receive_transfersize(15 downto 0) <= i_rx_data;
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end if;
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if i_receive_transfersize_en(1) = '1' then
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s_receive_transfersize(31 downto 16) <= i_rx_data;
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end if;
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end if;
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end process receive_transfersize;
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o_receive_transfersize <= s_receive_transfersize;
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-- purpose: 32 bit send_transfersize register
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, i_send_transfersize, i_receive_transfersize_en
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send_transfersize: process (i_sysclk, i_nReset)
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begin -- process registers
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_send_transfersize_reg <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_send_transfersize_en = '1' then
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s_send_transfersize_reg <= i_send_transfersize;
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end if;
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end if;
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end process send_transfersize;
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-- purpose: down counter for the receive transfer size
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, s_reveive_transfersize,
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-- i_receive_transfersize_en
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-- outputs: s_receive_transfersize_count
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receive_counter : process (i_sysclk, i_nReset)
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begin -- process receive_counter
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_receive_transfersize_count <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_receive_counter_load = '1' then
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s_receive_transfersize_count <= s_receive_transfersize;
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end if;
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if i_receive_counter_en = '1' then
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s_receive_transfersize_count <= s_receive_transfersize_count - 1;
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end if;
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end if;
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end process receive_counter;
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o_receive_counter_zero <=
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'1' when s_receive_transfersize_count = x"0000" else
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'0';
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-- purpose: down counter for the send transfer size
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, s_send_transfersize_reg,
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-- i_send_transfersize_en
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-- outputs: s_send_transfersize_count
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send_counter : process (i_sysclk, i_nReset)
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begin -- process receive_counter
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_send_transfersize_count <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_send_counter_load = '1' then
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s_receive_transfersize_count <= s_send_transfersize_reg;
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end if;
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if i_send_counter_en = '1' then
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s_send_transfersize_count <= s_send_transfersize_count - 1;
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end if;
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end if;
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end process send_counter;
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o_send_counter_zero <=
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'1' when s_send_transfersize_count = x"0000" else
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'0';
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-- purpose: registers to store the btag and inverse btag
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, i_btag_reg_en, i_nbtag_reg_en
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-- i_rx_data
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-- outputs: s_btag, s_nbtag
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btag_register : process (i_sysclk, i_nReset)
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begin -- process receive_counter
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_btag <= (others => '0');
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s_nbtag <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_btag_reg_en = '1' then
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s_btag <= i_rx_data(15 downto 8);
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end if;
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if i_nbtag_reg_en = '1' then
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s_nbtag <= i_rx_data(7 downto 0);
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end if;
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end if;
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end process btag_register;
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o_btag_correct <=
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'1' when s_btag = not s_nbtag else
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'0';
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o_dev_dep_msg_out <=
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'1' when i_rx_data(7 downto 0) = x"01" else
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'0';
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o_request_dev_dep_msg_in <=
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'1' when i_rx_data(7 downto 0) = x"02" else
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'0';
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o_eom_bit_detected <=
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'1' when i_rx_data(15 downto 8) = b"00000001" else
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'0';
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-- purpose: mulitiplexer to construct the tmc header structure
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-- type : combinational
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-- inputs : i_send_mux_sel, s_btag, s_nbtag, s_send_fifo_data,
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-- s_send_transfersize_reg
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-- outputs: o_tx_data
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tx_data_mux: process (i_send_mux_sel, s_btag, s_nbtag, s_send_fifo_data,
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s_send_transfersize_reg)
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begin -- process tx_data_mux
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case i_send_mux_sel is
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when "000" => o_tx_data <= x"02" & s_btag; -- MsgID and stored bTag
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when "001" => o_tx_data <= s_nbtag & x"00"; -- inverted bTag and Reserved
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when "010" => o_tx_data <= s_send_transfersize_reg(15 downto 0);
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when "011" => o_tx_data <= s_send_transfersize_reg(31 downto 16);
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when "100" => o_tx_data <= x"0001"; -- TransferAttributes: EOM = 1
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when "101" => o_tx_data <= x"0000"; -- Header byte 10 and 11, Reserved
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when "110" => o_tx_data <= s_send_fifo_data; -- message data
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when others => o_tx_data <= s_send_fifo_data;
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324 |
|
|
end case;
|
325 |
|
|
end process tx_data_mux;
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
-- purpose: set and reset behavour for the status flags
|
329 |
|
|
-- type : sequential
|
330 |
|
|
-- inputs : i_sysclk, i_nReset, i_receive_newdata_set,
|
331 |
|
|
-- i_receive_end_of_message_set, s_send_data_request_set,
|
332 |
|
|
-- i_receive_fifo_rd_en, s_receive_fifo_empty, i_send_fifo_wr_en
|
333 |
|
|
-- outputs: o_receive_newdata, o_receive_end_of_message, o_send_data_request
|
334 |
|
|
gecko3com_simple_flags: process (i_sysclk, i_nReset)
|
335 |
|
|
begin -- process gecko3com_simple_flags
|
336 |
|
|
if i_nReset = '0' then -- asynchronous reset (active low)
|
337 |
|
|
o_receive_newdata <= '0';
|
338 |
|
|
o_receive_end_of_message <= '0';
|
339 |
|
|
o_send_data_request <= '0';
|
340 |
|
|
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
|
341 |
|
|
if i_receive_newdata_set = '1' then
|
342 |
|
|
o_receive_newdata <= '1';
|
343 |
|
|
end if;
|
344 |
|
|
if i_receive_fifo_rd_en = '1' then
|
345 |
|
|
o_receive_newdata <= '0';
|
346 |
|
|
end if;
|
347 |
|
|
|
348 |
|
|
if i_receive_end_of_message_set = '1' then
|
349 |
|
|
o_receive_end_of_message <= '1';
|
350 |
|
|
end if;
|
351 |
|
|
if s_receive_fifo_empty = '1' then
|
352 |
|
|
o_receive_end_of_message <= '0';
|
353 |
|
|
end if;
|
354 |
|
|
|
355 |
|
|
if i_send_data_request_set = '1' then
|
356 |
|
|
o_send_data_request <= '1';
|
357 |
|
|
end if;
|
358 |
|
|
if i_send_fifo_wr_en = '1' then
|
359 |
|
|
o_send_data_request <= '0';
|
360 |
|
|
end if;
|
361 |
|
|
end if;
|
362 |
|
|
end process gecko3com_simple_flags;
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
end behaviour;
|