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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3COM_simple_datapath.vhd] - Blame information for rev 24

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1 22 nussgipfel
--  GECKO3COM IP Core
2
--
3
--  Copyright (C) 2009 by
4
--   ___    ___   _   _
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--  (  _ \ (  __)( ) ( )
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--  | (_) )| (   | |_| |   Bern University of Applied Sciences
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--  |  _ < |  _) |  _  |   School of Engineering and
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--  | (_) )| |   | | | |   Information Technology
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--  (____/ (_)   (_) (_)
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--
11
--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
17
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
18
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details. 
20
--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
22
--
23
--  URL to the project description: 
24
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
25
--------------------------------------------------------------------------------
26
--
27
--  Author:  Christoph Zimmermann
28
--  Date of creation:  16:52:52 01/28/2010 
29
--  Description:
30
--      This is the top module for the GECKO3com simple IP core.
31
--      Not the one for Xilinx EDK (with PLB bus), for processor less designs.
32
--
33
--      This core provides a simple FIFO and register interface to the
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--      USB data transfer capabilities of the GECKO3COM/GECKO3main system.
35
--
36 23 nussgipfel
--      Look at GECKO3COM_simple_test.vhd for an example how to use it.
37 22 nussgipfel
--
38
--  Target Devices:     general
39
--  Tool versions:      11.1
40
--  Dependencies:       Xilinx FPGA's Spartan3 and up or Virtex4 and up.
41
--
42
--------------------------------------------------------------------------------
43
 
44
library IEEE;
45
use IEEE.STD_LOGIC_1164.all;
46
use IEEE.STD_LOGIC_ARITH.all;
47
use IEEE.STD_LOGIC_UNSIGNED.all;
48
 
49
library work;
50
use work.GECKO3COM_defines.all;
51
 
52
 
53
entity GECKO3COM_simple_datapath is
54
 
55
  generic (
56
    BUSWIDTH : integer := 16);
57
 
58
  port (
59
    i_nReset  : in  std_logic;
60
    i_sysclk  : in  std_logic;
61
    i_rx_data : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
62
    o_tx_data : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
63
 
64
    i_receive_fifo_rd_en      : in  std_logic;
65
    i_receive_fifo_wr_en      : in  std_logic;
66
    o_receive_fifo_empty      : out std_logic;
67
    o_receive_fifo_full       : out std_logic;
68
    o_receive_fifo_data       : out std_logic_vector(BUSWIDTH-1 downto 0);
69
    i_receive_fifo_reset      : in  std_logic;
70
    o_receive_transfersize    : out std_logic_vector(31 downto 0);
71
    i_receive_transfersize_en : in  std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
72
    i_receive_counter_load    : in  std_logic;
73
    i_receive_counter_en      : in  std_logic;
74
    o_receive_counter_zero    : out std_logic;
75
    o_dev_dep_msg_out         : out std_logic;
76
    o_request_dev_dep_msg_in  : out std_logic;
77
    i_btag_reg_en             : in  std_logic;
78
    i_nbtag_reg_en            : in  std_logic;
79
    o_btag_correct            : out std_logic;
80
    o_eom_bit_detected        : out std_logic;
81
 
82
    i_send_fifo_rd_en      : in  std_logic;
83
    i_send_fifo_wr_en      : in  std_logic;
84
    o_send_fifo_empty      : out std_logic;
85
    o_send_fifo_full       : out std_logic;
86
    i_send_fifo_data       : in  std_logic_vector(BUSWIDTH-1 downto 0);
87
    i_send_fifo_reset      : in  std_logic;
88
    i_send_transfersize    : in  std_logic_vector(31 downto 0);
89
    i_send_transfersize_en : in  std_logic;
90 23 nussgipfel
    i_send_have_more_data  : in  std_logic;
91 22 nussgipfel
    i_send_counter_load    : in  std_logic;
92
    i_send_counter_en      : in  std_logic;
93
    o_send_counter_zero    : out std_logic;
94
    i_send_mux_sel         : in  std_logic_vector(2 downto 0);
95
 
96
    i_receive_newdata_set        : in  std_logic;
97
    o_receive_newdata            : out std_logic;
98
    i_receive_end_of_message_set : in  std_logic;
99
    o_receive_end_of_message     : out std_logic;
100
    i_send_data_request_set      : in  std_logic;
101
    o_send_data_request          : out std_logic);
102
 
103
end GECKO3COM_simple_datapath;
104
 
105
architecture behaviour of GECKO3COM_simple_datapath is
106
 
107
  -----------------------------------------------------------------------------
108
  -- COMPONENTS
109
  -----------------------------------------------------------------------------
110
 
111
  component receive_fifo
112
    generic (
113
      BUSWIDTH : integer);
114
    port (
115
      i_din    : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
116
      i_clk    : in  std_logic;
117
      i_rd_en  : in  std_logic;
118
      i_rst    : in  std_logic;
119
      i_wr_en  : in  std_logic;
120
      o_dout   : out std_logic_vector(BUSWIDTH-1 downto 0);
121
      o_empty  : out std_logic;
122
      o_full   : out std_logic);
123
  end component;
124
 
125
  component send_fifo
126
    generic (
127
      BUSWIDTH : integer);
128
    port (
129
      i_din    : in  std_logic_vector(BUSWIDTH-1 downto 0);
130
      i_clk    : in  std_logic;
131
      i_rd_en  : in  std_logic;
132
      i_rst    : in  std_logic;
133
      i_wr_en  : in  std_logic;
134
      o_dout   : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
135
      o_empty  : out std_logic;
136
      o_full   : out std_logic);
137
  end component;
138
 
139
 
140
  -----------------------------------------------------------------------------
141
  -- interconection signals
142
  -----------------------------------------------------------------------------
143
 
144
  signal s_receive_transfersize : std_logic_vector(31 downto 0);
145
  signal s_send_transfersize_reg: std_logic_vector(31 downto 0);
146
 
147
  signal s_receive_transfersize_count: std_logic_vector(31 downto 0);
148
  signal s_send_transfersize_count: std_logic_vector(31 downto 0);
149
 
150
  signal s_receive_fifo_empty : std_logic;
151
 
152
  signal s_send_fifo_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
153 23 nussgipfel
  signal s_btag, s_nbtag, s_msg_id: std_logic_vector(7 downto 0);
154 22 nussgipfel
 
155
begin  -- behaviour
156
 
157
  receive_fifo_1 : receive_fifo
158
    generic map (
159
      BUSWIDTH => BUSWIDTH)
160
    port map (
161
      i_din   => i_rx_data,
162
      i_clk   => i_sysclk,
163
      i_rd_en => i_receive_fifo_rd_en,
164 24 nussgipfel
      i_rst   => i_receive_fifo_reset,
165 22 nussgipfel
      i_wr_en => i_receive_fifo_wr_en,
166
      o_dout  => o_receive_fifo_data,
167
      o_empty => s_receive_fifo_empty,
168
      o_full  => o_receive_fifo_full);
169
 
170
  send_fifo_1 : send_fifo
171
    generic map (
172
      BUSWIDTH => BUSWIDTH)
173
    port map (
174
      i_din   => i_send_fifo_data,
175
      i_clk   => i_sysclk,
176
      i_rd_en => i_send_fifo_rd_en,
177 24 nussgipfel
      i_rst   => i_send_fifo_reset,
178 22 nussgipfel
      i_wr_en => i_send_fifo_wr_en,
179
      o_dout  => s_send_fifo_data,
180
      o_empty => o_send_fifo_empty,
181
      o_full  => o_send_fifo_full);
182
 
183
 
184
  o_receive_fifo_empty <= s_receive_fifo_empty;
185
 
186
  -- purpose: process to fill the 32 bit receive_transfersize register with 8
187
  --          or 16 bit wide input data.
188
  -- type   : sequential
189
  -- inputs : i_sysclk, i_nReset, i_rx_data, i_receive_transfersize_en
190
  receive_transfersize: process (i_sysclk, i_nReset)
191
  begin  -- process registers
192
    if i_nReset = '0' then              -- asynchronous reset (active low)
193
      s_receive_transfersize <= (others => '0');
194
    elsif i_sysclk'event and i_sysclk = '1' then  -- rising clock edge
195
      if i_receive_transfersize_en(0) = '1' then
196
        s_receive_transfersize(15 downto 0) <= i_rx_data;
197
      end if;
198
      if i_receive_transfersize_en(1) = '1' then
199
        s_receive_transfersize(31 downto 16) <= i_rx_data;
200
      end if;
201
    end if;
202
  end process receive_transfersize;
203
 
204
  o_receive_transfersize <= s_receive_transfersize;
205
 
206
 
207
  -- purpose: 32 bit send_transfersize register
208
  -- type   : sequential
209
  -- inputs : i_sysclk, i_nReset, i_send_transfersize, i_receive_transfersize_en
210
  send_transfersize: process (i_sysclk, i_nReset)
211
  begin  -- process registers
212
    if i_nReset = '0' then              -- asynchronous reset (active low)
213
      s_send_transfersize_reg <= (others => '0');
214
    elsif i_sysclk'event and i_sysclk = '1' then  -- rising clock edge
215
      if i_send_transfersize_en = '1' then
216
        s_send_transfersize_reg <= i_send_transfersize;
217
      end if;
218
    end if;
219
  end process send_transfersize;
220
 
221
 
222
  -- purpose: down counter for the receive transfer size
223
  -- type   : sequential
224
  -- inputs : i_sysclk, i_nReset, s_reveive_transfersize,
225
  --          i_receive_transfersize_en
226
  -- outputs: s_receive_transfersize_count
227
  receive_counter : process (i_sysclk, i_nReset)
228
  begin  -- process receive_counter
229
    if i_nReset = '0' then              -- asynchronous reset (active low)
230
      s_receive_transfersize_count <= (others => '0');
231
    elsif i_sysclk'event and i_sysclk = '1' then  -- rising clock edge
232
      if i_receive_counter_load = '1' then
233
        s_receive_transfersize_count <= s_receive_transfersize;
234
      end if;
235
      if i_receive_counter_en = '1' then
236
        s_receive_transfersize_count <= s_receive_transfersize_count - 1;
237
      end if;
238
    end if;
239
  end process receive_counter;
240
 
241
  o_receive_counter_zero <=
242
    '1' when s_receive_transfersize_count = x"0000" else
243
    '0';
244
 
245
 
246
  -- purpose: down counter for the send transfer size
247
  -- type   : sequential
248
  -- inputs : i_sysclk, i_nReset, s_send_transfersize_reg,
249
  --          i_send_transfersize_en
250
  -- outputs: s_send_transfersize_count
251
  send_counter : process (i_sysclk, i_nReset)
252 23 nussgipfel
  begin  -- process send_counter
253 22 nussgipfel
    if i_nReset = '0' then              -- asynchronous reset (active low)
254
      s_send_transfersize_count <= (others => '0');
255
    elsif i_sysclk'event and i_sysclk = '1' then  -- rising clock edge
256
      if i_send_counter_load = '1' then
257 23 nussgipfel
        s_send_transfersize_count <= s_send_transfersize_reg;
258 22 nussgipfel
      end if;
259
      if i_send_counter_en = '1' then
260
        s_send_transfersize_count <= s_send_transfersize_count - 1;
261
      end if;
262
    end if;
263
  end process send_counter;
264
 
265
  o_send_counter_zero <=
266
    '1' when s_send_transfersize_count = x"0000" else
267
    '0';
268
 
269
 
270
  -- purpose: registers to store the btag and inverse btag
271
  -- type   : sequential
272
  -- inputs : i_sysclk, i_nReset, i_btag_reg_en, i_nbtag_reg_en
273
  --          i_rx_data
274
  -- outputs: s_btag, s_nbtag
275
  btag_register : process (i_sysclk, i_nReset)
276 23 nussgipfel
  begin  -- process btag_register
277 22 nussgipfel
    if i_nReset = '0' then              -- asynchronous reset (active low)
278
      s_btag <= (others => '0');
279 23 nussgipfel
      s_msg_id <= (others => '0');
280 22 nussgipfel
      s_nbtag <= (others => '0');
281
    elsif i_sysclk'event and i_sysclk = '1' then  -- rising clock edge
282
      if i_btag_reg_en = '1' then
283
        s_btag <= i_rx_data(15 downto 8);
284 23 nussgipfel
        s_msg_id <= i_rx_data(7 downto 0);
285 22 nussgipfel
      end if;
286
      if   i_nbtag_reg_en = '1' then
287
        s_nbtag <= i_rx_data(7 downto 0);
288
      end if;
289
    end if;
290
  end process btag_register;
291
 
292
  o_btag_correct <=
293
    '1' when s_btag = not s_nbtag else
294
    '0';
295
 
296
 
297
  o_dev_dep_msg_out <=
298 23 nussgipfel
    '1' when s_msg_id(7 downto 0) = x"01" else
299 22 nussgipfel
    '0';
300
 
301
  o_request_dev_dep_msg_in <=
302 23 nussgipfel
    '1' when s_msg_id(7 downto 0) = x"02" else
303 22 nussgipfel
    '0';
304
 
305
  o_eom_bit_detected <=
306
    '1' when i_rx_data(15 downto 8) = b"00000001" else
307
    '0';
308
 
309
 
310
  -- purpose: mulitiplexer to construct the tmc header structure
311
  -- type   : combinational
312 24 nussgipfel
  -- inputs : i_send_mux_sel, i_send_have_more_data, s_btag, s_nbtag,
313
  --          s_send_fifo_data, s_send_transfersize_reg
314 22 nussgipfel
  -- outputs: o_tx_data
315 24 nussgipfel
  tx_data_mux: process (i_send_mux_sel, i_send_have_more_data, s_btag,
316
                        s_nbtag, s_send_fifo_data, s_send_transfersize_reg)
317 22 nussgipfel
  begin  -- process tx_data_mux
318
    case i_send_mux_sel is
319
      when "000" => o_tx_data <= x"02" & s_btag;  -- MsgID and stored bTag
320
      when "001" => o_tx_data <= s_nbtag & x"00"; -- inverted bTag and Reserved
321
      when "010" => o_tx_data <= s_send_transfersize_reg(15 downto 0);
322
      when "011" => o_tx_data <= s_send_transfersize_reg(31 downto 16);
323 23 nussgipfel
                    --TransferAttributes EOM bit:
324
      when "100" => o_tx_data <= b"000000000000000" & i_send_have_more_data;
325 22 nussgipfel
      when "101" => o_tx_data <= x"0000";  -- Header byte 10 and 11, Reserved
326
      when "110" => o_tx_data <= s_send_fifo_data;  -- message data
327
      when others => o_tx_data <= s_send_fifo_data;
328
    end case;
329
  end process tx_data_mux;
330
 
331
 
332 23 nussgipfel
  -- purpose: set and reset behavour for the status flags
333
  -- type   : sequential
334
  -- inputs : i_sysclk, i_nReset, i_receive_newdata_set,
335
  --          i_receive_end_of_message_set, s_send_data_request_set,
336
  --          i_receive_fifo_rd_en, s_receive_fifo_empty, i_send_fifo_wr_en
337
  -- outputs: o_receive_newdata, o_receive_end_of_message, o_send_data_request
338
  gecko3com_simple_flags : process (i_sysclk, i_nReset)
339
    variable v_receive_fifo_empty_old : std_logic;
340
  begin  -- process gecko3com_simple_flags
341
    if i_nReset = '0' then              -- asynchronous reset (active low)
342
      o_receive_newdata        <= '0';
343 22 nussgipfel
      o_receive_end_of_message <= '0';
344 23 nussgipfel
      o_send_data_request      <= '0';
345
      v_receive_fifo_empty_old := '0';
346
    elsif i_sysclk'event and i_sysclk = '1' then  -- rising clock edge
347
      if i_receive_newdata_set = '1' then
348
        o_receive_newdata <= '1';
349
      end if;
350
      if i_receive_fifo_rd_en = '1' then
351
        o_receive_newdata <= '0';
352
      end if;
353 22 nussgipfel
 
354 23 nussgipfel
      if i_receive_end_of_message_set = '1' then
355
        o_receive_end_of_message <= '1';
356
      end if;
357
      if s_receive_fifo_empty = '1' and v_receive_fifo_empty_old = '0' then
358
        o_receive_end_of_message <= '0';
359
      end if;
360
      v_receive_fifo_empty_old := s_receive_fifo_empty;
361
 
362
      if i_send_data_request_set = '1' then
363
        o_send_data_request <= '1';
364
      end if;
365
      if i_send_fifo_wr_en = '1' then
366
        o_send_data_request <= '0';
367
      end if;
368 22 nussgipfel
    end if;
369 23 nussgipfel
  end process gecko3com_simple_flags;
370 22 nussgipfel
 
371
 
372
end behaviour;

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