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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3COM_simple_fsm.vhd] - Blame information for rev 24

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1 22 nussgipfel
--  GECKO3COM IP Core
2
--
3
--  Copyright (C) 2009 by
4
--   ___    ___   _   _
5
--  (  _ \ (  __)( ) ( )
6
--  | (_) )| (   | |_| |   Bern University of Applied Sciences
7
--  |  _ < |  _) |  _  |   School of Engineering and
8
--  | (_) )| |   | | | |   Information Technology
9
--  (____/ (_)   (_) (_)
10
--
11
--  This program is free software: you can redistribute it and/or modify
12
--  it under the terms of the GNU General Public License as published by
13
--  the Free Software Foundation, either version 3 of the License, or
14
--  (at your option) any later version.
15
--
16
--  This program is distributed in the hope that it will be useful,
17
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
18
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
--  GNU General Public License for more details. 
20
--  You should have received a copy of the GNU General Public License
21
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
22
--
23
--  URL to the project description: 
24
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
25
--------------------------------------------------------------------------------
26
--
27
--  Author:  Christoph Zimmermann
28
--  Date of creation:  3 february 2010 
29
--  Description:
30
--      This is the finite-state-mashine for the GECKO3com simple IP core.
31
--   
32
--      This core provides a simple FIFO and register interface to the
33
--      USB data transfer capabilities of the GECKO3COM/GECKO3main system.
34
--
35 23 nussgipfel
--      Look at GECKO3COM_simple_test.vhd for an example how to use it.
36 22 nussgipfel
--
37
--  Target Devices:     general
38
--  Tool versions:      11.1
39
--
40
--------------------------------------------------------------------------------
41
 
42
library IEEE;
43
use IEEE.STD_LOGIC_1164.all;
44
use IEEE.STD_LOGIC_ARITH.all;
45
use IEEE.STD_LOGIC_UNSIGNED.all;
46
 
47
library work;
48
use work.GECKO3COM_defines.all;
49
 
50
 
51
entity GECKO3COM_simple_fsm is
52
 
53
  port (
54
    i_nReset                     : in  std_logic;
55
    i_sysclk                     : in  std_logic;
56
    o_receive_fifo_wr_en         : out std_logic;
57
    i_receive_fifo_full          : in  std_logic;
58
    o_receive_fifo_reset         : out std_logic;
59
    o_receive_transfersize_en    : out std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
60
    o_receive_counter_load       : out std_logic;
61
    o_receive_counter_en         : out std_logic;
62
    i_receive_counter_zero       : in  std_logic;
63
    i_dev_dep_msg_out            : in  std_logic;
64
    i_request_dev_dep_msg_in     : in  std_logic;
65
    o_btag_reg_en                : out std_logic;
66
    o_nbtag_reg_en               : out std_logic;
67
    i_btag_correct               : in  std_logic;
68
    i_eom_bit_detected           : in  std_logic;
69
    i_send_transfersize_en       : in  std_logic;
70
    o_send_fifo_rd_en            : out std_logic;
71
    i_send_fifo_empty            : in  std_logic;
72
    o_send_fifo_reset            : out std_logic;
73
    o_send_counter_load          : out std_logic;
74
    o_send_counter_en            : out std_logic;
75
    i_send_counter_zero          : in  std_logic;
76
    o_send_mux_sel               : out std_logic_vector(2 downto 0);
77
    o_send_finished              : out std_logic;
78
    o_receive_newdata_set        : out std_logic;
79
    o_receive_end_of_message_set : out std_logic;
80
    o_send_data_request_set      : out std_logic;
81
    i_gpif_rx                    : in  std_logic;
82
    i_gpif_rx_empty              : in  std_logic;
83
    o_gpif_rx_rd_en              : out std_logic;
84
    i_gpif_tx                    : in  std_logic;
85
    i_gpif_tx_full               : in  std_logic;
86
    o_gpif_tx_wr_en              : out std_logic;
87
    i_gpif_abort                 : in  std_logic;
88
    o_gpif_eom                   : out std_logic);
89
 
90
end GECKO3COM_simple_fsm;
91
 
92
 
93
architecture fsm of GECKO3COM_simple_fsm is
94
 
95
  -- XST specific synthesize attributes
96
  attribute safe_implementation : string;
97
  attribute safe_recovery_state : string;
98
 
99
  type   state_type is (st1_idle, st2_abort, st3_read_msg_id, st4_read_nbtag,
100
                        st5_check_btag, st6_read_transfer_size_low,
101
                        st7_read_transfer_size_high, st8_check_attributes,
102
                        st9_signal_data_request, st10_signal_receive_new_data,
103
                        st11_receive_data, st12_receive_wait,
104
                        st13_wait_for_receive_end, st14_read_align_bytes,
105
                        st15_start_response, st16_send_msg_id,
106
                        st17_send_nbtag, st18_send_transfer_size_low,
107
                        st19_send_transfer_size_high, st20_send_attributes,
108
                        st21_load_counter, st22_send_data, st23_send_wait,
109
                        st24_wait_for_send_end);
110
  signal state, next_state : state_type;
111
 
112
  -- XST specific synthesize attributes
113
  attribute safe_recovery_state of state : signal is "st1_idle";
114
  attribute safe_implementation of state : signal is "yes";
115
 
116
  --Declare internal signals for all outputs of the state-machine
117
  signal s_receive_fifo_wr_en         : std_logic;
118
  signal s_receive_fifo_reset         : std_logic;
119
  signal s_receive_transfersize_en    : std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
120
  signal s_receive_counter_load       : std_logic;
121
  signal s_receive_counter_en         : std_logic;
122
  signal s_btag_reg_en                : std_logic;
123
  signal s_nbtag_reg_en               : std_logic;
124
  signal s_send_fifo_rd_en            : std_logic;
125
  signal s_send_fifo_reset            : std_logic;
126
  signal s_send_counter_load          : std_logic;
127
  signal s_send_counter_en            : std_logic;
128
  signal s_send_mux_sel               : std_logic_vector(2 downto 0);
129
  signal s_send_finished              : std_logic;
130
  signal s_receive_newdata_set        : std_logic;
131
  signal s_receive_end_of_message_set : std_logic;
132
  signal s_send_data_request_set      : std_logic;
133
  signal s_gpif_eom                   : std_logic;
134
  signal s_gpif_rx_rd_en              : std_logic;
135
  signal s_gpif_tx_wr_en              : std_logic;
136
 
137
 
138
begin  -- fsm
139
 
140
  SYNC_PROC : process (i_sysclk)
141
  begin
142
    if (i_sysclk'event and i_sysclk = '1') then
143
      if (i_nReset = '0') then
144
        state <= st1_idle;
145
 
146
        o_receive_fifo_wr_en         <= '0';
147
        o_receive_fifo_reset         <= '1';
148
        o_receive_transfersize_en    <= (others => '0');
149
        o_receive_counter_load       <= '0';
150
        o_receive_counter_en         <= '0';
151
        o_btag_reg_en                <= '0';
152
        o_nbtag_reg_en               <= '0';
153
        o_send_fifo_rd_en            <= '0';
154
        o_send_fifo_reset            <= '1';
155
        o_send_counter_load          <= '0';
156
        o_send_counter_en            <= '0';
157
        o_send_mux_sel               <= (others => '0');
158
        o_send_finished              <= '0';
159
        o_receive_newdata_set        <= '0';
160
        o_receive_end_of_message_set <= '0';
161
        o_send_data_request_set      <= '0';
162
        o_gpif_eom                   <= '0';
163
        o_gpif_rx_rd_en              <= '0';
164
        o_gpif_tx_wr_en              <= '0';
165
 
166
      else
167
        state <= next_state;
168
 
169
        o_receive_fifo_wr_en         <= s_receive_fifo_wr_en;
170
        o_receive_fifo_reset         <= s_receive_fifo_reset;
171
        o_receive_transfersize_en    <= s_receive_transfersize_en;
172
        o_receive_counter_load       <= s_receive_counter_load;
173
        o_receive_counter_en         <= s_receive_counter_en;
174
        o_btag_reg_en                <= s_btag_reg_en;
175
        o_nbtag_reg_en               <= s_nbtag_reg_en;
176
        o_send_fifo_rd_en            <= s_send_fifo_rd_en;
177
        o_send_fifo_reset            <= s_send_fifo_reset;
178
        o_send_counter_load          <= s_send_counter_load;
179
        o_send_counter_en            <= s_send_counter_en;
180
        o_send_mux_sel               <= s_send_mux_sel;
181
        o_send_finished              <= s_send_finished;
182
        o_receive_newdata_set        <= s_receive_newdata_set;
183
        o_receive_end_of_message_set <= s_receive_end_of_message_set;
184
        o_send_data_request_set      <= s_send_data_request_set;
185
        o_gpif_eom                   <= s_gpif_eom;
186
        o_gpif_rx_rd_en              <= s_gpif_rx_rd_en;
187
        o_gpif_tx_wr_en              <= s_gpif_tx_wr_en;
188
      end if;
189
    end if;
190
  end process;
191
 
192
  --MEALY State-Machine - Outputs based on state and inputs
193
  OUTPUT_DECODE : process (state, i_receive_fifo_full,
194
                           i_receive_counter_zero, i_dev_dep_msg_out,
195
                           i_request_dev_dep_msg_in, i_btag_correct,
196
                           i_eom_bit_detected, i_send_transfersize_en,
197
                           i_send_fifo_empty, i_send_counter_zero,
198
                           i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
199
                           i_gpif_tx_full, i_gpif_abort)
200
  begin
201
 
202
    s_receive_fifo_wr_en         <= '0';
203
    s_receive_fifo_reset         <= '0';
204
    s_receive_transfersize_en    <= (others => '0');
205
    s_receive_counter_load       <= '0';
206
    s_receive_counter_en         <= '0';
207
    s_btag_reg_en                <= '0';
208
    s_nbtag_reg_en               <= '0';
209
    s_send_fifo_rd_en            <= '0';
210
    s_send_fifo_reset            <= '0';
211
    s_send_counter_load          <= '0';
212
    s_send_counter_en            <= '0';
213
    s_send_mux_sel               <= (others => '0');
214 24 nussgipfel
    s_send_finished              <= '0';
215 22 nussgipfel
    s_receive_newdata_set        <= '0';
216
    s_receive_end_of_message_set <= '0';
217
    s_send_data_request_set      <= '0';
218
    s_gpif_eom                   <= '0';
219
    s_gpif_rx_rd_en              <= '0';
220
    s_gpif_tx_wr_en              <= '0';
221
 
222
    if state = st11_receive_data then
223
      s_receive_fifo_wr_en <= '1';
224
    end if;
225
 
226
    if state = st2_abort then
227
      s_receive_fifo_reset <= '1';
228
    end if;
229
 
230
    if state = st6_read_transfer_size_low then
231
      s_receive_transfersize_en <= "01";
232
    elsif state = st7_read_transfer_size_high then
233
      s_receive_transfersize_en <= "10";
234
    end if;
235
 
236
    if state = st10_signal_receive_new_data then
237
      s_receive_counter_load <= '1';
238
    end if;
239
 
240
    if (state = st10_signal_receive_new_data and
241
        i_gpif_rx_empty = '0' and
242
        i_receive_fifo_full = '0')
243
      or (state = st11_receive_data)
244
      or (state = st12_receive_wait and
245
          i_gpif_rx_empty = '0' and
246
          i_receive_fifo_full = '1')
247
    then
248
      s_receive_counter_en <= '1';
249
    end if;
250
 
251
    if state = st3_read_msg_id then
252
      s_btag_reg_en <= '1';
253
    end if;
254
 
255
    if state = st4_read_nbtag then
256
      s_nbtag_reg_en <= '1';
257
    end if;
258
 
259
    if (state = st21_load_counter and
260
        i_gpif_tx_full = '0' and
261
        i_send_fifo_empty = '0')
262
      or state = st22_send_data
263
      or (state = st23_send_wait and
264
          i_gpif_tx_full = '0' and
265
          i_send_fifo_empty = '0')
266
    then
267
      s_send_fifo_rd_en <= '1';
268
    end if;
269
 
270 23 nussgipfel
    if state = st2_abort or state = st24_wait_for_send_end then
271 22 nussgipfel
      s_send_fifo_reset <= '1';
272
    end if;
273
 
274
    if state = st21_load_counter then
275
      s_send_counter_load <= '1';
276
    end if;
277
 
278
    if (state = st21_load_counter and i_gpif_tx_full = '0' and
279
        i_send_fifo_empty = '0') or
280
      state = st22_send_data or
281
      (state = st23_send_wait and i_gpif_tx_full = '0' and
282
       i_send_fifo_empty = '0')
283
    then
284
      s_send_counter_en <= '1';
285
    end if;
286
 
287
    if state = st16_send_msg_id then
288
      s_send_mux_sel <= "000";
289
    elsif state = st17_send_nbtag then
290
      s_send_mux_sel <= "001";
291
    elsif state =st18_send_transfer_size_low then
292
      s_send_mux_sel <= "010";
293
    elsif state = st19_send_transfer_size_high then
294
      s_send_mux_sel <= "011";
295
    elsif state = st20_send_attributes then
296
      s_send_mux_sel <= "100";
297
    elsif state = st21_load_counter then
298
      s_send_mux_sel <= "101";
299
    end if;
300
 
301
    if state = st24_wait_for_send_end and i_gpif_tx = '0' then
302 24 nussgipfel
      s_send_finished <= '1';
303 22 nussgipfel
    end if;
304
 
305
    if state = st10_signal_receive_new_data then
306
      s_receive_newdata_set <= '1';
307
    end if;
308
 
309
    if state = st8_check_attributes and i_eom_bit_detected = '1' then
310
      s_receive_end_of_message_set <= '1';
311
    end if;
312
 
313
    if state = st9_signal_data_request then
314
      s_send_data_request_set <= '1';
315
    end if;
316 24 nussgipfel
 
317 22 nussgipfel
    if state = st22_send_data and i_send_counter_zero = '1' then
318
      s_gpif_eom <= '1';
319
    end if;
320
 
321
    if (i_gpif_rx_empty = '0' and
322
        (state = st1_idle or
323
         state = st3_read_msg_id or
324
         state = st4_read_nbtag or
325
         state = st5_check_btag or
326
         state = st6_read_transfer_size_low or
327
         state = st7_read_transfer_size_high or
328
         state = st8_check_attributes))
329
      or ((state = st10_signal_receive_new_data or state = st12_receive_wait)
330
          and i_gpif_rx_empty = '0' and i_receive_fifo_full = '0')
331
      or state = st11_receive_data
332
      or (state = st14_read_align_bytes and i_gpif_rx_empty = '0')
333
    then
334
      s_gpif_rx_rd_en <= '1';
335
    end if;
336
 
337
    if (i_gpif_tx_full = '0' and
338
        (state = st16_send_msg_id or
339
         state = st17_send_nbtag or
340
         state = st18_send_transfer_size_low or
341
         state = st19_send_transfer_size_high or
342
         state = st20_send_attributes or
343
         state = st21_load_counter))
344
      or state = st22_send_data
345
    then
346
      s_gpif_tx_wr_en <= '1';
347
    end if;
348
  end process;
349
 
350
  NEXT_STATE_DECODE : process (state, i_receive_fifo_full,
351
                               i_receive_counter_zero, i_dev_dep_msg_out,
352
                               i_request_dev_dep_msg_in, i_btag_correct,
353
                               i_eom_bit_detected, i_send_transfersize_en,
354
                               i_send_fifo_empty, i_send_counter_zero,
355
                               i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
356
                               i_gpif_tx_full, i_gpif_abort)
357
  begin
358
    --declare default state for next_state to avoid latches
359
    next_state <= state;                --default is to stay in current state
360
 
361
    case (state) is
362
      when st1_idle =>
363
        if i_gpif_abort = '1' then
364
          next_state <= st2_abort;
365
        elsif i_gpif_rx_empty = '0' then
366
          next_state <= st3_read_msg_id;
367
        end if;
368
 
369
      when st2_abort =>
370
        next_state <= st1_idle;
371
 
372
      when st3_read_msg_id =>
373
        if i_gpif_abort = '1' then
374
          next_state <= st2_abort;
375
        elsif i_gpif_rx_empty = '0' then
376
          next_state <= st4_read_nbtag;
377
        end if;
378
 
379
      when st4_read_nbtag =>
380
        if i_gpif_abort = '1' then
381
          next_state <= st2_abort;
382
        elsif i_gpif_rx_empty = '0' then
383
          next_state <= st5_check_btag;
384
        end if;
385
 
386
      when st5_check_btag =>
387
        if i_gpif_abort = '1' then
388
          next_state <= st2_abort;
389
        elsif i_btag_correct = '0' then
390
          next_state <= st1_idle;
391
        elsif i_gpif_rx_empty = '0' then
392
          next_state <= st6_read_transfer_size_low;
393
        end if;
394
 
395
      when st6_read_transfer_size_low =>
396
        if i_gpif_abort = '1' then
397
          next_state <= st2_abort;
398
        elsif i_gpif_rx_empty = '0' then
399
          next_state <= st7_read_transfer_size_high;
400
        end if;
401
 
402
      when st7_read_transfer_size_high =>
403
        if i_gpif_abort = '1' then
404
          next_state <= st2_abort;
405
        elsif i_gpif_rx_empty = '0' then
406
          next_state <= st8_check_attributes;
407
        end if;
408
 
409
      when st8_check_attributes =>
410
        if i_gpif_abort = '1' then
411
          next_state <= st2_abort;
412
        elsif i_gpif_rx_empty = '0' and i_request_dev_dep_msg_in = '1' then
413
          next_state <= st9_signal_data_request;
414
        elsif i_gpif_rx_empty = '0' and i_dev_dep_msg_out = '1' then
415
          next_state <= st10_signal_receive_new_data;
416
        end if;
417
 
418
      when st9_signal_data_request =>
419
        if i_gpif_abort = '1' then
420
          next_state <= st2_abort;
421
        elsif i_send_transfersize_en = '1' then
422
          next_state <= st15_start_response;
423
        end if;
424
 
425
      when st10_signal_receive_new_data =>
426
        if i_gpif_abort = '1' then
427
          next_state <= st2_abort;
428
        elsif i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
429
          next_state <= st11_receive_data;
430
        end if;
431
 
432
      when st11_receive_data =>
433
        if i_gpif_abort = '1' then
434
          next_state <= st2_abort;
435
        elsif i_receive_counter_zero = '1' then
436
          next_state <= st13_wait_for_receive_end;
437
        elsif  i_gpif_rx_empty = '1' or i_receive_fifo_full = '1' then
438
          next_state <= st12_receive_wait;
439
        end if;
440
 
441
      when st12_receive_wait =>
442
        if i_gpif_abort = '1' then
443
          next_state <= st2_abort;
444
        elsif  i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
445
          next_state <= st11_receive_data;
446
        end if;
447
 
448
      when st13_wait_for_receive_end =>
449
        if i_gpif_abort = '1' then
450
          next_state <= st2_abort;
451
        elsif i_gpif_rx = '0' then
452
          next_state <= st14_read_align_bytes;
453
        end if;
454
 
455
      when st14_read_align_bytes =>
456
        if i_gpif_abort = '1' then
457
          next_state <= st2_abort;
458
        elsif i_gpif_rx_empty = '1' then
459
          next_state <= st1_idle;
460
        end if;
461
 
462
      when st15_start_response =>
463
        if i_gpif_abort = '1' then
464
          next_state <= st2_abort;
465
        elsif i_gpif_tx_full = '0' then
466
          next_state <= st16_send_msg_id;
467
        end if;
468
 
469
      when st16_send_msg_id =>
470
        if i_gpif_abort = '1' then
471
          next_state <= st2_abort;
472
        elsif i_gpif_tx_full = '0' then
473
          next_state <= st17_send_nbtag;
474
        end if;
475
 
476
      when st17_send_nbtag =>
477
        if i_gpif_abort = '1' then
478
          next_state <= st2_abort;
479
        elsif i_gpif_tx_full = '0' then
480
          next_state <= st18_send_transfer_size_low;
481
        end if;
482
 
483
      when st18_send_transfer_size_low =>
484
        if i_gpif_abort = '1' then
485
          next_state <= st2_abort;
486
        elsif i_gpif_tx_full = '0' then
487
          next_state <= st19_send_transfer_size_high;
488
        end if;
489
 
490
      when st19_send_transfer_size_high =>
491
        if i_gpif_abort = '1' then
492
          next_state <= st2_abort;
493
        elsif i_gpif_tx_full = '0' then
494
          next_state <= st20_send_attributes;
495
        end if;
496
 
497
      when st20_send_attributes =>
498
        if i_gpif_abort = '1' then
499
          next_state <= st2_abort;
500
        elsif i_gpif_tx_full = '0' then
501
          next_state <= st21_load_counter;
502
        end if;
503
 
504
      when st21_load_counter =>
505
        if i_gpif_abort = '1' then
506
          next_state <= st2_abort;
507
        elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
508
          next_state <= st22_send_data;
509
        end if;
510
 
511
      when st22_send_data =>
512
        if i_gpif_abort = '1' then
513
          next_state <= st2_abort;
514
        elsif i_send_counter_zero = '1' then
515
          next_state <= st24_wait_for_send_end;
516
        elsif i_gpif_tx_full = '1' or i_send_fifo_empty = '1' then
517
          next_state <= st23_send_wait;
518
        end if;
519
 
520
      when st23_send_wait =>
521
        if i_gpif_abort = '1' then
522
          next_state <= st2_abort;
523
        elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
524
          next_state <= st22_send_data;
525
        end if;
526
 
527
      when st24_wait_for_send_end =>
528
        if i_gpif_abort = '1' then
529
          next_state <= st2_abort;
530
        elsif i_gpif_tx = '0' then
531
          next_state <= st1_idle;
532
        end if;
533
 
534
      when others =>
535
        next_state <= st1_idle;
536
    end case;
537
  end process;
538
 
539
end fsm;

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