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nussgipfel |
##############################################################
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#
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# Xilinx Core Generator version 11.1
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# Date: Sun Feb 14 17:28:00 2010
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = True
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = True
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SET designentry = VHDL
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SET device = xc3s4000
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SET devicefamily = spartan3
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SET flowvendor = Foundation_iSE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = fg676
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -4
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SET verilogsim = True
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SET vhdlsim = True
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# END Project Options
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# BEGIN Select
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SELECT Fifo_Generator family Xilinx,_Inc. 3.3
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# END Select
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# BEGIN Parameters
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CSET almost_empty_flag=true
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CSET almost_full_flag=true
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CSET component_name=coregenerator_fifo_receive
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CSET data_count=false
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CSET data_count_width=9
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CSET dout_reset_value=0
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CSET empty_threshold_assert_value=2
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CSET empty_threshold_negate_value=3
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CSET enable_ecc=false
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CSET fifo_implementation=Independent_Clocks_Block_RAM
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CSET full_threshold_assert_value=1020
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CSET full_threshold_negate_value=1019
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CSET input_data_width=16
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CSET input_depth=1024
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CSET output_data_width=32
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CSET output_depth=512
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CSET overflow_flag=false
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CSET overflow_sense=Active_High
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CSET performance_options=Standard_FIFO
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CSET programmable_empty_type=No_Programmable_Empty_Threshold
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CSET programmable_full_type=No_Programmable_Full_Threshold
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CSET read_clock_frequency=100
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CSET read_data_count=false
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CSET read_data_count_width=9
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CSET reset_pin=true
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CSET reset_type=Asynchronous_Reset
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CSET underflow_flag=false
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CSET underflow_sense=Active_High
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CSET use_extra_logic=false
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CSET valid_flag=false
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CSET valid_sense=Active_High
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CSET write_acknowledge_flag=false
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CSET write_acknowledge_sense=Active_High
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CSET write_clock_frequency=100
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CSET write_data_count=false
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CSET write_data_count_width=9
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# END Parameters
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GENERATE
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# CRC: 37e23f46
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