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COPYRIGHT (c) 2006, 2007 XILINX, INC.
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ALL RIGHTS RESERVED
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Core name : FIFO Generator
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Version : v3.3 rev 1
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Release Date : April 2, 2007
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File : fifo_generator_release_notes.txt
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Revision History
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Date By Version Change Description
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========================================================================
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09/2006 Xilinx, Inc. 3.2 Initial creation.
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02/2007 Xilinx, Inc. 3.3 Revised for v3.3.
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02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1.
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========================================================================
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INTRODUCTION
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RELEASE NOTES
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1. General Core Design
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1.1 Enhancements
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1.2 Resolved Issues
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1.3 Outstanding Issues
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2. General Simulation
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2.1 Enhancements
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2.2 Resolved Issues
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2.3 Outstanding Issues
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3. Documentation
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3.1 Enhancements
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3.2 Resolved Issues
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3.3 Outstanding Issues
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OTHER GENERAL INFORMATION
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TECHNICAL SUPPORT
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========================================================================
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INTRODUCTION
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============
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Thank you using the FIFO Generator core from Xilinx!
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In order to obtain the latest core updates and documentation,
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please visit the Intellectual Property page located at:
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http://www.xilinx.com/ipcenter/index.htm
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This document contains the release notes for FIFO Generator v3.3
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which includes enhancements, resolved issues and outstanding known
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issues. For release notes and known issues for CORE Generator 9.1i IP
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Update 1 and FIFO Generator v3.3 please see Answer Record 234307.
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RELEASE NOTES
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=============
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This section lists any enhancements, resolved issues and outstanding
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known issues.
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1. General Core Design
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1.1 Enhancements
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1.1.1 Spartan(TM)-3A DSP support
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1.1.2 Added Support for Error Correction Checking (ECC) feature for
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Virtex-5 Built-In FIFO configuration.
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1.2 Resolved Issues
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1.2.1 Coregen GUI - For Block RAM and Distributed RAM FIFOs, if the
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reset pin is not chosen, the reset type text in page 6 of the
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GUI (summary) is displayed as "Asynchronous" instead of
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"Not Selected".
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Change request: 423076
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1.2.2 Programmable full threshold assert range is incorrect for
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independent clock Block RAM configurations.
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Change request: 422495
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1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol
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.. , these pins should be connected to the same signal" occur
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during MAP when targeting Virtex-4 and Virtex-5.
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Change request: 419562, 430838
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1.3 Outstanding Issues
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1.3.1 "WARNING:Ngdbuild:452 - logical net
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'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during
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NgdBuild although programmable empty or full is not selected.
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Warnings can be safely ignored.
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Change request: 431975
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2. General Simulation
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2.1 Enhancements
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None at this time.
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2.2 Resolved Issues
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None at this time.
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2.3 Outstanding Issues
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2.3.1 Ncelab warnings during Verilog structural and timing simulations
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in ncsim for Virtex5 Block RAM FIFOs.
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The simulations will be successful, but there will be warnings
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similar to the following in the log file: "memory index out of
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declared bounds" in simprims_ver_virtex5_source.v or
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unisims_ver_virtex5_source.v. Cadence does not want to fix this
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issue. These warning messages can safely be ignored.
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Change request: 423374, 423375
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3. Documentation
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3.1 Enhancements
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3.1.1 Added clarification on the WR_DATA_COUNT and RD_DATA_COUNT description.
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Change request: 4328061
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3.2 Resolved Issues
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None at this time.
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3.3 Outstanding Issues
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None at this time.
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TECHNICAL SUPPORT
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=================
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The fastest method for obtaining specific technical support for the
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FIFO Generator core is through the http://support.xilinx.com/
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website. Questions are routed to a team of engineers with specific
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expertise in using the Block Memory Generator core. Xilinx will provide
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technical support for use of this product as described in the Block
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Memory Generator Datasheet. Xilinx cannot guarantee timing,
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functionality, or support of this product for designs that do not
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follow these guidelines.
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