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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com.vhd] - Blame information for rev 29

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Line No. Rev Author Line
1 14 nussgipfel
--  GECKO3COM IP Core
2
--
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--  Copyright (C) 2009 by
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--   ___    ___   _   _
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--  (  _ \ (  __)( ) ( )
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--  | (_) )| (   | |_| |   Bern University of Applied Sciences
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--  |  _ < |  _) |  _  |   School of Engineering and
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--  | (_) )| |   | | | |   Information Technology
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--  (____/ (_)   (_) (_)
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details. 
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--  URL to the project description: 
24
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
25 18 nussgipfel
--------------------------------------------------------------------------------
26 14 nussgipfel
--
27
--  Author:  Andreas Habegger, Christoph Zimmermann
28
--  Date of creation: 8. April 2009
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--  Description:
30 18 nussgipfel
--    GECKO3COM defines the communication between the GECKO3main and a USB
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--    Master e.g. a computer.
32 14 nussgipfel
--
33 18 nussgipfel
--    This file is the top module, it instantiates all required submodules and
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--    connects them together.
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--
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--  Target Devices:     Xilinx Spartan3 FPGA's
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--                      (usage of BlockRam in the Datapath)
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--  Tool versions:      11.1
39 14 nussgipfel
--  Dependencies:
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--
41 18 nussgipfel
--------------------------------------------------------------------------------
42 14 nussgipfel
 
43 11 nussgipfel
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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47
library work;
48 14 nussgipfel
use work.GECKO3COM_defines.all;
49 11 nussgipfel
 
50
 
51 14 nussgipfel
entity gpif_com is
52 11 nussgipfel
  port (
53 18 nussgipfel
    -- interface signals to higher level
54
    i_nReset  : in  std_logic;          -- asynchronous active low reset
55
    i_SYSCLK  : in  std_logic;          -- FPGA System CLK
56
    o_ABORT   : out std_logic;          -- Abort detected, you have to flush the data
57
    o_RX      : out std_logic;          -- controll LED rx
58
    o_TX      : out std_logic;          -- controll LED tx
59
    i_RD_EN   : in  std_logic;          -- read enable
60
    o_EMPTY   : out std_logic;          -- receive fifo empty
61
    o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- receive data
62 20 nussgipfel
    i_EOM     : in  std_logic;
63 18 nussgipfel
    i_WR_EN   : in  std_logic;          -- write enable
64
    o_FULL    : out std_logic;          -- send fifo full
65
    i_TX_DATA : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- send data
66
 
67
    -- GPIF connections, to be connected to FPGA pins
68
    i_IFCLK    : in    std_logic;       -- GPIF CLK (GPIF is Master and provides the clock)
69
    i_WRU      : in    std_logic;       -- write from GPIF
70
    i_RDYU     : in    std_logic;       -- GPIF is ready
71
    o_WRX      : out   std_logic;       -- To write to GPIF
72
    o_RDYX     : out   std_logic;       -- IP Core is ready
73
    b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));  -- bidirect data bus
74 14 nussgipfel
end gpif_com;
75 11 nussgipfel
 
76
 
77
 
78 14 nussgipfel
architecture structure of gpif_com is
79
 
80 11 nussgipfel
  -- interconection signals
81 29 nussgipfel
  signal s_FIFOrst, s_WRX, s_RDYX         : std_logic;
82 11 nussgipfel
 
83 29 nussgipfel
  signal s_ABORT_FSM, s_ABORT_TMP         : std_logic;
84
  signal s_RX_FSM, s_RX_TMP               : std_logic;
85
  signal s_TX_FSM, s_TX_TMP               : std_logic;
86
  signal s_EOM, s_EOM_TMP, s_EOM_FF       : std_logic;  -- End of message
87 20 nussgipfel
  signal s_X2U_FULL_IFCLK, s_X2U_FULL_TMP : std_logic;
88 14 nussgipfel
 
89 18 nussgipfel
  -- USB to Xilinx (U2X)
90 12 nussgipfel
  signal s_U2X_WR_EN,
91 18 nussgipfel
    s_U2X_RD_EN,
92
    s_U2X_FULL,
93
    s_U2X_AM_FULL,
94
    s_U2X_EMPTY,
95 29 nussgipfel
    s_U2X_AM_EMPTY  : std_logic;
96
  signal s_U2X_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
97 18 nussgipfel
 
98
  -- Xilinx to USB (X2U)
99 12 nussgipfel
  signal s_X2U_WR_EN,
100 18 nussgipfel
    s_X2U_RD_EN,
101
    s_X2U_FULL,
102
    s_X2U_AM_FULL,
103
    s_X2U_EMPTY,
104 29 nussgipfel
    s_X2U_AM_EMPTY  : std_logic;
105
  signal s_X2U_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
106 18 nussgipfel
 
107
  -----------------------------------------------------------------------------
108 11 nussgipfel
  -- data bus
109 18 nussgipfel
  -----------------------------------------------------------------------------
110 11 nussgipfel
 
111
  -- data signals
112 29 nussgipfel
  signal s_dbus_trans_dir : std_logic;
113
  signal s_dbus_in        : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
114
  signal s_dbus_out       : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
115
  signal s_dbus_out_fifo  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
116 14 nussgipfel
 
117 11 nussgipfel
  -----------------------------------------------------------------------------
118
  -- COMPONENTS
119
  -----------------------------------------------------------------------------
120
 
121 14 nussgipfel
  -- FSM GPIF
122
  component gpif_com_fsm
123 18 nussgipfel
    port (
124 20 nussgipfel
      i_nReset         : in  std_logic;
125
      i_IFCLK          : in  std_logic;
126
      i_WRU            : in  std_logic;
127
      i_RDYU           : in  std_logic;
128
      i_EOM            : in  std_logic;
129
      i_U2X_FULL       : in  std_logic;
130
      i_U2X_AM_FULL    : in  std_logic;
131
      i_X2U_FULL_IFCLK : in  std_logic;
132
      i_X2U_AM_EMPTY   : in  std_logic;
133
      i_X2U_EMPTY      : in  std_logic;
134
      o_bus_trans_dir  : out std_logic;
135
      o_U2X_WR_EN      : out std_logic;
136
      o_X2U_RD_EN      : out std_logic;
137
      o_FIFOrst        : out std_logic;
138
      o_WRX            : out std_logic;
139
      o_RDYX           : out std_logic;
140
      o_ABORT          : out std_logic;
141
      o_RX             : out std_logic;
142
      o_TX             : out std_logic);
143 14 nussgipfel
  end component;
144 11 nussgipfel
 
145 14 nussgipfel
  -- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
146
  component fifo_dualclock
147 18 nussgipfel
    port (
148
      i_din          : IN  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
149
      i_rd_clk       : IN  std_logic;
150
      i_rd_en        : IN  std_logic;
151
      i_rst          : IN  std_logic;
152
      i_wr_clk       : IN  std_logic;
153
      i_wr_en        : IN  std_logic;
154
      o_almost_empty : OUT std_logic;
155
      o_almost_full  : OUT std_logic;
156
      o_dout         : OUT std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
157
      o_empty        : OUT std_logic;
158
      o_full         : OUT std_logic);
159 14 nussgipfel
  end component;
160
 
161 11 nussgipfel
 
162
begin
163
 
164
  -----------------------------------------------------------------------------
165
  -- Port map
166
  -----------------------------------------------------------------------------
167
 
168 14 nussgipfel
  F_IN : fifo_dualclock
169 18 nussgipfel
    port map (
170
      i_din          => s_dbus_in,
171
      i_rd_clk       => i_SYSCLK,
172
      i_rd_en        => s_U2X_RD_EN,
173
      i_rst          => s_FIFOrst,
174
      i_wr_clk       => i_IFCLK ,
175
      i_wr_en        => s_U2X_WR_EN,
176
      o_almost_empty => s_U2X_AM_EMPTY,
177
      o_almost_full  => s_U2X_AM_FULL,
178
      o_dout         => s_U2X_DATA,
179
      o_empty        => s_U2X_EMPTY,
180
      o_full         => s_U2X_FULL
181
      );
182 11 nussgipfel
 
183
 
184 14 nussgipfel
  F_OUT : fifo_dualclock
185 18 nussgipfel
    port map (
186
      i_din          => s_X2U_DATA,
187
      i_rd_clk       => i_IFCLK,
188
      i_rd_en        => s_X2U_RD_EN,
189
      i_rst          => s_FIFOrst,
190
      i_wr_clk       => i_SYSCLK,
191
      i_wr_en        => s_X2U_WR_EN,
192
      o_almost_empty => s_X2U_AM_EMPTY,
193
      o_almost_full  => s_X2U_AM_FULL,
194 29 nussgipfel
      o_dout         => s_dbus_out_fifo,
195 18 nussgipfel
      o_empty        => s_X2U_EMPTY,
196
      o_full         => s_X2U_FULL
197
      );
198 11 nussgipfel
 
199 12 nussgipfel
 
200 14 nussgipfel
  FSM_GPIF : gpif_com_fsm
201 18 nussgipfel
    port map (
202 20 nussgipfel
      i_nReset         => i_nReset,
203
      i_IFCLK          => i_IFCLK,
204
      i_WRU            => i_WRU,
205
      i_RDYU           => i_RDYU,
206 24 nussgipfel
      --i_EOM            => s_EOM,
207 22 nussgipfel
      i_EOM            => s_EOM_FF,
208 20 nussgipfel
      i_U2X_FULL       => s_U2X_FULL,
209
      i_U2X_AM_FULL    => s_U2X_AM_FULL,
210
      i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK,
211
      i_X2U_AM_EMPTY   => s_X2U_AM_EMPTY,
212
      i_X2U_EMPTY      => s_X2U_EMPTY,
213
      o_U2X_WR_EN      => s_U2X_WR_EN,
214
      o_X2U_RD_EN      => s_X2U_RD_EN,
215
      o_FIFOrst        => s_FIFOrst,
216
      o_bus_trans_dir  => s_dbus_trans_dir,
217
      o_WRX            => s_WRX,
218
      o_RDYX           => s_RDYX,
219
      o_ABORT          => s_ABORT_FSM,
220
      o_RX             => s_RX_FSM,
221
      o_TX             => s_TX_FSM
222 18 nussgipfel
      );
223 11 nussgipfel
 
224 18 nussgipfel
 
225
 
226
  s_U2X_RD_EN  <= i_RD_EN;
227
  o_EMPTY   <= s_U2X_EMPTY;
228
  o_RX_DATA <= s_U2X_DATA;
229
 
230
  s_X2U_WR_EN <= i_WR_EN;
231
  o_FULL    <= s_X2U_FULL;
232
  s_X2U_DATA <= i_TX_DATA;
233
 
234
  o_WRX <= s_WRX;
235
  o_RDYX <= s_RDYX;
236
 
237 14 nussgipfel
  -- Double buffer the ABORT, RX and TX signal to avoid metastability
238
  double_buf_sig : process (i_SYSCLK, i_nReset)
239
  begin
240
    if i_nReset = '0' then
241 18 nussgipfel
      o_ABORT     <= '0';
242 14 nussgipfel
      s_ABORT_TMP <= '0';
243 18 nussgipfel
      o_TX        <= '0';
244
      s_TX_TMP    <= '0';
245
      o_RX        <= '0';
246
      s_RX_TMP    <= '0';
247
    elsif rising_edge(i_SYSCLK) then
248
      o_ABORT     <= s_ABORT_TMP;
249 14 nussgipfel
      s_ABORT_TMP <= s_ABORT_FSM;
250 18 nussgipfel
      o_TX        <= s_TX_TMP;
251
      s_TX_TMP    <= s_TX_FSM;
252
      o_RX        <= s_RX_TMP;
253
      s_RX_TMP    <= s_RX_FSM;
254 14 nussgipfel
    end if;
255
  end process double_buf_sig;
256 11 nussgipfel
 
257 22 nussgipfel
  -- Double buffer the s_EOM and s_X2U_FULL_IFCLK signal to avoid metastability
258 20 nussgipfel
  double_buf_ifclk : process (i_IFCLK, i_nReset)
259
  begin
260
    if i_nReset = '0' then
261
      s_X2U_FULL_TMP <= '0';
262
      s_X2U_FULL_IFCLK <= '0';
263
    elsif rising_edge(i_IFCLK) then
264
      s_EOM     <= s_EOM_TMP;
265
      s_EOM_TMP <= i_EOM;
266
      s_X2U_FULL_IFCLK <= s_X2U_FULL_TMP;
267
      s_X2U_FULL_TMP <= s_X2U_FULL;
268
    end if;
269
  end process double_buf_ifclk;
270 11 nussgipfel
 
271 24 nussgipfel
  --purpose: EOM bit flip-flop
272
  --type   : sequential
273
  --inputs : i_IFCLK, i_nReset, s_EOM, s_X2U_EMPTY
274
  --outputs: s_EOM_FF
275 22 nussgipfel
  EOM_FF: process (i_IFCLK, i_nReset)
276
  begin  -- process EOM_FF
277
    if i_nReset = '0' then                -- asynchronous reset (active low)
278
      s_EOM_FF <= '0';
279
    elsif i_IFCLK'event and i_IFCLK = '1' then  -- rising clock edge
280
      if s_EOM = '1' then
281
        s_EOM_FF <= '1';
282
      end if;
283 28 nussgipfel
      if s_X2U_EMPTY = '1' and s_TX_FSM = '0' then
284 22 nussgipfel
        s_EOM_FF <= '0';
285
      end if;
286
    end if;
287
  end process EOM_FF;
288
 
289
  -----------------------------------------------------------------------------
290
  -- Data bus access
291
  -----------------------------------------------------------------------------
292 20 nussgipfel
 
293 22 nussgipfel
  -- purpose: to handle the access on the bidirectional bus
294
  -- type   : combinational
295
  -- inputs : s_bus_trans_dir
296
  -- outputs: 
297 14 nussgipfel
  bus_access : process (s_dbus_trans_dir, s_dbus_out)
298
  begin  -- process bus_access
299
    if s_dbus_trans_dir = '1' then
300 18 nussgipfel
      b_gpif_bus <= s_dbus_out;
301 14 nussgipfel
    else
302 18 nussgipfel
      b_gpif_bus <= (others => 'Z');
303 14 nussgipfel
    end if;
304
  end process bus_access;
305 18 nussgipfel
 
306 19 nussgipfel
  -- buffer the gpif bus input signals to avoid that the last word in the
307
  -- usb to xilinx transfer is read twice.
308
  buf_input : process (i_IFCLK)
309
  begin
310
    if rising_edge(i_IFCLK) then
311
      s_dbus_in <= b_gpif_bus;
312 29 nussgipfel
 
313
      if s_X2U_RD_EN = '1' then
314
        s_dbus_out <= s_dbus_out_fifo;
315
      end if;
316 19 nussgipfel
    end if;
317
  end process buf_input;
318
 
319 18 nussgipfel
 
320 14 nussgipfel
end structure;

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