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--  GECKO3COM IP Core
--
--  Copyright (C) 2009 by
--   ___    ___   _   _
--  (  _ \ (  __)( ) ( )
--  | (_) )| (   | |_| |   Bern University of Applied Sciences
--  |  _ < |  _) |  _  |   School of Engineering and
--  | (_) )| |   | | | |   Information Technology
--  (____/ (_)   (_) (_)
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details. 
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--  URL to the project description: 
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
-------------------------------------------------------------------------------
--
--  Author:  Andreas Habegger, Christoph Zimmermann
--  Date of creation: 8. April 2009
--  Description:
--      FSM that controls the interface between the EZ-USB (and it's internal
--      GPIF, General Purpose Interface) and our FPGA. The interface is
--      synchronous, where the GPIF provides the clock. This FSM is synchronous
--      to the GPIF clock, also this side of the FIFO's.
--
--    You can find more detailed information how the interface works in the
--    ../Doc folder.
--
--  Target Devices:     general
--  Tool versions:      Xilinx ISE 11.1, XST
--  Dependencies:
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
library work;
use work.GECKO3COM_defines.all;
 
entity gpif_com_fsm is
  port (
    i_nReset         : in  std_logic;
    i_IFCLK          : in  std_logic;  -- GPIF CLK (GPIF is Master and provides the clock)
    i_WRU            : in  std_logic;   -- write from GPIF
    i_RDYU           : in  std_logic;   -- GPIF is ready
    i_EOM            : in  std_logic;   -- all data for X2U transfer is in FIFO
    i_U2X_FULL       : in  std_logic;
    i_U2X_AM_FULL    : in  std_logic;   -- signals for IN FIFO
    i_X2U_FULL_IFCLK : in  std_logic;
    i_X2U_AM_EMPTY   : in  std_logic;
    i_X2U_EMPTY      : in  std_logic;   -- signals for OUT FIFO
    o_bus_trans_dir  : out std_logic;
    o_U2X_WR_EN      : out std_logic;   -- signals for IN FIFO
    o_X2U_RD_EN      : out std_logic;   -- signals for OUT FIFO
    o_FIFOrst        : out std_logic;
    o_WRX            : out std_logic;   -- To write to GPIF
    o_RDYX           : out std_logic;   -- Core is ready
    o_ABORT          : out std_logic;  -- abort condition detected. we have to flush the data
    o_RX             : out std_logic;
    o_TX             : out std_logic    --
    );
 
end gpif_com_fsm;
 
 
 
architecture fsm of gpif_com_fsm is
 
  -- XST specific synthesize attributes
  attribute safe_implementation: string;
  attribute safe_recovery_state: string;
 
 
  -----------------------------------------------------------------------------
  -- FSM
  -----------------------------------------------------------------------------
 
  type   t_busAccess is (readFromGPIF, writeToGPIF);
  signal s_bus_trans_dir : t_busAccess;
 
 
  type t_fsmState is (rst, idle,        -- controll states
                      -- in com states
                      inRQ, inACK, inWait, inTrans, inThrot,
                      inThrotBreak, inThrotEnd,
                      endInTrans,
                      -- out com states
                      outRQ, outRQdelay, outTrans, outACK, outACKwait,
                      outUSBwait, outUSBwaitEnd, outFIFOwait, endOutTrans);
 
 
 
  signal pr_state, nx_state : t_fsmState;
  -- XST specific synthesize attributes
  attribute safe_recovery_state of pr_state : signal is "idle";
  attribute safe_implementation of pr_state : signal is "yes";
 
 
  -- interconection signals
  signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
 
  -- USB to Xilinx (U2X)
  signal s_U2X_WR_EN : std_logic;
 
  -- Xilinx to USB (X2U)
  signal s_X2U_RD_EN : std_logic;
 
begin
 
 
 
  o_FIFOrst       <= s_FIFOrst;
  o_X2U_RD_EN     <= s_X2U_RD_EN;
  o_WRX           <= s_WRX;
  o_RDYX          <= s_RDYX;
  o_U2X_WR_EN     <= s_U2X_WR_EN;
  o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
  o_ABORT         <= s_ABORT;
 
 
  -----------------------------------------------------------------------------
  -- FSM GPIF
  -----------------------------------------------------------------------------
 
  -- state reg
  action : process(i_IFCLK, i_nReset)
  begin
 
    if i_nReset = '0' then
      pr_state <= rst;
 
    elsif rising_edge(i_IFCLK) then
        pr_state <= nx_state;
    end if;
  end process action;
 
 
  -- comb logic
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
                        i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
  begin  -- process transaction
 
    -- default signal values to avoid latches:
    s_FIFOrst       <= '0';
    s_bus_trans_dir <= readFromGPIF;
    s_U2X_WR_EN     <= '0';
    s_X2U_RD_EN     <= '0';
    nx_state        <= idle;
    s_WRX           <= '0';
    s_RDYX          <= '0';
    s_ABORT         <= '0';
    o_RX            <= '0';
    o_TX            <= '0';
 
    case pr_state is
      -- controll
 
      when rst =>
        -- output signal values:
        s_FIFOrst   <= '1';
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        s_X2U_RD_EN <= '0';
        s_ABORT     <= '1';
        o_RX        <= '0';
        o_TX        <= '0';
        s_bus_trans_dir <= readFromGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        else
          nx_state <= idle;
        end if;
 
      when idle =>
        -- output signal values:
        s_FIFOrst       <= '0';
        s_WRX           <= '0';
        s_RDYX          <= '0';
        s_U2X_WR_EN     <= '0';
        s_X2U_RD_EN     <= '0';
        s_bus_trans_dir <= readFromGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        elsif i_WRU = '0' and
          --(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then
          i_X2U_EMPTY = '0' then
          nx_state <= outRQ;
        else
          nx_state <= idle;
        end if;
 
        -----------------------------------------------------------------------
        -- in trans
      when inRQ =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_U2X_FULL = '0' then
          nx_state <= inACK;
        else
          nx_state <= idle;
        end if;
 
      when inACK =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' then
          nx_state <= inWait;
        else
          nx_state <= endInTrans;
        end if;
 
        when inWait =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        nx_state <= inTrans;
 
      when inTrans =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '1';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' then
          nx_state <= endInTrans;
        elsif i_U2X_AM_FULL = '1' then
          nx_state <= inThrot;
        else
          nx_state <= inTrans;
        end if;
 
      when inThrot =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_U2X_AM_FULL = '0' then
          nx_state <= inThrotBreak;
          --nx_state <= inThrotEnd;
        elsif i_WRU = '0' then
          nx_state <= endInTrans;
        else
          nx_state <= inThrot;
        end if;
 
      when inThrotBreak =>
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions 
        nx_state <= inThrotEnd;
 
      when inThrotEnd =>
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '1';
        s_U2X_WR_EN <= '0';
        o_RX        <= '1';
 
        -- state decisions 
        nx_state <= inTrans;
 
      when endInTrans =>
        -- output signal values:
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        o_RX        <= '0';
 
        -- state decisions
        nx_state <= idle;
 
        -----------------------------------------------------------------------
        -- out trans
      when outRQ =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        else
          nx_state <= outRQdelay;
        end if;
 
      when outRQdelay =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
        else
          nx_state <= outACK;
        end if;
 
      when outACK =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '1';
        o_TX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outACKwait;
        end if;
 
      when outACKwait =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
          s_X2U_RD_EN <= '1';
        else
          nx_state <= outACKwait;
        end if;
 
      when outTrans =>
        -- output signal values:
        s_WRX           <= '1';
        s_RDYX          <= '0';
        s_X2U_RD_EN     <= '1';
        o_TX            <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state        <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_X2U_EMPTY = '1' and i_EOM = '0' then
          nx_state <= outFIFOwait;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
        else
          nx_state <= outUSBwait;
          s_X2U_RD_EN <= '0';
        end if;
 
      when outUSBwait =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outUSBwaitEnd;
        else
          nx_state <= outUSBwait;
        end if;
 
      when outUSBwaitEnd =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '1';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        nx_state <= outTrans;
 
      when outFIFOwait =>
        -- output signal values:
        s_WRX       <= '1';
        s_RDYX      <= '1';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
        elsif i_X2U_EMPTY = '0' then
          nx_state <= outTrans;
          s_X2U_RD_EN <= '1';
        else
          nx_state <= outFIFOwait;
        end if;
 
      when endOutTrans =>
        -- output signal values:
        s_RDYX          <= '0';
        s_WRX           <= '0';
        s_X2U_RD_EN     <= '0';
        s_bus_trans_dir <= writeToGPIF;
 
        -- state decisions
        if i_RDYU = '0' then
          nx_state <= idle;
        else
          nx_state <= endOutTrans;
        end if;
 
        -- error case
      when others =>
        nx_state <= idle;
    end case;
 
  end process transaction;
 
end fsm;

Line No.	Rev	Author	Line
1	14	nussgipfel	`-- GECKO3COM IP Core`
2			`--`
3			`-- Copyright (C) 2009 by`
4			`-- ___ ___ _ _`
5			`-- ( _ \ ( __)( ) ( )`
6			`-- \| (_) )\| ( \| \|_\| \| Bern University of Applied Sciences`
7			`-- \| _ < \| _) \| _ \| School of Engineering and`
8			`-- \| (_) )\| \| \| \| \| \| Information Technology`
9			`-- (____/ (_) (_) (_)`
10			`--`
11			`-- This program is free software: you can redistribute it and/or modify`
12			`-- it under the terms of the GNU General Public License as published by`
13			`-- the Free Software Foundation, either version 3 of the License, or`
14			`-- (at your option) any later version.`
15			`--`
16			`-- This program is distributed in the hope that it will be useful,`
17			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`-- GNU General Public License for more details.`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`--`
23			`-- URL to the project description:`
24			`-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start`
25	18	nussgipfel	`-------------------------------------------------------------------------------`
26	14	nussgipfel	`--`
27			`-- Author: Andreas Habegger, Christoph Zimmermann`
28			`-- Date of creation: 8. April 2009`
29			`-- Description:`
30	18	nussgipfel	`-- FSM that controls the interface between the EZ-USB (and it's internal`
31			`-- GPIF, General Purpose Interface) and our FPGA. The interface is`
32			`-- synchronous, where the GPIF provides the clock. This FSM is synchronous`
33			`-- to the GPIF clock, also this side of the FIFO's.`
34	14	nussgipfel	`--`
35	18	nussgipfel	`-- You can find more detailed information how the interface works in the`
36			`-- ../Doc folder.`
37	14	nussgipfel	`--`
38	18	nussgipfel	`-- Target Devices: general`
39			`-- Tool versions: Xilinx ISE 11.1, XST`
40	14	nussgipfel	`-- Dependencies:`
41			`--`
42	18	nussgipfel	`-------------------------------------------------------------------------------`
43	14	nussgipfel
44	11	nussgipfel	`library ieee;`
45			`use ieee.std_logic_1164.all;`
46			`use ieee.std_logic_arith.all;`
47
48			`library work;`
49	14	nussgipfel	`use work.GECKO3COM_defines.all;`
50	11	nussgipfel
51	14	nussgipfel	`entity gpif_com_fsm is`
52	11	nussgipfel	`port (`
53	20	nussgipfel	`i_nReset : in std_logic;`
54			`i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)`
55			`i_WRU : in std_logic; -- write from GPIF`
56			`i_RDYU : in std_logic; -- GPIF is ready`
57			`i_EOM : in std_logic; -- all data for X2U transfer is in FIFO`
58			`i_U2X_FULL : in std_logic;`
59			`i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO`
60			`i_X2U_FULL_IFCLK : in std_logic;`
61			`i_X2U_AM_EMPTY : in std_logic;`
62			`i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO`
63			`o_bus_trans_dir : out std_logic;`
64			`o_U2X_WR_EN : out std_logic; -- signals for IN FIFO`
65			`o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO`
66			`o_FIFOrst : out std_logic;`
67			`o_WRX : out std_logic; -- To write to GPIF`
68			`o_RDYX : out std_logic; -- Core is ready`
69			`o_ABORT : out std_logic; -- abort condition detected. we have to flush the data`
70			`o_RX : out std_logic;`
71			`o_TX : out std_logic --`
72	18	nussgipfel	`);`
73
74	14	nussgipfel	`end gpif_com_fsm;`
75	11	nussgipfel
76
77
78	14	nussgipfel	`architecture fsm of gpif_com_fsm is`
79	11	nussgipfel
80	19	nussgipfel	`-- XST specific synthesize attributes`
81			`attribute safe_implementation: string;`
82			`attribute safe_recovery_state: string;`
83	27	nussgipfel
84	19	nussgipfel
85	18	nussgipfel	`-----------------------------------------------------------------------------`
86	11	nussgipfel	`-- FSM`
87			`-----------------------------------------------------------------------------`
88
89	18	nussgipfel	`type t_busAccess is (readFromGPIF, writeToGPIF);`
90	14	nussgipfel	`signal s_bus_trans_dir : t_busAccess;`
91
92
93	18	nussgipfel	`type t_fsmState is (rst, idle, -- controll states`
94	28	nussgipfel	`-- in com states`
95	19	nussgipfel	`inRQ, inACK, inWait, inTrans, inThrot,`
96	28	nussgipfel	`inThrotBreak, inThrotEnd,`
97			`endInTrans,`
98			`-- out com states`
99			`outRQ, outRQdelay, outTrans, outACK, outACKwait,`
100			`outUSBwait, outUSBwaitEnd, outFIFOwait, endOutTrans);`
101	11	nussgipfel
102	18	nussgipfel
103
104	11	nussgipfel	`signal pr_state, nx_state : t_fsmState;`
105	18	nussgipfel	`-- XST specific synthesize attributes`
106			`attribute safe_recovery_state of pr_state : signal is "idle";`
107	19	nussgipfel	`attribute safe_implementation of pr_state : signal is "yes";`
108
109	18	nussgipfel
110	11	nussgipfel	`-- interconection signals`
111	18	nussgipfel	`signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;`
112	11	nussgipfel
113	18	nussgipfel	`-- USB to Xilinx (U2X)`
114	12	nussgipfel	`signal s_U2X_WR_EN : std_logic;`
115	11	nussgipfel
116	18	nussgipfel	`-- Xilinx to USB (X2U)`
117			`signal s_X2U_RD_EN : std_logic;`
118
119	11	nussgipfel	`begin`
120
121	19	nussgipfel
122
123	18	nussgipfel	`o_FIFOrst <= s_FIFOrst;`
124			`o_X2U_RD_EN <= s_X2U_RD_EN;`
125			`o_WRX <= s_WRX;`
126			`o_RDYX <= s_RDYX;`
127			`o_U2X_WR_EN <= s_U2X_WR_EN;`
128	14	nussgipfel	`o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';`
129	18	nussgipfel	`o_ABORT <= s_ABORT;`
130	11	nussgipfel
131	18	nussgipfel
132	11	nussgipfel	`-----------------------------------------------------------------------------`
133			`-- FSM GPIF`
134			`-----------------------------------------------------------------------------`
135
136	18	nussgipfel	`-- state reg`
137	11	nussgipfel	`action : process(i_IFCLK, i_nReset)`
138	18	nussgipfel	`begin`
139	11	nussgipfel
140	18	nussgipfel	`if i_nReset = '0' then`
141			`pr_state <= rst;`
142
143			`elsif rising_edge(i_IFCLK) then`
144			`pr_state <= nx_state;`
145			`end if;`
146			`end process action;`
147	11	nussgipfel
148
149	18	nussgipfel	`-- comb logic`
150	20	nussgipfel	`transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,`
151			`i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)`
152	18	nussgipfel	`begin -- process transaction`
153	11	nussgipfel
154	18	nussgipfel	`-- default signal values to avoid latches:`
155			`s_FIFOrst <= '0';`
156			`s_bus_trans_dir <= readFromGPIF;`
157			`s_U2X_WR_EN <= '0';`
158			`s_X2U_RD_EN <= '0';`
159			`nx_state <= idle;`
160			`s_WRX <= '0';`
161			`s_RDYX <= '0';`
162			`s_ABORT <= '0';`
163			`o_RX <= '0';`
164			`o_TX <= '0';`
165
166			`case pr_state is`
167			`-- controll`
168
169			`when rst =>`
170			`-- output signal values:`
171			`s_FIFOrst <= '1';`
172			`s_WRX <= '0';`
173			`s_RDYX <= '0';`
174			`s_U2X_WR_EN <= '0';`
175			`s_X2U_RD_EN <= '0';`
176			`s_ABORT <= '1';`
177			`o_RX <= '0';`
178			`o_TX <= '0';`
179			`s_bus_trans_dir <= readFromGPIF;`
180
181			`-- state decisions`
182			`if i_WRU = '1' and i_RDYU = '1' then`
183			`nx_state <= rst;`
184			`else`
185			`nx_state <= idle;`
186			`end if;`
187	11	nussgipfel
188	18	nussgipfel	`when idle =>`
189			`-- output signal values:`
190			`s_FIFOrst <= '0';`
191			`s_WRX <= '0';`
192			`s_RDYX <= '0';`
193			`s_U2X_WR_EN <= '0';`
194			`s_X2U_RD_EN <= '0';`
195			`s_bus_trans_dir <= readFromGPIF;`
196	11	nussgipfel
197	18	nussgipfel	`-- state decisions`
198			`if i_WRU = '1' and i_RDYU = '1' then`
199			`nx_state <= rst;`
200			`elsif i_WRU = '1' and i_RDYU = '0' then`
201			`nx_state <= inRQ;`
202	20	nussgipfel	`elsif i_WRU = '0' and`
203	29	nussgipfel	`--(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then`
204			`i_X2U_EMPTY = '0' then`
205	18	nussgipfel	`nx_state <= outRQ;`
206			`else`
207			`nx_state <= idle;`
208			`end if;`
209
210	20	nussgipfel	`-----------------------------------------------------------------------`
211	11	nussgipfel	`-- in trans`
212	28	nussgipfel	`when inRQ =>`
213	18	nussgipfel	`-- output signal values:`
214	28	nussgipfel	`s_WRX <= '0';`
215			`s_RDYX <= '0';`
216	19	nussgipfel	`s_U2X_WR_EN <= '0';`
217			`o_RX <= '0';`
218
219	18	nussgipfel	`-- state decisions`
220			`if i_WRU = '1' and i_RDYU = '1' then`
221			`nx_state <= rst;`
222			`elsif i_U2X_FULL = '0' then`
223			`nx_state <= inACK;`
224			`else`
225			`nx_state <= idle;`
226			`end if;`
227	11	nussgipfel
228	18	nussgipfel	`when inACK =>`
229			`-- output signal values:`
230			`s_WRX <= '0';`
231			`s_RDYX <= '1';`
232	19	nussgipfel	`s_U2X_WR_EN <= '0';`
233	18	nussgipfel	`o_RX <= '1';`
234	11	nussgipfel
235	18	nussgipfel	`-- state decisions`
236			`if i_WRU = '1' and i_RDYU = '1' then`
237			`nx_state <= rst;`
238			`elsif i_WRU = '1' then`
239	19	nussgipfel	`nx_state <= inWait;`
240	18	nussgipfel	`else`
241			`nx_state <= endInTrans;`
242			`end if;`
243	19	nussgipfel
244			`when inWait =>`
245			`-- output signal values:`
246			`s_WRX <= '0';`
247			`s_RDYX <= '1';`
248			`s_U2X_WR_EN <= '0';`
249			`o_RX <= '1';`
250
251			`-- state decisions`
252			`nx_state <= inTrans;`
253	18	nussgipfel
254			`when inTrans =>`
255			`-- output signal values:`
256			`s_WRX <= '0';`
257			`s_RDYX <= '1';`
258			`s_U2X_WR_EN <= '1';`
259			`o_RX <= '1';`
260	11	nussgipfel
261	18	nussgipfel	`-- state decisions`
262			`if i_WRU = '1' and i_RDYU = '1' then`
263			`nx_state <= rst;`
264			`elsif i_WRU = '0' then`
265			`nx_state <= endInTrans;`
266	20	nussgipfel	`elsif i_U2X_AM_FULL = '1' then`
267	18	nussgipfel	`nx_state <= inThrot;`
268			`else`
269			`nx_state <= inTrans;`
270			`end if;`
271	11	nussgipfel
272	18	nussgipfel	`when inThrot =>`
273			`-- output signal values:`
274			`s_WRX <= '0';`
275			`s_RDYX <= '0';`
276			`s_U2X_WR_EN <= '0';`
277			`o_RX <= '1';`
278	11	nussgipfel
279	18	nussgipfel	`-- state decisions`
280			`if i_WRU = '1' and i_RDYU = '1' then`
281			`nx_state <= rst;`
282	20	nussgipfel	`elsif i_U2X_AM_FULL = '0' then`
283	19	nussgipfel	`nx_state <= inThrotBreak;`
284	20	nussgipfel	`--nx_state <= inThrotEnd;`
285	18	nussgipfel	`elsif i_WRU = '0' then`
286			`nx_state <= endInTrans;`
287			`else`
288			`nx_state <= inThrot;`
289			`end if;`
290	11	nussgipfel
291	19	nussgipfel	`when inThrotBreak =>`
292			`-- this is a one clock delay to help the fx2 to see the RDYX signal.`
293
294			`-- output signal values:`
295			`s_WRX <= '0';`
296			`s_RDYX <= '1';`
297			`s_U2X_WR_EN <= '0';`
298			`o_RX <= '1';`
299
300			`-- state decisions`
301			`nx_state <= inThrotEnd;`
302	18	nussgipfel
303	19	nussgipfel	`when inThrotEnd =>`
304			`-- this is a one clock delay to help the fx2 to see the RDYX signal.`
305
306			`-- output signal values:`
307			`s_WRX <= '0';`
308			`s_RDYX <= '1';`
309			`s_U2X_WR_EN <= '0';`
310			`o_RX <= '1';`
311
312			`-- state decisions`
313			`nx_state <= inTrans;`
314
315	18	nussgipfel	`when endInTrans =>`
316			`-- output signal values:`
317			`s_WRX <= '0';`
318			`s_RDYX <= '0';`
319	19	nussgipfel	`s_U2X_WR_EN <= '0';`
320			`o_RX <= '0';`
321	18	nussgipfel
322			`-- state decisions`
323			`nx_state <= idle;`
324
325	20	nussgipfel	`-----------------------------------------------------------------------`
326	11	nussgipfel	`-- out trans`
327	18	nussgipfel	`when outRQ =>`
328			`-- output signal values:`
329	20	nussgipfel	`s_WRX <= '1';`
330			`s_RDYX <= '0';`
331			`s_X2U_RD_EN <= '0';`
332	18	nussgipfel
333			`-- state decisions`
334			`if i_WRU = '1' and i_RDYU = '1' then`
335			`nx_state <= rst;`
336			`elsif i_WRU = '1' and i_RDYU = '0' then`
337			`nx_state <= inRQ;`
338			`else`
339	27	nussgipfel	`nx_state <= outRQdelay;`
340	18	nussgipfel	`end if;`
341	11	nussgipfel
342	27	nussgipfel	`when outRQdelay =>`
343			`-- output signal values:`
344			`s_WRX <= '1';`
345			`s_RDYX <= '0';`
346			`s_X2U_RD_EN <= '0';`
347
348			`-- state decisions`
349			`if i_WRU = '1' and i_RDYU = '1' then`
350			`nx_state <= rst;`
351			`elsif i_WRU = '1' and i_RDYU = '0' then`
352			`nx_state <= inRQ;`
353			`else`
354			`nx_state <= outACK;`
355			`end if;`
356
357	28	nussgipfel	`when outACK =>`
358	20	nussgipfel	`-- output signal values:`
359			`s_WRX <= '1';`
360			`s_RDYX <= '0';`
361			`s_X2U_RD_EN <= '1';`
362			`o_TX <= '1';`
363	11	nussgipfel
364	20	nussgipfel	`-- state decisions`
365			`if i_WRU = '1' and i_RDYU = '1' then`
366			`nx_state <= rst;`
367			`elsif i_WRU = '0' and i_RDYU = '1' then`
368			`nx_state <= outTrans;`
369			`else`
370	28	nussgipfel	`nx_state <= outACKwait;`
371			`end if;`
372
373			`when outACKwait =>`
374			`-- output signal values:`
375			`s_WRX <= '1';`
376			`s_RDYX <= '0';`
377			`s_X2U_RD_EN <= '0';`
378			`o_TX <= '1';`
379
380			`-- state decisions`
381			`if i_WRU = '1' and i_RDYU = '1' then`
382			`nx_state <= rst;`
383			`elsif i_WRU = '0' and i_RDYU = '1' then`
384			`nx_state <= outTrans;`
385	29	nussgipfel	`s_X2U_RD_EN <= '1';`
386	28	nussgipfel	`else`
387			`nx_state <= outACKwait;`
388	20	nussgipfel	`end if;`
389	28	nussgipfel
390	18	nussgipfel	`when outTrans =>`
391			`-- output signal values:`
392			`s_WRX <= '1';`
393			`s_RDYX <= '0';`
394			`s_X2U_RD_EN <= '1';`
395	20	nussgipfel	`o_TX <= '1';`
396	18	nussgipfel	`s_bus_trans_dir <= writeToGPIF;`
397
398			`-- state decisions`
399			`if i_WRU = '1' and i_RDYU = '1' then`
400			`nx_state <= rst;`
401	20	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
402	18	nussgipfel	`nx_state <= endOutTrans;`
403	20	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '0' then`
404			`nx_state <= outFIFOwait;`
405	18	nussgipfel	`elsif i_WRU = '0' and i_RDYU = '1' then`
406			`nx_state <= outTrans;`
407			`else`
408	28	nussgipfel	`nx_state <= outUSBwait;`
409	29	nussgipfel	`s_X2U_RD_EN <= '0';`
410	18	nussgipfel	`end if;`
411
412	20	nussgipfel	`when outUSBwait =>`
413	18	nussgipfel	`-- output signal values:`
414			`s_WRX <= '1';`
415			`s_RDYX <= '0';`
416			`s_X2U_RD_EN <= '0';`
417			`o_TX <= '1';`
418			`s_bus_trans_dir <= writeToGPIF;`
419
420			`-- state decisions`
421			`if i_WRU = '1' and i_RDYU = '1' then`
422			`nx_state <= rst;`
423	27	nussgipfel	`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
424			`nx_state <= endOutTrans;`
425	18	nussgipfel	`elsif i_WRU = '0' and i_RDYU = '1' then`
426	28	nussgipfel	`nx_state <= outUSBwaitEnd;`
427	18	nussgipfel	`else`
428	20	nussgipfel	`nx_state <= outUSBwait;`
429	18	nussgipfel	`end if;`
430	29	nussgipfel
431	28	nussgipfel	`when outUSBwaitEnd =>`
432			`-- output signal values:`
433			`s_WRX <= '1';`
434	29	nussgipfel	`s_RDYX <= '0';`
435			`s_X2U_RD_EN <= '1';`
436	28	nussgipfel	`o_TX <= '1';`
437			`s_bus_trans_dir <= writeToGPIF;`
438
439			`-- state decisions`
440			`nx_state <= outTrans;`
441	18	nussgipfel
442	20	nussgipfel	`when outFIFOwait =>`
443			`-- output signal values:`
444			`s_WRX <= '1';`
445			`s_RDYX <= '1';`
446			`s_X2U_RD_EN <= '0';`
447			`o_TX <= '1';`
448			`s_bus_trans_dir <= writeToGPIF;`
449
450			`-- state decisions`
451			`if i_WRU = '1' and i_RDYU = '1' then`
452			`nx_state <= rst;`
453			`elsif i_X2U_EMPTY = '1' and i_EOM = '1' then`
454			`nx_state <= endOutTrans;`
455	27	nussgipfel	`elsif i_X2U_EMPTY = '0' then`
456	20	nussgipfel	`nx_state <= outTrans;`
457	29	nussgipfel	`s_X2U_RD_EN <= '1';`
458	20	nussgipfel	`else`
459			`nx_state <= outFIFOwait;`
460			`end if;`
461
462	18	nussgipfel	`when endOutTrans =>`
463			`-- output signal values:`
464			`s_RDYX <= '0';`
465	20	nussgipfel	`s_WRX <= '0';`
466			`s_X2U_RD_EN <= '0';`
467	18	nussgipfel	`s_bus_trans_dir <= writeToGPIF;`
468
469			`-- state decisions`
470	20	nussgipfel	`if i_RDYU = '0' then`
471			`nx_state <= idle;`
472			`else`
473			`nx_state <= endOutTrans;`
474			`end if;`
475	18	nussgipfel
476	11	nussgipfel	`-- error case`
477	18	nussgipfel	`when others =>`
478			`nx_state <= idle;`
479			`end case;`
480	11	nussgipfel
481	18	nussgipfel	`end process transaction;`
482
483			`end fsm;`

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