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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com_test.vhd] - Blame information for rev 19

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Line No. Rev Author Line
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--  GECKO3COM IP Core
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--
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--  Copyright (C) 2009 by
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--   ___    ___   _   _
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--  (  _ \ (  __)( ) ( )
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--  | (_) )| (   | |_| |   Bern University of Applied Sciences
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--  |  _ < |  _) |  _  |   School of Engineering and
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--  | (_) )| |   | | | |   Information Technology
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--  (____/ (_)   (_) (_)
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details. 
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--  URL to the project description: 
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--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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--------------------------------------------------------------------------------
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--
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--  Author: Christoph Zimmermann
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--  Date of creation: 8. April 2009
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--  Description:
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--    First test scenario for the GECKO3com IP core. 
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--    This module (to be implemented as top module) is used to test the
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--    low-level communication between the GPIF from the EZ-USB and the FPGA.
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--    For this, it instantiates the the gpif_com module, reads all the 
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--    received data from the FIFO (and puts them to nowhere) and writes a pre
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--    defined USB TMC response packet to the send FIFO.
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--
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--    If you would like to change the USB TMC response, you have to change the 
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--    ROM content in this file (don't forget to adjust the the transfer size 
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--    field AND the counter limit).
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--
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--  Target Devices:     Xilinx Spartan3 FPGA's (usage of BlockRam in the
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--                      Datapath)
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--  Tool versions:      11.1
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--  Dependencies:
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library work;
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use work.GECKO3COM_defines.all;
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entity gpif_com_test is
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  port (
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    i_nReset   : in    std_logic;
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    i_IFCLK    : in    std_logic;       -- GPIF CLK (GPIF is Master and provides the clock)
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    i_SYSCLK   : in    std_logic;       -- FPGA System CLK
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    i_WRU      : in    std_logic;       -- write from GPIF
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    i_RDYU     : in    std_logic;       -- GPIF is ready
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    o_WRX      : out   std_logic;       -- To write to GPIF
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    o_RDYX     : out   std_logic;       -- IP Core is ready
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    b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- bidirect data bus
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    o_LEDrx    : out   std_logic;       -- controll LED rx
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    o_LEDtx    : out   std_logic;       -- controll LED tx
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    o_LEDrun   : out   std_logic;       -- controll LED running signalisation
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    o_dummy    : out   std_logic        -- dummy output for RX data consumer
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    );
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end gpif_com_test;
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architecture behaviour of gpif_com_test is
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  -----------------------------------------------------------------------------
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  -- controll bus
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  -----------------------------------------------------------------------------
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  signal s_EMPTY, s_FULL : std_logic;
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  signal s_RX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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  signal s_RD_EN, s_WR_EN : std_logic;
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  signal s_TX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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  signal s_ABORT, s_ABORT_TMP : std_logic;
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  signal s_RX_DATA_TMP : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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  signal s_EMPTY_TMP, s_FULL_TMP : std_logic;
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  signal s_rom_adress : std_logic_vector(4 downto 0);
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  ----------------------------------------------------------------------------- 
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  --     COMPONENTS  
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  -----------------------------------------------------------------------------
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  component gpif_com
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    port (
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      i_nReset   : in    std_logic;
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      i_SYSCLK   : in    std_logic;
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      o_ABORT    : out   std_logic;
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      o_RX       : out   std_logic;
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      o_TX       : out   std_logic;
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      i_RD_EN    : in    std_logic;
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      o_EMPTY    : out   std_logic;
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      o_RX_DATA  : out   std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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      i_WR_EN    : in    std_logic;
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      o_FULL     : out   std_logic;
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      i_TX_DATA  : in    std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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      i_IFCLK    : in    std_logic;
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      i_WRU      : in    std_logic;
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      i_RDYU     : in    std_logic;
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      o_WRX      : out   std_logic;
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      o_RDYX     : out   std_logic;
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      b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));
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  end component;
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  component message_rom
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    port (
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      A : in  std_logic_vector(4 downto 0);
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      D : out std_logic_vector(15 downto 0));
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  end component;
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begin  -- behaviour
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  GPIF_INTERFACE: gpif_com
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    port map (
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      i_nReset   => i_nReset,
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      i_SYSCLK   => i_SYSCLK,
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      o_ABORT    => s_ABORT,
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      o_RX       => o_LEDrx,
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      o_TX       => o_LEDtx,
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      i_RD_EN    => s_RD_EN,
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      o_EMPTY    => s_EMPTY,
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      o_RX_DATA  => s_RX_DATA,
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      i_WR_EN    => s_WR_EN,
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      o_FULL     => s_FULL,
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      i_TX_DATA  => s_TX_DATA,
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      --i_IFCLK    => i_SYSCLK,
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      i_IFCLK    => i_IFCLK,
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      i_WRU      => i_WRU,
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      i_RDYU     => i_RDYU,
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      o_WRX      => o_WRX,
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      o_RDYX     => o_RDYX,
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      b_gpif_bus => b_gpif_bus);
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  o_LEDrun <= '1';
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  -----------------------------------------------------------------------------
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  --     RX DATA CONSUMER WITH THROTLING  
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  -----------------------------------------------------------------------------
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  -- purpose: activates the read enable signal of the receive FIFO as slow as
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  -- you want.
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  -- type   : sequential
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  -- inputs : i_SYSCLK
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  -- outputs: s_RX_DATA_TMP
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  rx_throtling: process (i_SYSCLK, i_nReset)
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    -- counter variable
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    variable v_rx_throtle_count : std_logic_vector(6 downto 0);
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  begin
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    if i_nReset = '0' then
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      v_rx_throtle_count := (others => '0');
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      s_RD_EN <= '0';
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    elsif i_SYSCLK = '1' and i_SYSCLK'event then
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      if v_rx_throtle_count >= 2 then
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        s_RD_EN <= '1';
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        v_rx_throtle_count := (others => '0');
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      else
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        v_rx_throtle_count := v_rx_throtle_count + 1;
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        s_RD_EN <= '0';
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      end if;
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    end if;
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  end process rx_throtling;
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  -- purpose: reads the receive data from the GPIF interface
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  -- type   : sequential
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  -- inputs : i_SYSCLK
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  -- outputs: s_RX_DATA_TMP
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  rx_consumer: process (i_SYSCLK)
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  begin  -- process rx_consumer
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    if i_SYSCLK = '1' and i_SYSCLK'event then
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      s_RX_DATA_TMP <= s_RX_DATA;
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      s_EMPTY_TMP <= s_EMPTY;
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      s_FULL_TMP <= s_FULL;
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      s_ABORT_TMP <= s_ABORT;
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    end if;
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  end process rx_consumer;
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  -- dummy logic to "use" these signals and avoid that they are removed by
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  -- the optimizer
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  process(s_RX_DATA_TMP, s_EMPTY_TMP, s_FULL_TMP, s_ABORT_TMP)
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    variable result : std_logic := '0';
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  begin
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    result := '0';
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    for i in s_RX_DATA_TMP'range loop
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      result := result or s_RX_DATA_TMP(i);
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    end loop;
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    o_dummy <= result or s_EMPTY_TMP or s_FULL_TMP or s_ABORT_TMP;
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  end process;
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  -----------------------------------------------------------------------------
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  --     RESPONSE MESSAGE GENERATOR  
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  -----------------------------------------------------------------------------
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  message_rom_1: message_rom
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    port map (
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      A => s_rom_adress,
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      D => s_TX_DATA);
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  -- purpose: counts up the rom adress lines to read out the response message
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  -- type   : sequential
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  -- inputs : i_SYSCLK
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  -- outputs: s_RX_DATA_TMP
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  rom_adress_counter: process (i_SYSCLK, i_nReset)
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  begin
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    if i_nReset = '0' then
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      s_rom_adress <= (others => '0');
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      --s_WR_EN <= '1';
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      s_WR_EN <= '0';
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    elsif i_SYSCLK = '1' and i_SYSCLK'event then
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      if s_rom_adress = 24 then
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        s_rom_adress <= s_rom_adress;
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        s_WR_EN <= '0';
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      else
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        s_rom_adress <= s_rom_adress + 1;
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        --s_WR_EN <= '1';
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        s_WR_EN <= '0';
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      end if;
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    end if;
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  end process rom_adress_counter;
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end behaviour;

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