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ktt1 |
/******************************************************************************/
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/* _ _ __ ____ */
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/* / / | | / _| | __| */
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/* | |_| | _ _ / / | |_ */
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/* | _ | | | | | | | | _| */
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/* | | | | | |_| | \ \_ | |__ */
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/* |_| |_| \_____| \__| |____| microLab */
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/* */
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/* Bern University of Applied Sciences (BFH) */
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/* Quellgasse 21 */
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/* Room HG 4.33 */
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/* 2501 Biel/Bienne */
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/* Switzerland */
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/* */
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/* http://www.microlab.ch */
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/******************************************************************************/
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/* GECKO4COM
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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Parts of this code are based on the USRP2 firmware (GNU Radio Project),
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version 3.0.2, Copyright 2003 Free Software Foundation, Inc
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********************************************************************
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*/
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#include "fx2regs.h"
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#include "isr.h"
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#include "fx2utils.h"
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#include "usb_common.h"
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#include "usb_requests.h"
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#include "syncdelay.h"
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sbit at 0x80+0 PA0;
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sbit at 0x80+1 PA1;
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sbit at 0x80+2 PA2;
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sbit at 0x80+3 PA3;
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sbit at 0x80+4 PA4;
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sbit at 0x80+5 PA5;
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sbit at 0x80+6 PA6;
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sbit at 0x80+7 PA7;
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#define USB_TMC_STATUS_SUCCESS 1
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#define USB_TMC_INDICATOR_PULSE_MASK 1<<2
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#define USB_TMC_INITIATE_ABORT_BULK_OUT 1
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#define USB_TMC_CHECK_ABORT_BULK_OUT_STATUS 2
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#define USB_TMC_INITIATE_ABORT_BULK_IN 3
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#define USB_TMC_CHECK_ABORT_BULK_IN_STATUS 4
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#define USB_TMC_INITIATE_CLEAR 5
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#define USB_TMC_CHECK_CLEAR_STATUS 6
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#define USB_TMC_GET_CAPABILITIES 7
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#define USB_TMC_INDICATOR_PULSE 64
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#define USB_TMC_READ_STATUS_BYTE 128
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#define IFCONFIG_INTERNAL_CLOCK 1<<7
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#define IFCONFIG_INTERNAL_48MHZ_Clock 1<<6
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#define IFCONFIG_DRIVE_IFCLK_PIN 1<<5
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#define IFCONFIG_INVERT_IFCLK 1<<4
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#define IFCONFIG_ASYNC_MODE 1<<3
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#define IFCONFIG_USE_GSTATE 1<<2
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#define IFCONFIG_USE_GPIF 2
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#define IFCONFIG_USE_FIFOS 3
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#define FIXED_EP2_PROG_FLAG 4
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#define FIXED_EP4_PROG_FLAG 5
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#define FIXED_EP6_PROG_FLAG 6
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#define FIXED_EP8_PROG_FLAG 7
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#define FIXED_EP2_EMPTY_FLAG 8
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#define FIXED_EP4_EMPTY_FLAG 9
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#define FIXED_EP6_EMPTY_FLAG 10
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#define FIXED_EP8_EMPTY_FLAG 11
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#define FIXED_EP2_FULL_FLAG 12
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#define FIXED_EP4_FULL_FLAG 13
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#define FIXED_EP6_FULL_FLAG 14
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#define FIXED_EP8_FULL_FLAG 15
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#define PORT_A_USE_FLAGD 1 << 7
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#define PORT_A_USE_SLCS 1 << 6
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#define PORT_A_USE_INT1 2
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#define PORT_A_USE_INT0 1
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#define PKTEND_ACTIVE_HIGH 1<<5
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#define SLOE_ACTIVE_HIGH 1<<4
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#define SLRD_ACTIVE_HIGH 1<<3
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#define SLWR_ACTIVE_HIGH 1<<2
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#define EMPTY_FLAG_ACTIVE_HIGH 2
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#define FULL_FLAG_ACTIVE_HIGH 1
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#define DISABLE_AUTO_ARMING 2
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#define ENABLE_ENHANCED_PACKET_HANDLING 1
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#define ACTIVE_ENDPOINT 1 << 7
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#define IN_ENDPOINT 1<<6
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#define ISOCHRONOUS_MODE 1 << 4
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#define BULK_MODE 2 << 4
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#define INTERRUPT_MODE 3 << 4
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#define SIZE_1KB 1<<3
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#define QUAD_BUFFERING 0
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#define DOUBLE_BUFFERING 2
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#define TRIPLE_BUFFERING 3
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#define FIFO_IN_EARLY 1 << 6
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#define FIFO_OUT_EARLY 1 << 5
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#define FIFO_AUTO_OUT 1 << 4
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#define FIFO_AUTO_IN 1 << 3
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#define FIFO_ZEROLEN 1 << 2
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#define FIFO_WORDWIDE 1
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extern xdata char device_bus_attributes_hs[];
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extern xdata char device_bus_attributes_fs[];
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unsigned char app_class_cmd(void) {
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switch (bRequestType) {
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case 0xA1 : switch (bRequest) {
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case USB_TMC_GET_CAPABILITIES :
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BUF[1] = 0;
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EP0BUF[2] = 0;
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EP0BUF[3] = 1;
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EP0BUF[4] = USB_TMC_INDICATOR_PULSE_MASK;
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EP0BUF[5] = 0;
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EP0BUF[6] = 0;
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EP0BUF[7] = 0;
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EP0BUF[8] = 0;
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EP0BUF[9] = 0;
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EP0BUF[10] = 0;
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EP0BUF[11] = 0;
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EP0BUF[12] = 0;
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EP0BUF[13] = 1;
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EP0BUF[14] = 0;
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EP0BUF[15] = 0;
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EP0BUF[16] = 0;
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EP0BUF[17] = 0;
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EP0BUF[18] = 0;
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EP0BUF[19] = 0;
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EP0BUF[20] = 0;
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EP0BUF[21] = 0;
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EP0BUF[22] = 0;
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EP0BUF[23] = 0;
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EP0BCH = 0;
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EP0BCL = 0x18;
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return 1;
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case USB_TMC_INDICATOR_PULSE :
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IOD = 0xEF; /* indicator pulse */
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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IOD = 0xFF;
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EP0BCH = 0;
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EP0BCL = 1;
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return 1;
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case USB_TMC_INITIATE_CLEAR :
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/* reset the stuff in the FPGA */
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PA1 = 1;
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NOP;
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PA1 = 0;
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BCH = 0;
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EP0BCL = 1;
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return 1;
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case USB_TMC_CHECK_CLEAR_STATUS :
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BUF[1] = 0;
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EP0BCH = 0;
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EP0BCL = 2;
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return 1;
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case USB_TMC_READ_STATUS_BYTE :
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IOD = 0xFF; /* select the USB488 status word */
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BUF[1] = wValueL;
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EP0BUF[2] = (IOD&0xF)<<2;/*status byte*/
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EP0BCH = 0;
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EP0BCL = 3;
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return 1;
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default : break;
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}
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/* TODO: finish the abort handling! */
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case 0xA2 : switch (bRequest) {
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case USB_TMC_INITIATE_ABORT_BULK_OUT :
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IOD = 0xCF; /* read btag lo nibble */
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BUF[1] = IOD&0xF;
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IOD= 0xDF; /* read btag hi nibble */
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EP0BCH = 0;
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EP0BUF[1] |= (IOD&0xF)<<4;
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EP0BCL = 2;
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return 1;
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case USB_TMC_CHECK_ABORT_BULK_OUT_STATUS :
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BUF[1] = 0;
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EP0BUF[2] = 0;
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EP0BUF[3] = 0;
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EP0BUF[4] = 0;
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EP0BUF[5] = 0;
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EP0BUF[6] = 0;
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EP0BUF[7] = 0;
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EP0BCH = 0;
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EP0BCL = 8;
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return 1;
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case USB_TMC_INITIATE_ABORT_BULK_IN :
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IOD = 0xCF; /* read btag lo nibble */
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BUF[1] = IOD&0xF;
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IOD= 0xDF; /* read btag hi nibble */
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EP0BCH = 0;
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EP0BUF[1] |= (IOD&0xF)<<4;
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EP0BCL = 2;
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return 1;
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case USB_TMC_CHECK_ABORT_BULK_IN_STATUS :
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EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
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EP0BUF[1] = 0;
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EP0BUF[2] = 0;
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EP0BUF[3] = 0;
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EP0BUF[4] = 0;
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EP0BUF[5] = 0;
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EP0BUF[6] = 0;
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EP0BUF[7] = 0;
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EP0BCH = 0;
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EP0BCL = 8;
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return 1;
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default : break;
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}
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default : break;
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}
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return 0;
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}
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unsigned char app_vendor_cmd(void) {
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return 0;
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}
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void setup_endpoint_fifos() {
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/* IMPORTANT: Endpoint configurations:
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EP6 => USBTMC IN endpoint (to PC) double buffered 512 bytes
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EP8 => USBTMC OUT endpoint (from PC) double buffered 512 bytes
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both endpoints are 8 bytes fifo
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*/
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IFCONFIG = IFCONFIG_USE_FIFOS;
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SYNCDELAY;
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SYNCDELAY;
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PORTACFG = PORT_A_USE_FLAGD | PORT_A_USE_INT0;
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SYNCDELAY;
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PINFLAGSAB = (FIXED_EP6_FULL_FLAG << 4)|
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FIXED_EP8_EMPTY_FLAG; /* Flag B is EP6 Full Flag; Flag A is EP8 Empty Flag */
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SYNCDELAY;
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PINFLAGSCD = (FIXED_EP4_FULL_FLAG << 4)|
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FIXED_EP2_EMPTY_FLAG;
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SYNCDELAY;
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FIFOPINPOLAR = 0; /* All FIFO signals active low */
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SYNCDELAY;
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REVCTL = 0; /* Auto Arming and no enhanced packet handling */
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SYNCDELAY;
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EP2CFG=0; /* Disabled endpoint */
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SYNCDELAY;
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EP4CFG=0; /* Disabled endpoint */
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SYNCDELAY;
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EP6CFG=ACTIVE_ENDPOINT|IN_ENDPOINT|BULK_MODE|DOUBLE_BUFFERING;
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SYNCDELAY;
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EP8CFG=ACTIVE_ENDPOINT|BULK_MODE; /* fixed to double buffering ! */
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SYNCDELAY;
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EP2FIFOCFG = 0;
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SYNCDELAY;
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EP4FIFOCFG = 0;
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SYNCDELAY;
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EP6FIFOCFG = 0;
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SYNCDELAY;
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EP8FIFOCFG = 0;
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SYNCDELAY; /* Set all FIFOs to passive byte wide */
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| 275 |
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| 276 |
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| 277 |
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FIFORESET=0x80;
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| 278 |
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SYNCDELAY;
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| 279 |
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FIFORESET=0x02;
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| 280 |
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SYNCDELAY;
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| 281 |
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FIFORESET=0x04;
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| 282 |
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SYNCDELAY;
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| 283 |
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FIFORESET=0x06;
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| 284 |
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SYNCDELAY;
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| 285 |
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FIFORESET=0x08;
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| 286 |
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SYNCDELAY;
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| 287 |
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FIFORESET=0x00;
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| 288 |
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SYNCDELAY; /* Reset all FIFOs */
|
| 289 |
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| 290 |
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EP8FIFOCFG=FIFO_AUTO_OUT|FIFO_OUT_EARLY; /* Autoout and OUTEARLY */
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| 291 |
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SYNCDELAY;
|
| 292 |
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EP6FIFOCFG=FIFO_IN_EARLY;
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| 293 |
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SYNCDELAY;
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| 294 |
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| 295 |
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| 296 |
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}
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| 297 |
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| 298 |
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| 299 |
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| 300 |
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void main(void) {
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| 301 |
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EA = 0; /* disable all interrupts */
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| 302 |
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|
| 303 |
|
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PA1 = 1; /* indicate to the FPGA that the FX2 is still setting up things */
|
| 304 |
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PA3 = 0; /* Indicate to the FPGA that the FX2 uses full speed */
|
| 305 |
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OEA = 1<<3|1<<1; /* PA1 and PA3 are set to output, the rest of the pins as input */
|
| 306 |
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| 307 |
|
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setup_autovectors();
|
| 308 |
|
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usb_install_handlers();
|
| 309 |
|
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setup_endpoint_fifos();
|
| 310 |
|
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OED = 0xF0; /* The high 4 pins of the d-port are outputs the low 4 are inputs */
|
| 311 |
|
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IOD = 0xFF; /* select the USB488 status word */
|
| 312 |
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|
| 313 |
|
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EA = 1; /* enable all interrupts */
|
| 314 |
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|
| 315 |
|
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fx2_renumerate();
|
| 316 |
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|
| 317 |
|
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/* now everything should be fine */
|
| 318 |
|
|
PA1 = 0; /* indicate to the FPGA that the FX2 is ready */
|
| 319 |
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|
| 320 |
|
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while (1) {
|
| 321 |
|
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if(usb_setup_packet_avail()) usb_handle_setup_packet();
|
| 322 |
|
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}
|
| 323 |
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}
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