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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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-- The unisim library is used for simulation of the xilinx specific components
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-- For generic usage please use:
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-- LIBRARY work;
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-- USE work.xilinx_generic.all;
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-- And use the xilinx generic package found in the xilinx generic module
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LIBRARY unisim;
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USE unisim.all;
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ARCHITECTURE xilinx OF cmd_18_1e_if IS
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COMPONENT RAMB16_S9
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GENERIC ( INIT_00 : bit_vector;
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INIT_01 : bit_vector;
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INIT_02 : bit_vector;
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INIT_03 : bit_vector;
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INIT_04 : bit_vector;
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INIT_05 : bit_vector;
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INIT_06 : bit_vector;
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INIT_07 : bit_vector;
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INIT_08 : bit_vector;
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INIT_09 : bit_vector;
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INIT_0A : bit_vector;
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INIT_0B : bit_vector;
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INIT_0C : bit_vector;
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INIT_0D : bit_vector;
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INIT_0E : bit_vector;
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INIT_0F : bit_vector;
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INIT_10 : bit_vector;
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INIT_11 : bit_vector;
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INIT_12 : bit_vector;
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INIT_13 : bit_vector;
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INIT_14 : bit_vector;
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INIT_15 : bit_vector;
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INIT_16 : bit_vector;
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INIT_17 : bit_vector;
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INIT_18 : bit_vector;
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INIT_19 : bit_vector;
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INIT_1A : bit_vector;
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INIT_1B : bit_vector;
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INIT_1C : bit_vector;
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INIT_1D : bit_vector;
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INIT_1E : bit_vector;
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INIT_1F : bit_vector;
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INIT_20 : bit_vector;
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INIT_21 : bit_vector;
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INIT_22 : bit_vector;
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INIT_23 : bit_vector;
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INIT_24 : bit_vector;
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INIT_25 : bit_vector;
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INIT_26 : bit_vector;
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INIT_27 : bit_vector;
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INIT_28 : bit_vector;
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INIT_29 : bit_vector;
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INIT_2A : bit_vector;
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INIT_2B : bit_vector;
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INIT_2C : bit_vector;
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INIT_2D : bit_vector;
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INIT_2E : bit_vector;
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INIT_2F : bit_vector;
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INIT_30 : bit_vector;
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INIT_31 : bit_vector;
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INIT_32 : bit_vector;
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INIT_33 : bit_vector;
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INIT_34 : bit_vector;
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INIT_35 : bit_vector;
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INIT_36 : bit_vector;
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INIT_37 : bit_vector;
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INIT_38 : bit_vector;
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INIT_39 : bit_vector;
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INIT_3A : bit_vector;
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INIT_3B : bit_vector;
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INIT_3C : bit_vector;
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INIT_3D : bit_vector;
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INIT_3E : bit_vector;
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INIT_3F : bit_vector);
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PORT ( DO : OUT std_logic_vector( 7 DOWNTO 0 );
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DOP : OUT std_logic_vector( 0 DOWNTO 0 );
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ADDR : IN std_logic_vector( 10 DOWNTO 0 );
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DI : IN std_logic_vector( 7 DOWNTO 0 );
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DIP : IN std_logic_vector( 0 DOWNTO 0 );
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EN : IN std_logic;
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WE : IN std_logic;
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CLK : IN std_logic;
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SSR : IN std_logic );
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END COMPONENT;
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SIGNAL s_n_clock : std_logic;
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SIGNAL s_string_data : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_string_index : std_logic_vector(10 DOWNTO 0 );
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SIGNAL s_push : std_logic;
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SIGNAL s_valid_command : std_logic;
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SIGNAL s_string_select_reg : std_logic_vector( 4 DOWNTO 0 );
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SIGNAL s_string_cnt_reg : std_logic_vector( 5 DOWNTO 0 );
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BEGIN
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--------------------------------------------------------------------------------
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--- Here the outputs are defined ---
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--------------------------------------------------------------------------------
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push_size <= s_string_data(7);
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push_data <= "0"&s_string_data(6 DOWNTO 0);
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push <= s_push;
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--------------------------------------------------------------------------------
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--- Here the control signals are defined ---
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--------------------------------------------------------------------------------
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s_n_clock <= NOT(clock);
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s_push <= '0' WHEN s_string_data = X"00" OR
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fifo_full = '1' ELSE '1';
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s_valid_command <= '1' WHEN start_command = '1' AND
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(command_id = "0011000" OR
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command_id = "0011110") ELSE '0';
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s_string_index <= s_string_select_reg&s_string_cnt_reg;
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--------------------------------------------------------------------------------
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--- Here the processes are defined ---
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--------------------------------------------------------------------------------
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make_command_done : PROCESS( clock , s_push , s_string_data )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_push = '1' AND
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s_string_data = X"0A") THEN command_done <= '1';
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ELSE command_done <= '0';
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END IF;
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END IF;
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END PROCESS make_command_done;
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make_string_select_reg : PROCESS( clock , reset , s_valid_command ,
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command_id , n_usb_power , n_usb_charge ,
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n_bus_power , fpga_configured ,
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fpga_type , flash_empty )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_string_select_reg <= (OTHERS => '0');
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ELSIF (s_valid_command = '1') THEN
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IF (command_id = "0011000") THEN
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s_string_select_reg <= "1"&flash_empty&n_usb_power&n_usb_charge&n_bus_power;
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ELSE
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s_string_select_reg <= "0"&fpga_configured&fpga_type;
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END IF;
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END IF;
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END IF;
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END PROCESS make_string_select_reg;
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make_string_cnt_reg : PROCESS( clock , reset , s_valid_command , s_push )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_string_cnt_reg <= (OTHERS => '1');
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ELSIF (s_valid_command = '1') THEN s_string_cnt_reg <= (OTHERS => '0');
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ELSIF (s_push = '1') THEN
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s_string_cnt_reg <= unsigned(s_string_cnt_reg) + 1;
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END IF;
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END IF;
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END PROCESS make_string_cnt_reg;
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--------------------------------------------------------------------------------
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--- Here the string rom is defined ---
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--------------------------------------------------------------------------------
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string_rom : RAMB16_S9
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GENERIC MAP ( INIT_00 => X"36373647474630303031533343582033206E61747261705320786E696C6958B0",
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INIT_01 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C",
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INIT_02 => X"36373647474630303531533343582033206E61747261705320786E696C6958B0",
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| 195 |
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INIT_03 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C",
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| 196 |
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INIT_04 => X"36373647474630303032533343582033206E61747261705320786E696C6958B0",
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| 197 |
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INIT_05 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C",
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| 198 |
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INIT_06 => X"36373647474630303034533343582033206E61747261705320786E696C6958B0",
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| 199 |
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INIT_07 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C",
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| 200 |
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INIT_08 => X"36373647474630303035533343582033206E61747261705320786E696C6958B0",
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| 201 |
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INIT_09 => X"0000000000000000000000000000000A646572756769666E6F6320746F6E202C",
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| 202 |
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INIT_0A => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5",
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| 203 |
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INIT_0B => X"00000000000000000000000000000000000000000000000000000A6570797420",
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INIT_0C => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5",
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INIT_0D => X"00000000000000000000000000000000000000000000000000000A6570797420",
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INIT_0E => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5",
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| 207 |
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INIT_0F => X"00000000000000000000000000000000000000000000000000000A6570797420",
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| 208 |
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INIT_10 => X"36373647474630303031533343582033206E61747261705320786E696C6958A9",
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| 209 |
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INIT_11 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C",
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| 210 |
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INIT_12 => X"36373647474630303531533343582033206E61747261705320786E696C6958A9",
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| 211 |
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INIT_13 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C",
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| 212 |
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INIT_14 => X"36373647474630303032533343582033206E61747261705320786E696C6958A9",
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| 213 |
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INIT_15 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C",
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| 214 |
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INIT_16 => X"36373647474630303034533343582033206E61747261705320786E696C6958A9",
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| 215 |
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INIT_17 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C",
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| 216 |
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INIT_18 => X"36373647474630303035533343582033206E61747261705320786E696C6958A9",
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| 217 |
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INIT_19 => X"000000000000000000000000000000000000000000000A676E696E6E7572202C",
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| 218 |
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INIT_1A => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5",
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| 219 |
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INIT_1B => X"00000000000000000000000000000000000000000000000000000A6570797420",
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| 220 |
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INIT_1C => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5",
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| 221 |
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INIT_1D => X"00000000000000000000000000000000000000000000000000000A6570797420",
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| 222 |
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INIT_1E => X"41475046206E776F6E6B6E7520726F206465746E756F6D2041475046206F4EA5",
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| 223 |
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INIT_1F => X"00000000000000000000000000000000000000000000000000000A6570797420",
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| 224 |
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INIT_20 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
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| 225 |
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C",
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| 226 |
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INIT_22 => X"7265776F70202C6465696C7070757320425355203A6E69616D344F4B434547B9",
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| 227 |
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INIT_23 => X"0000000000000A64656D6D6172676F7270206873616C46202C53554220676E69",
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| 228 |
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INIT_24 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
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| 229 |
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C",
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| 230 |
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INIT_26 => X"6873616C46202C6465696C7070757320425355203A6E69616D344F4B434547AB",
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| 231 |
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INIT_27 => X"00000000000000000000000000000000000000000A64656D6D6172676F727020",
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| 232 |
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INIT_28 => X"6F70202C6465696C7070757320314F494E4547203A6E69616D344F4B434547BC",
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| 233 |
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INIT_29 => X"0000000A64656D6D6172676F7270206873616C46202C53554220676E69726577",
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| 234 |
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INIT_2A => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
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| 235 |
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000A3F6D656C",
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| 236 |
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INIT_2C => X"6C46202C6465696C7070757320314F494E4547203A6E69616D344F4B434547AE",
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| 237 |
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INIT_2D => X"00000000000000000000000000000000000A64656D6D6172676F727020687361",
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| 238 |
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INIT_2E => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
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| 239 |
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000A3F6D656C",
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| 240 |
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INIT_30 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
|
| 241 |
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C",
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| 242 |
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INIT_32 => X"7265776F70202C6465696C7070757320425355203A6E69616D344F4B434547B4",
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| 243 |
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INIT_33 => X"00000000000000000000000A7974706D65206873616C46202C53554220676E69",
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| 244 |
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INIT_34 => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
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| 245 |
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000A3F6D656C",
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| 246 |
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INIT_36 => X"6873616C46202C6465696C7070757320425355203A6E69616D344F4B434547A6",
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| 247 |
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INIT_37 => X"000000000000000000000000000000000000000000000000000A7974706D6520",
|
| 248 |
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INIT_38 => X"6F70202C6465696C7070757320314F494E4547203A6E69616D344F4B434547B7",
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| 249 |
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INIT_39 => X"00000000000000000A7974706D65206873616C46202C53554220676E69726577",
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| 250 |
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INIT_3A => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
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| 251 |
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000A3F6D656C",
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| 252 |
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INIT_3C => X"6C46202C6465696C7070757320314F494E4547203A6E69616D344F4B434547A9",
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| 253 |
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INIT_3D => X"000000000000000000000000000000000000000000000A7974706D6520687361",
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| 254 |
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INIT_3E => X"626F727020676E697265646C6F73202C65746174532064656E696665646E55A4",
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| 255 |
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000A3F6D656C")
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| 256 |
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PORT MAP ( DO => s_string_data,
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DOP => OPEN,
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| 258 |
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ADDR => s_string_index,
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| 259 |
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DI => X"00",
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| 260 |
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DIP => "0",
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| 261 |
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EN => '1',
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| 262 |
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WE => '0',
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| 263 |
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CLK => s_n_clock,
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| 264 |
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SSR => '0' );
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| 265 |
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| 266 |
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END xilinx;
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