| 1 |
5 |
ktt1 |
--------------------------------------------------------------------------------
|
| 2 |
|
|
-- _ _ __ ____ --
|
| 3 |
|
|
-- / / | | / _| | __| --
|
| 4 |
|
|
-- | |_| | _ _ / / | |_ --
|
| 5 |
|
|
-- | _ | | | | | | | | _| --
|
| 6 |
|
|
-- | | | | | |_| | \ \_ | |__ --
|
| 7 |
|
|
-- |_| |_| \_____| \__| |____| microLab --
|
| 8 |
|
|
-- --
|
| 9 |
|
|
-- Bern University of Applied Sciences (BFH) --
|
| 10 |
|
|
-- Quellgasse 21 --
|
| 11 |
|
|
-- Room HG 4.33 --
|
| 12 |
|
|
-- 2501 Biel/Bienne --
|
| 13 |
|
|
-- Switzerland --
|
| 14 |
|
|
-- --
|
| 15 |
|
|
-- http://www.microlab.ch --
|
| 16 |
|
|
--------------------------------------------------------------------------------
|
| 17 |
|
|
-- GECKO4com
|
| 18 |
|
|
--
|
| 19 |
|
|
-- 2010/2011 Dr. Theo Kluter
|
| 20 |
|
|
--
|
| 21 |
|
|
-- This VHDL code is free code: you can redistribute it and/or modify
|
| 22 |
|
|
-- it under the terms of the GNU General Public License as published by
|
| 23 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
| 24 |
|
|
-- (at your option) any later version.
|
| 25 |
|
|
--
|
| 26 |
|
|
-- This VHDL code is distributed in the hope that it will be useful,
|
| 27 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 28 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 29 |
|
|
-- GNU General Public License for more details.
|
| 30 |
|
|
-- You should have received a copy of the GNU General Public License
|
| 31 |
|
|
-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
|
| 32 |
|
|
--
|
| 33 |
|
|
|
| 34 |
|
|
-- The unisim library is used for simulation of the xilinx specific components
|
| 35 |
|
|
-- For generic usage please use:
|
| 36 |
|
|
-- LIBRARY work;
|
| 37 |
|
|
-- USE work.xilinx_generic.all;
|
| 38 |
|
|
-- And use the xilinx generic package found in the xilinx generic module
|
| 39 |
|
|
LIBRARY unisim;
|
| 40 |
|
|
USE unisim.all;
|
| 41 |
|
|
|
| 42 |
|
|
-- For sending messages to the PC, the FIFO has to contain:
|
| 43 |
|
|
-- 1) The size of the message (in bytes) with the size bit set (can have 1,
|
| 44 |
|
|
-- 2,3, or 4 bytes to indicate size (LSB first))
|
| 45 |
|
|
-- 2) The message itself.
|
| 46 |
|
|
|
| 47 |
|
|
ARCHITECTURE xilinx OF USBTMC IS
|
| 48 |
|
|
|
| 49 |
|
|
TYPE USBTMC_STATE_TYPE IS (WAIT_HEADER,INIT_READ_HEADER,READ_HEADER,
|
| 50 |
|
|
INTERPRET_HEADER,SIGNAL_ERROR,ERROR_WAIT,
|
| 51 |
|
|
INIT_COPY_PAYLOAD,DET_RX_SIZE,CHECK_TX_FIFO,
|
| 52 |
|
|
REQUEST_PAYLOAD_BYTES,CHECK_PAYLOAD_BYTES,
|
| 53 |
|
|
INIT_DUMMY_READ,DO_DUMMY_READ,DUMMY_NOP,
|
| 54 |
|
|
DET_MAX_TRASF_SIZE,CHECK_FIFO_STATUS,
|
| 55 |
|
|
RESET_MESSAGE_SIZE,GET_MESSAGE_SIZE_0,
|
| 56 |
|
|
GET_MESSAGE_SIZE_1,GET_MESSAGE_SIZE_2,
|
| 57 |
|
|
GET_MESSAGE_SIZE_3,MESSAGE_UPDATE,SEND_HEADER,
|
| 58 |
|
|
SEND_PAYLOAD,SEND_PKT_END,CHECK_FULL_STATUS,
|
| 59 |
|
|
TX_NOP);
|
| 60 |
|
|
|
| 61 |
|
|
COMPONENT FD
|
| 62 |
|
|
GENERIC ( INIT : bit );
|
| 63 |
|
|
PORT ( Q : OUT std_logic;
|
| 64 |
|
|
C : IN std_logic;
|
| 65 |
|
|
D : IN std_logic );
|
| 66 |
|
|
END COMPONENT;
|
| 67 |
|
|
|
| 68 |
|
|
COMPONENT FD_1
|
| 69 |
|
|
GENERIC ( INIT : bit );
|
| 70 |
|
|
PORT ( Q : OUT std_logic;
|
| 71 |
|
|
C : IN std_logic;
|
| 72 |
|
|
D : IN std_logic );
|
| 73 |
|
|
END COMPONENT;
|
| 74 |
|
|
|
| 75 |
|
|
COMPONENT FDE
|
| 76 |
|
|
GENERIC ( INIT : bit );
|
| 77 |
|
|
PORT ( Q : OUT std_logic;
|
| 78 |
|
|
CE : IN std_logic;
|
| 79 |
|
|
C : IN std_logic;
|
| 80 |
|
|
D : IN std_logic );
|
| 81 |
|
|
END COMPONENT;
|
| 82 |
|
|
|
| 83 |
|
|
COMPONENT fifo_2kb_ef
|
| 84 |
|
|
PORT ( clock : IN std_logic;
|
| 85 |
|
|
reset : IN std_logic;
|
| 86 |
|
|
high_speed : IN std_logic;
|
| 87 |
|
|
-- push port
|
| 88 |
|
|
push : IN std_logic;
|
| 89 |
|
|
push_data : IN std_logic_vector( 7 DOWNTO 0 );
|
| 90 |
|
|
push_last : IN std_logic;
|
| 91 |
|
|
-- pop port
|
| 92 |
|
|
pop : IN std_logic;
|
| 93 |
|
|
pop_data : OUT std_logic_vector( 7 DOWNTO 0 );
|
| 94 |
|
|
pop_last : OUT std_logic;
|
| 95 |
|
|
-- control port
|
| 96 |
|
|
fifo_full : OUT std_logic;
|
| 97 |
|
|
early_full : OUT std_logic;
|
| 98 |
|
|
fifo_empty : OUT std_logic );
|
| 99 |
|
|
END COMPONENT;
|
| 100 |
|
|
|
| 101 |
|
|
COMPONENT fifo_2kb
|
| 102 |
|
|
PORT ( clock : IN std_logic;
|
| 103 |
|
|
reset : IN std_logic;
|
| 104 |
|
|
-- push port
|
| 105 |
|
|
push : IN std_logic;
|
| 106 |
|
|
push_data : IN std_logic_vector( 7 DOWNTO 0 );
|
| 107 |
|
|
push_size : IN std_logic;
|
| 108 |
|
|
-- pop port
|
| 109 |
|
|
pop : IN std_logic;
|
| 110 |
|
|
pop_data : OUT std_logic_vector( 7 DOWNTO 0 );
|
| 111 |
|
|
pop_size : OUT std_logic;
|
| 112 |
|
|
-- control port
|
| 113 |
|
|
fifo_full : OUT std_logic;
|
| 114 |
|
|
fifo_empty : OUT std_logic );
|
| 115 |
|
|
END COMPONENT;
|
| 116 |
|
|
|
| 117 |
|
|
CONSTANT c_high_speed_packet_size : std_logic_vector( 9 DOWNTO 0 ) := "10"&X"00";
|
| 118 |
|
|
CONSTANT c_full_speed_packet_size : std_logic_vector( 9 DOWNTO 0 ) := "00"&X"40";
|
| 119 |
|
|
|
| 120 |
|
|
SIGNAL s_fifo_clock_reg : std_logic;
|
| 121 |
|
|
SIGNAL s_reset : std_logic;
|
| 122 |
|
|
SIGNAL s_reset_count_reg : std_logic_vector( 2 DOWNTO 0 );
|
| 123 |
|
|
|
| 124 |
|
|
SIGNAL s_EP8_not_empty : std_logic;
|
| 125 |
|
|
SIGNAL s_EP6_not_full : std_logic;
|
| 126 |
|
|
SIGNAL s_endpoint_addr_next : std_logic_vector( 1 DOWNTO 0 );
|
| 127 |
|
|
SIGNAL s_endpoint_n_oe_next : std_logic;
|
| 128 |
|
|
SIGNAL s_endpoint_n_re_next : std_logic;
|
| 129 |
|
|
|
| 130 |
|
|
SIGNAL s_ena_out_ffs : std_logic;
|
| 131 |
|
|
SIGNAL s_ena_in_ffs : std_logic;
|
| 132 |
|
|
SIGNAL s_ena_data_in : std_logic;
|
| 133 |
|
|
SIGNAL s_ready_to_receive_reg : std_logic;
|
| 134 |
|
|
|
| 135 |
|
|
SIGNAL s_usbtmc_state_reg : USBTMC_STATE_TYPE;
|
| 136 |
|
|
SIGNAL s_request_header_byte : std_logic;
|
| 137 |
|
|
SIGNAL s_header_byte_request_pending : std_logic;
|
| 138 |
|
|
SIGNAL s_header_byte_valid : std_logic;
|
| 139 |
|
|
SIGNAL s_header_byte_pending_id : std_logic_vector( 3 DOWNTO 0 );
|
| 140 |
|
|
SIGNAL s_header_byte_valid_id : std_logic_vector( 3 DOWNTO 0 );
|
| 141 |
|
|
SIGNAL s_header_byte_request_id : std_logic_vector( 3 DOWNTO 0 );
|
| 142 |
|
|
SIGNAL s_header_request_done : std_logic;
|
| 143 |
|
|
SIGNAL s_header_error_reg : std_logic;
|
| 144 |
|
|
SIGNAL s_header_error_next : std_logic;
|
| 145 |
|
|
SIGNAL s_Message_ID_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 146 |
|
|
SIGNAL s_known_Message_ID : std_logic;
|
| 147 |
|
|
SIGNAL s_bTag_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 148 |
|
|
SIGNAL s_bTag_inverse : std_logic_vector( 7 DOWNTO 0 );
|
| 149 |
|
|
SIGNAL s_bTag_error : std_logic;
|
| 150 |
|
|
SIGNAL s_data_in_is_zero : std_logic;
|
| 151 |
|
|
SIGNAL s_reserved_3_error : std_logic;
|
| 152 |
|
|
SIGNAL s_transfer_size_reg : std_logic_vector( 31 DOWNTO 0 );
|
| 153 |
|
|
SIGNAL s_zero_payload_size_reg : std_logic;
|
| 154 |
|
|
SIGNAL s_eom_bit_reg : std_logic;
|
| 155 |
|
|
SIGNAL s_rx_message_in_progress_reg : std_logic;
|
| 156 |
|
|
|
| 157 |
|
|
SIGNAL s_data_in : std_logic_vector( 7 DOWNTO 0 );
|
| 158 |
|
|
SIGNAL s_read_fifo_full : std_logic;
|
| 159 |
|
|
SIGNAL s_last_message_byte : std_logic;
|
| 160 |
|
|
|
| 161 |
|
|
SIGNAL s_data_out_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 162 |
|
|
SIGNAL s_ep_n_we_reg : std_logic;
|
| 163 |
|
|
SIGNAL s_ep_pkt_end_reg : std_logic;
|
| 164 |
|
|
SIGNAL s_ep_n_tri_next : std_logic;
|
| 165 |
|
|
SIGNAL s_tx_pop_data : std_logic_vector( 7 DOWNTO 0 );
|
| 166 |
|
|
SIGNAL s_tx_pop_data_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 167 |
|
|
SIGNAL s_tx_pop_size : std_logic;
|
| 168 |
|
|
SIGNAL s_tx_fifo_empty : std_logic;
|
| 169 |
|
|
|
| 170 |
|
|
SIGNAL s_tx_fifo_data_reg : std_logic_vector( 7 DOWNTO 0 );
|
| 171 |
|
|
SIGNAL s_tx_fifo_data_valid_reg : std_logic;
|
| 172 |
|
|
SIGNAL s_tx_fifo_size_bit_reg : std_logic;
|
| 173 |
|
|
SIGNAL s_tx_fifo_pop : std_logic;
|
| 174 |
|
|
SIGNAL s_outstanding_messages_reg : std_logic_vector( 9 DOWNTO 0 );
|
| 175 |
|
|
SIGNAL s_message_in_progress_reg : std_logic;
|
| 176 |
|
|
SIGNAL s_message_size_reg : std_logic_vector( 31 DOWNTO 0 );
|
| 177 |
|
|
SIGNAL s_valid_msg_size_byte : std_logic;
|
| 178 |
|
|
SIGNAL s_valid_payload_byte : std_logic;
|
| 179 |
|
|
SIGNAL s_tx_data_pop : std_logic;
|
| 180 |
|
|
SIGNAL s_can_tx_complete_message : std_logic;
|
| 181 |
|
|
SIGNAL s_can_tx_complete_message_reg : std_logic;
|
| 182 |
|
|
SIGNAL s_real_payload_size_reg : std_logic_vector( 32 DOWNTO 0 );
|
| 183 |
|
|
SIGNAL s_header_insert_count_reg : std_logic_vector( 4 DOWNTO 0 );
|
| 184 |
|
|
SIGNAL s_bytes_send_cnt_reg : std_logic_vector( 9 DOWNTO 0 );
|
| 185 |
|
|
SIGNAL s_require_n_pkt_end : std_logic;
|
| 186 |
|
|
SIGNAL s_send_payload_byte : std_logic;
|
| 187 |
|
|
|
| 188 |
|
|
SIGNAL s_nr_of_bytes_req_cnt_reg : std_logic_vector( 9 DOWNTO 0 );
|
| 189 |
|
|
SIGNAL s_resting_buffer_bytes : std_logic_vector( 9 DOWNTO 0 );
|
| 190 |
|
|
SIGNAL s_rx_payload_cnt_reg : std_logic_vector( 32 DOWNTO 0 );
|
| 191 |
|
|
SIGNAL s_rx_payload_cnt_next : std_logic_vector( 32 DOWNTO 0 );
|
| 192 |
|
|
SIGNAL s_rx_cnt_reg : std_logic_vector( 9 DOWNTO 0 );
|
| 193 |
|
|
SIGNAL s_can_rx_all : std_logic;
|
| 194 |
|
|
SIGNAL s_req_payload_byte : std_logic;
|
| 195 |
|
|
SIGNAL s_rx_pending_pipe_reg : std_logic_vector( 1 DOWNTO 0 );
|
| 196 |
|
|
SIGNAL s_lmb_pipe_reg : std_logic_vector( 1 DOWNTO 0 );
|
| 197 |
|
|
SIGNAL s_rf_last_data_byte : std_logic;
|
| 198 |
|
|
SIGNAL s_dummy_read_cnt_reg : std_logic_vector( 2 DOWNTO 0 );
|
| 199 |
|
|
|
| 200 |
|
|
SIGNAL s_wf_push : std_logic;
|
| 201 |
|
|
SIGNAL s_wf_push_data : std_logic_vector( 7 DOWNTO 0 );
|
| 202 |
|
|
SIGNAL s_wf_push_size : std_logic;
|
| 203 |
|
|
|
| 204 |
|
|
SIGNAL s_fx2_data_nibble : std_logic_vector( 3 DOWNTO 0 );
|
| 205 |
|
|
SIGNAL s_fx2_data_select : std_logic_vector( 3 DOWNTO 0 );
|
| 206 |
|
|
SIGNAL s_ind_pipe_reg : std_logic_vector( 1 DOWNTO 0 );
|
| 207 |
|
|
|
| 208 |
|
|
BEGIN
|
| 209 |
|
|
|
| 210 |
|
|
--------------------------------------------------------------------------------
|
| 211 |
|
|
-- define outputs --
|
| 212 |
|
|
--------------------------------------------------------------------------------
|
| 213 |
|
|
sync_reset_out <= s_reset;
|
| 214 |
|
|
transfer_in_prog <= s_rx_message_in_progress_reg;
|
| 215 |
|
|
rf_last_data_byte<= s_rf_last_data_byte;
|
| 216 |
|
|
wf_fifo_empty <= s_tx_fifo_empty;
|
| 217 |
|
|
indicator_pulse <= s_ind_pipe_reg(0) AND NOT(s_ind_pipe_reg(1));
|
| 218 |
|
|
|
| 219 |
|
|
--------------------------------------------------------------------------------
|
| 220 |
|
|
-- define control signals --
|
| 221 |
|
|
--------------------------------------------------------------------------------
|
| 222 |
|
|
s_endpoint_addr_next <= "11" WHEN
|
| 223 |
|
|
s_usbtmc_state_reg = INIT_READ_HEADER OR
|
| 224 |
|
|
s_usbtmc_state_reg = READ_HEADER OR
|
| 225 |
|
|
s_usbtmc_state_reg = INTERPRET_HEADER OR
|
| 226 |
|
|
s_usbtmc_state_reg = INIT_COPY_PAYLOAD OR
|
| 227 |
|
|
s_usbtmc_state_reg = DET_RX_SIZE OR
|
| 228 |
|
|
s_usbtmc_state_reg = CHECK_TX_FIFO OR
|
| 229 |
|
|
s_usbtmc_state_reg = REQUEST_PAYLOAD_BYTES OR
|
| 230 |
|
|
s_usbtmc_state_reg = CHECK_PAYLOAD_BYTES OR
|
| 231 |
|
|
s_usbtmc_state_reg = INIT_DUMMY_READ OR
|
| 232 |
|
|
s_usbtmc_state_reg = DO_DUMMY_READ OR
|
| 233 |
|
|
s_usbtmc_state_reg = DUMMY_NOP
|
| 234 |
|
|
ELSE
|
| 235 |
|
|
"10" WHEN
|
| 236 |
|
|
s_usbtmc_state_reg = CHECK_FIFO_STATUS OR
|
| 237 |
|
|
s_usbtmc_state_reg = RESET_MESSAGE_SIZE OR
|
| 238 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR
|
| 239 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR
|
| 240 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR
|
| 241 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3 OR
|
| 242 |
|
|
s_usbtmc_state_reg = MESSAGE_UPDATE OR
|
| 243 |
|
|
s_usbtmc_state_reg = SEND_HEADER OR
|
| 244 |
|
|
s_usbtmc_state_reg = SEND_PAYLOAD OR
|
| 245 |
|
|
s_usbtmc_state_reg = SEND_PKT_END OR
|
| 246 |
|
|
s_usbtmc_state_reg = CHECK_FULL_STATUS OR
|
| 247 |
|
|
s_usbtmc_state_reg = TX_NOP
|
| 248 |
|
|
ELSE "00";
|
| 249 |
|
|
s_endpoint_n_oe_next <= '0' WHEN
|
| 250 |
|
|
s_usbtmc_state_reg = INIT_READ_HEADER OR
|
| 251 |
|
|
s_usbtmc_state_reg = READ_HEADER OR
|
| 252 |
|
|
s_usbtmc_state_reg = INTERPRET_HEADER OR
|
| 253 |
|
|
s_usbtmc_state_reg = INIT_COPY_PAYLOAD OR
|
| 254 |
|
|
s_usbtmc_state_reg = DET_RX_SIZE OR
|
| 255 |
|
|
s_usbtmc_state_reg = CHECK_TX_FIFO OR
|
| 256 |
|
|
s_usbtmc_state_reg = REQUEST_PAYLOAD_BYTES OR
|
| 257 |
|
|
s_usbtmc_state_reg = CHECK_PAYLOAD_BYTES OR
|
| 258 |
|
|
s_usbtmc_state_reg = INIT_DUMMY_READ OR
|
| 259 |
|
|
s_usbtmc_state_reg = DO_DUMMY_READ OR
|
| 260 |
|
|
s_usbtmc_state_reg = DUMMY_NOP
|
| 261 |
|
|
ELSE '1';
|
| 262 |
|
|
s_endpoint_n_re_next <= '0' WHEN s_request_header_byte = '1' OR
|
| 263 |
|
|
s_req_payload_byte = '1' OR
|
| 264 |
|
|
s_usbtmc_state_reg = DO_DUMMY_READ ELSE
|
| 265 |
|
|
'1';
|
| 266 |
|
|
s_ena_in_ffs <= NOT(s_fifo_clock_reg);
|
| 267 |
|
|
s_ena_out_ffs <= s_fifo_clock_reg;
|
| 268 |
|
|
s_ena_data_in <= (s_header_byte_request_pending OR
|
| 269 |
|
|
s_rx_pending_pipe_reg(0)) AND s_ena_in_ffs;
|
| 270 |
|
|
s_ep_n_tri_next <= '0' WHEN
|
| 271 |
|
|
s_usbtmc_state_reg = CHECK_FIFO_STATUS OR
|
| 272 |
|
|
s_usbtmc_state_reg = RESET_MESSAGE_SIZE OR
|
| 273 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR
|
| 274 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR
|
| 275 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR
|
| 276 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3 OR
|
| 277 |
|
|
s_usbtmc_state_reg = MESSAGE_UPDATE OR
|
| 278 |
|
|
s_usbtmc_state_reg = SEND_HEADER OR
|
| 279 |
|
|
s_usbtmc_state_reg = SEND_PAYLOAD OR
|
| 280 |
|
|
s_usbtmc_state_reg = SEND_PKT_END OR
|
| 281 |
|
|
s_usbtmc_state_reg = CHECK_FULL_STATUS OR
|
| 282 |
|
|
s_usbtmc_state_reg = TX_NOP
|
| 283 |
|
|
ELSE '1';
|
| 284 |
|
|
|
| 285 |
|
|
--------------------------------------------------------------------------------
|
| 286 |
|
|
-- Here the state machine is defined --
|
| 287 |
|
|
--------------------------------------------------------------------------------
|
| 288 |
|
|
make_state_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg ,
|
| 289 |
|
|
s_EP8_not_empty , s_header_request_done ,
|
| 290 |
|
|
s_header_error_reg , s_header_byte_valid ,
|
| 291 |
|
|
s_message_in_progress_reg ,
|
| 292 |
|
|
s_ready_to_receive_reg , s_outstanding_messages_reg ,
|
| 293 |
|
|
s_tx_fifo_empty , s_tx_pop_size , s_EP6_not_full )
|
| 294 |
|
|
VARIABLE v_next_state : USBTMC_STATE_TYPE;
|
| 295 |
|
|
BEGIN
|
| 296 |
|
|
CASE (s_usbtmc_state_reg) IS
|
| 297 |
|
|
WHEN WAIT_HEADER => IF (s_EP8_not_empty = '1' AND
|
| 298 |
|
|
s_ready_to_receive_reg = '1') THEN
|
| 299 |
|
|
v_next_state := INIT_READ_HEADER;
|
| 300 |
|
|
ELSE
|
| 301 |
|
|
v_next_state := WAIT_HEADER;
|
| 302 |
|
|
END IF;
|
| 303 |
|
|
WHEN INIT_READ_HEADER => v_next_state := READ_HEADER;
|
| 304 |
|
|
WHEN READ_HEADER => IF (s_header_request_done = '1') THEN
|
| 305 |
|
|
v_next_state := INTERPRET_HEADER;
|
| 306 |
|
|
ELSIF (s_EP8_not_empty = '0') THEN
|
| 307 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 308 |
|
|
ELSE
|
| 309 |
|
|
v_next_state := READ_HEADER;
|
| 310 |
|
|
END IF;
|
| 311 |
|
|
WHEN INTERPRET_HEADER => IF (s_header_byte_valid = '1') THEN
|
| 312 |
|
|
v_next_state := INTERPRET_HEADER;
|
| 313 |
|
|
ELSIF (s_header_error_reg = '1') THEN
|
| 314 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 315 |
|
|
ELSE
|
| 316 |
|
|
CASE (s_Message_ID_reg) IS
|
| 317 |
|
|
WHEN X"01" => v_next_state := INIT_COPY_PAYLOAD;
|
| 318 |
|
|
WHEN X"02" => v_next_state := DET_MAX_TRASF_SIZE;
|
| 319 |
|
|
WHEN OTHERS => v_next_state := SIGNAL_ERROR;
|
| 320 |
|
|
END CASE;
|
| 321 |
|
|
END IF;
|
| 322 |
|
|
WHEN INIT_COPY_PAYLOAD => v_next_state := DET_RX_SIZE;
|
| 323 |
|
|
WHEN DET_RX_SIZE => v_next_state := CHECK_TX_FIFO;
|
| 324 |
|
|
WHEN CHECK_TX_FIFO => IF (s_read_fifo_full = '1') THEN
|
| 325 |
|
|
v_next_state := CHECK_TX_FIFO;
|
| 326 |
|
|
ELSE
|
| 327 |
|
|
v_next_state := REQUEST_PAYLOAD_BYTES;
|
| 328 |
|
|
END IF;
|
| 329 |
|
|
WHEN REQUEST_PAYLOAD_BYTES => IF (s_rx_cnt_reg(9) = '1') THEN
|
| 330 |
|
|
v_next_state := CHECK_PAYLOAD_BYTES;
|
| 331 |
|
|
ELSE
|
| 332 |
|
|
v_next_state := REQUEST_PAYLOAD_BYTES;
|
| 333 |
|
|
END IF;
|
| 334 |
|
|
WHEN CHECK_PAYLOAD_BYTES => IF (s_rx_payload_cnt_reg(32) = '1') THEN
|
| 335 |
|
|
IF (s_transfer_size_reg(1 DOWNTO 0) = "00") THEN
|
| 336 |
|
|
v_next_state := DUMMY_NOP;
|
| 337 |
|
|
ELSE
|
| 338 |
|
|
v_next_state := INIT_DUMMY_READ;
|
| 339 |
|
|
END IF;
|
| 340 |
|
|
ELSE
|
| 341 |
|
|
IF (s_EP8_not_empty = '1') THEN
|
| 342 |
|
|
v_next_state := DET_RX_SIZE;
|
| 343 |
|
|
ELSE
|
| 344 |
|
|
v_next_state := CHECK_PAYLOAD_BYTES;
|
| 345 |
|
|
END IF;
|
| 346 |
|
|
END IF;
|
| 347 |
|
|
WHEN INIT_DUMMY_READ => v_next_state := DO_DUMMY_READ;
|
| 348 |
|
|
WHEN DO_DUMMY_READ => IF (s_dummy_read_cnt_reg(2) = '1') THEN
|
| 349 |
|
|
v_next_state := DUMMY_NOP;
|
| 350 |
|
|
ELSE
|
| 351 |
|
|
v_next_state := DO_DUMMY_READ;
|
| 352 |
|
|
END IF;
|
| 353 |
|
|
WHEN DET_MAX_TRASF_SIZE => IF (s_message_in_progress_reg = '1') THEN
|
| 354 |
|
|
v_next_state := CHECK_FIFO_STATUS;
|
| 355 |
|
|
ELSE
|
| 356 |
|
|
v_next_state := RESET_MESSAGE_SIZE;
|
| 357 |
|
|
END IF;
|
| 358 |
|
|
WHEN RESET_MESSAGE_SIZE => IF (s_outstanding_messages_reg(9) = '0') THEN
|
| 359 |
|
|
v_next_state := GET_MESSAGE_SIZE_0;
|
| 360 |
|
|
ELSE
|
| 361 |
|
|
v_next_state := CHECK_FIFO_STATUS;
|
| 362 |
|
|
END IF;
|
| 363 |
|
|
WHEN GET_MESSAGE_SIZE_0 => IF (s_tx_data_pop = '1') THEN
|
| 364 |
|
|
v_next_state := GET_MESSAGE_SIZE_1;
|
| 365 |
|
|
ELSE
|
| 366 |
|
|
v_next_state := GET_MESSAGE_SIZE_0;
|
| 367 |
|
|
END IF;
|
| 368 |
|
|
WHEN GET_MESSAGE_SIZE_1 => IF (s_tx_data_pop = '1' OR
|
| 369 |
|
|
s_valid_payload_byte = '1') THEN
|
| 370 |
|
|
v_next_state := GET_MESSAGE_SIZE_2;
|
| 371 |
|
|
ELSE
|
| 372 |
|
|
v_next_state := GET_MESSAGE_SIZE_1;
|
| 373 |
|
|
END IF;
|
| 374 |
|
|
WHEN GET_MESSAGE_SIZE_2 => IF (s_tx_data_pop = '1' OR
|
| 375 |
|
|
s_valid_payload_byte = '1') THEN
|
| 376 |
|
|
v_next_state := GET_MESSAGE_SIZE_3;
|
| 377 |
|
|
ELSE
|
| 378 |
|
|
v_next_state := GET_MESSAGE_SIZE_2;
|
| 379 |
|
|
END IF;
|
| 380 |
|
|
WHEN GET_MESSAGE_SIZE_3 => IF (s_tx_data_pop = '1' OR
|
| 381 |
|
|
s_valid_payload_byte = '1') THEN
|
| 382 |
|
|
v_next_state := MESSAGE_UPDATE;
|
| 383 |
|
|
ELSE
|
| 384 |
|
|
v_next_state := GET_MESSAGE_SIZE_3;
|
| 385 |
|
|
END IF;
|
| 386 |
|
|
WHEN MESSAGE_UPDATE => v_next_state := CHECK_FIFO_STATUS;
|
| 387 |
|
|
WHEN CHECK_FIFO_STATUS => IF (s_EP6_not_full = '0') THEN
|
| 388 |
|
|
v_next_state := CHECK_FIFO_STATUS;
|
| 389 |
|
|
ELSE
|
| 390 |
|
|
v_next_state := SEND_HEADER;
|
| 391 |
|
|
END IF;
|
| 392 |
|
|
WHEN SEND_HEADER => IF (s_header_insert_count_reg(4) = '1') THEN
|
| 393 |
|
|
v_next_state := SEND_PAYLOAD;
|
| 394 |
|
|
ELSE
|
| 395 |
|
|
v_next_state := SEND_HEADER;
|
| 396 |
|
|
END IF;
|
| 397 |
|
|
WHEN SEND_PAYLOAD => IF (s_require_n_pkt_end = '1' OR
|
| 398 |
|
|
s_real_payload_size_reg(32) = '1') THEN
|
| 399 |
|
|
v_next_state := SEND_PKT_END;
|
| 400 |
|
|
ELSE
|
| 401 |
|
|
v_next_state := SEND_PAYLOAD;
|
| 402 |
|
|
END IF;
|
| 403 |
|
|
WHEN SEND_PKT_END => v_next_state := CHECK_FULL_STATUS;
|
| 404 |
|
|
WHEN CHECK_FULL_STATUS => IF (s_real_payload_size_reg(32) = '1') THEN
|
| 405 |
|
|
v_next_state := TX_NOP;
|
| 406 |
|
|
ELSIF (s_EP6_not_full = '0') THEN
|
| 407 |
|
|
v_next_state := CHECK_FULL_STATUS;
|
| 408 |
|
|
ELSE
|
| 409 |
|
|
v_next_state := SEND_PAYLOAD;
|
| 410 |
|
|
END IF;
|
| 411 |
|
|
WHEN SIGNAL_ERROR => v_next_state := ERROR_WAIT;
|
| 412 |
|
|
WHEN ERROR_WAIT => v_next_state := ERROR_WAIT;
|
| 413 |
|
|
WHEN OTHERS => v_next_state := WAIT_HEADER;
|
| 414 |
|
|
END CASE;
|
| 415 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 416 |
|
|
IF (s_reset = '1') THEN s_usbtmc_state_reg <= WAIT_HEADER;
|
| 417 |
|
|
ELSE s_usbtmc_state_reg <= v_next_state;
|
| 418 |
|
|
END IF;
|
| 419 |
|
|
END IF;
|
| 420 |
|
|
END PROCESS make_state_reg;
|
| 421 |
|
|
|
| 422 |
|
|
make_ready_to_receive_reg : PROCESS( clock_48MHz , s_reset ,
|
| 423 |
|
|
s_usbtmc_state_reg , rf_pop )
|
| 424 |
|
|
BEGIN
|
| 425 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 426 |
|
|
IF (s_reset = '1' OR
|
| 427 |
|
|
(rf_pop = '1' AND
|
| 428 |
|
|
s_rf_last_data_byte = '1')) THEN s_ready_to_receive_reg <= '1';
|
| 429 |
|
|
ELSIF (s_usbtmc_state_reg = INIT_COPY_PAYLOAD) THEN
|
| 430 |
|
|
s_ready_to_receive_reg <= s_rx_message_in_progress_reg;
|
| 431 |
|
|
END IF;
|
| 432 |
|
|
END IF;
|
| 433 |
|
|
END PROCESS make_ready_to_receive_reg;
|
| 434 |
|
|
|
| 435 |
|
|
--------------------------------------------------------------------------------
|
| 436 |
|
|
-- Here the message sending is defined --
|
| 437 |
|
|
--------------------------------------------------------------------------------
|
| 438 |
|
|
s_tx_fifo_pop <= '1' WHEN (s_tx_fifo_data_valid_reg = '0' OR
|
| 439 |
|
|
s_tx_data_pop = '1' OR
|
| 440 |
|
|
s_send_payload_byte = '1') AND
|
| 441 |
|
|
s_tx_fifo_empty = '0' ELSE '0';
|
| 442 |
|
|
s_valid_msg_size_byte <= s_tx_fifo_data_valid_reg AND
|
| 443 |
|
|
s_tx_fifo_size_bit_reg;
|
| 444 |
|
|
s_valid_payload_byte <= s_tx_fifo_data_valid_reg AND
|
| 445 |
|
|
NOT(s_tx_fifo_size_bit_reg);
|
| 446 |
|
|
s_tx_data_pop <= '1' WHEN s_valid_msg_size_byte = '1' AND
|
| 447 |
|
|
(s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR
|
| 448 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR
|
| 449 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR
|
| 450 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3)
|
| 451 |
|
|
ELSE '0';
|
| 452 |
|
|
s_can_tx_complete_message <= '0' WHEN unsigned(s_message_size_reg) >
|
| 453 |
|
|
unsigned(s_transfer_size_reg)
|
| 454 |
|
|
ELSE '1';
|
| 455 |
|
|
s_require_n_pkt_end <= s_bytes_send_cnt_reg(9) WHEN FX2_hi_speed = '1' ELSE
|
| 456 |
|
|
s_bytes_send_cnt_reg(6);
|
| 457 |
|
|
s_send_payload_byte <= '1' WHEN s_usbtmc_state_reg = SEND_PAYLOAD AND
|
| 458 |
|
|
s_require_n_pkt_end = '0' AND
|
| 459 |
|
|
s_real_payload_size_reg(32) = '0' AND
|
| 460 |
|
|
s_valid_payload_byte = '1' ELSE '0';
|
| 461 |
|
|
|
| 462 |
|
|
make_tx_fifo_regs : PROCESS( clock_48MHz , s_reset , s_tx_fifo_pop ,
|
| 463 |
|
|
s_tx_pop_data , s_tx_pop_size , s_tx_data_pop ,
|
| 464 |
|
|
s_send_payload_byte )
|
| 465 |
|
|
BEGIN
|
| 466 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 467 |
|
|
IF (s_tx_fifo_pop = '1') THEN
|
| 468 |
|
|
s_tx_fifo_data_reg <= s_tx_pop_data;
|
| 469 |
|
|
s_tx_fifo_data_valid_reg <= '1';
|
| 470 |
|
|
s_tx_fifo_size_bit_reg <= s_tx_pop_size;
|
| 471 |
|
|
ELSIF (s_reset = '1' OR
|
| 472 |
|
|
s_tx_data_pop = '1' OR
|
| 473 |
|
|
s_send_payload_byte = '1') THEN
|
| 474 |
|
|
s_tx_fifo_data_reg <= (OTHERS => '0');
|
| 475 |
|
|
s_tx_fifo_data_valid_reg <= '0';
|
| 476 |
|
|
s_tx_fifo_size_bit_reg <= '0';
|
| 477 |
|
|
END IF;
|
| 478 |
|
|
END IF;
|
| 479 |
|
|
END PROCESS make_tx_fifo_regs;
|
| 480 |
|
|
|
| 481 |
|
|
make_message_in_progress_reg : PROCESS( clock_48MHz , s_reset )
|
| 482 |
|
|
BEGIN
|
| 483 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 484 |
|
|
IF (s_reset = '1') THEN s_message_in_progress_reg <= '0';
|
| 485 |
|
|
ELSIF (s_usbtmc_state_reg = CHECK_FIFO_STATUS) THEN
|
| 486 |
|
|
s_message_in_progress_reg <= NOT(s_can_tx_complete_message);
|
| 487 |
|
|
END IF;
|
| 488 |
|
|
END IF;
|
| 489 |
|
|
END PROCESS make_message_in_progress_reg;
|
| 490 |
|
|
|
| 491 |
|
|
make_outstanding_messages_reg : PROCESS( clock_48MHz , s_reset )
|
| 492 |
|
|
BEGIN
|
| 493 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 494 |
|
|
IF (s_reset = '1') THEN s_outstanding_messages_reg <= (OTHERS => '1');
|
| 495 |
|
|
ELSIF (s_usbtmc_state_reg = MESSAGE_UPDATE AND
|
| 496 |
|
|
pending_message = '0') THEN
|
| 497 |
|
|
s_outstanding_messages_reg <= unsigned(s_outstanding_messages_reg)-1;
|
| 498 |
|
|
ELSIF (s_usbtmc_state_reg /= MESSAGE_UPDATE AND
|
| 499 |
|
|
pending_message = '1') THEN
|
| 500 |
|
|
s_outstanding_messages_reg <= unsigned(s_outstanding_messages_reg)+1;
|
| 501 |
|
|
END IF;
|
| 502 |
|
|
END IF;
|
| 503 |
|
|
END PROCESS make_outstanding_messages_reg;
|
| 504 |
|
|
|
| 505 |
|
|
make_message_size_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg ,
|
| 506 |
|
|
s_send_payload_byte )
|
| 507 |
|
|
BEGIN
|
| 508 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 509 |
|
|
IF (s_usbtmc_state_reg = RESET_MESSAGE_SIZE OR
|
| 510 |
|
|
s_reset = '1') THEN s_message_size_reg <= (OTHERS => '0');
|
| 511 |
|
|
ELSIF (s_usbtmc_state_reg = GET_MESSAGE_SIZE_0 OR
|
| 512 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_1 OR
|
| 513 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_2 OR
|
| 514 |
|
|
s_usbtmc_state_reg = GET_MESSAGE_SIZE_3) THEN
|
| 515 |
|
|
IF (s_valid_payload_byte = '1') THEN
|
| 516 |
|
|
s_message_size_reg <= X"00"&s_message_size_reg(31 DOWNTO 8);
|
| 517 |
|
|
ELSIF (s_tx_data_pop = '1') THEN
|
| 518 |
|
|
s_message_size_reg <= s_tx_fifo_data_reg&s_message_size_reg(31 DOWNTO 8);
|
| 519 |
|
|
END IF;
|
| 520 |
|
|
ELSIF (s_send_payload_byte = '1') THEN
|
| 521 |
|
|
s_message_size_reg <= unsigned(s_message_size_reg) - 1;
|
| 522 |
|
|
END IF;
|
| 523 |
|
|
END IF;
|
| 524 |
|
|
END PROCESS make_message_size_reg;
|
| 525 |
|
|
|
| 526 |
|
|
make_can_tx_complete_message_reg : PROCESS( clock_48MHz , s_reset ,
|
| 527 |
|
|
s_usbtmc_state_reg ,
|
| 528 |
|
|
s_can_tx_complete_message )
|
| 529 |
|
|
BEGIN
|
| 530 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 531 |
|
|
IF (s_reset = '1') THEN s_can_tx_complete_message_reg <= '0';
|
| 532 |
|
|
ELSIF (s_usbtmc_state_reg = CHECK_FIFO_STATUS) THEN
|
| 533 |
|
|
s_can_tx_complete_message_reg <= s_can_tx_complete_message;
|
| 534 |
|
|
END IF;
|
| 535 |
|
|
END IF;
|
| 536 |
|
|
END PROCESS make_can_tx_complete_message_reg;
|
| 537 |
|
|
|
| 538 |
|
|
make_real_payload_size_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg ,
|
| 539 |
|
|
s_can_tx_complete_message ,
|
| 540 |
|
|
s_transfer_size_reg ,
|
| 541 |
|
|
s_send_payload_byte )
|
| 542 |
|
|
BEGIN
|
| 543 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 544 |
|
|
IF (s_reset = '1') THEN s_real_payload_size_reg <= (OTHERS => '1');
|
| 545 |
|
|
ELSIF (s_usbtmc_state_reg = CHECK_FIFO_STATUS) THEN
|
| 546 |
|
|
IF (s_can_tx_complete_message = '1') THEN
|
| 547 |
|
|
s_real_payload_size_reg <= "0"&s_message_size_reg;
|
| 548 |
|
|
ELSE
|
| 549 |
|
|
s_real_payload_size_reg <= "0"&s_transfer_size_reg;
|
| 550 |
|
|
END IF;
|
| 551 |
|
|
ELSIF ((s_header_insert_count_reg(4) = '1' AND
|
| 552 |
|
|
s_usbtmc_state_reg = SEND_HEADER) OR
|
| 553 |
|
|
s_send_payload_byte = '1') THEN
|
| 554 |
|
|
s_real_payload_size_reg <= unsigned(s_real_payload_size_reg) - 1;
|
| 555 |
|
|
END IF;
|
| 556 |
|
|
END IF;
|
| 557 |
|
|
END PROCESS make_real_payload_size_reg;
|
| 558 |
|
|
|
| 559 |
|
|
make_header_insert_count_reg : PROCESS( clock_48MHz , s_reset ,
|
| 560 |
|
|
s_usbtmc_state_reg )
|
| 561 |
|
|
BEGIN
|
| 562 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 563 |
|
|
IF (s_usbtmc_state_reg = CHECK_FIFO_STATUS OR
|
| 564 |
|
|
s_reset = '1') THEN s_header_insert_count_reg <= "0"&X"A";
|
| 565 |
|
|
ELSIF (s_usbtmc_state_reg = SEND_HEADER) THEN
|
| 566 |
|
|
s_header_insert_count_reg <= unsigned(s_header_insert_count_reg) - 1;
|
| 567 |
|
|
END IF;
|
| 568 |
|
|
END IF;
|
| 569 |
|
|
END PROCESS make_header_insert_count_reg;
|
| 570 |
|
|
|
| 571 |
|
|
make_bytes_send_cnt_reg : PROCESS( clock_48MHz , s_reset ,
|
| 572 |
|
|
s_usbtmc_state_reg , s_send_payload_byte )
|
| 573 |
|
|
BEGIN
|
| 574 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 575 |
|
|
IF (s_usbtmc_state_reg = CHECK_FIFO_STATUS OR
|
| 576 |
|
|
s_usbtmc_state_reg = SEND_PKT_END OR
|
| 577 |
|
|
s_reset = '1') THEN s_bytes_send_cnt_reg <= (OTHERS => '0');
|
| 578 |
|
|
ELSIF (s_usbtmc_state_reg = SEND_HEADER OR
|
| 579 |
|
|
s_send_payload_byte = '1') THEN
|
| 580 |
|
|
s_bytes_send_cnt_reg <= unsigned(s_bytes_send_cnt_reg) + 1;
|
| 581 |
|
|
END IF;
|
| 582 |
|
|
END IF;
|
| 583 |
|
|
END PROCESS make_bytes_send_cnt_reg;
|
| 584 |
|
|
|
| 585 |
|
|
make_fx2_data_reg : PROCESS( clock_48MHz , s_header_insert_count_reg ,
|
| 586 |
|
|
s_Message_ID_reg , s_bTag_reg ,
|
| 587 |
|
|
s_real_payload_size_reg ,
|
| 588 |
|
|
s_can_tx_complete_message_reg ,
|
| 589 |
|
|
s_tx_fifo_data_reg )
|
| 590 |
|
|
BEGIN
|
| 591 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 592 |
|
|
CASE (s_header_insert_count_reg) IS
|
| 593 |
|
|
WHEN "01010" => s_data_out_reg <= s_Message_ID_reg;
|
| 594 |
|
|
WHEN "01001" => s_data_out_reg <= s_bTag_reg;
|
| 595 |
|
|
WHEN "01000" => s_data_out_reg <= NOT(s_bTag_reg);
|
| 596 |
|
|
WHEN "00111" => s_data_out_reg <= X"00";
|
| 597 |
|
|
WHEN "00110" => s_data_out_reg <= s_real_payload_size_reg( 7 DOWNTO 0 );
|
| 598 |
|
|
WHEN "00101" => s_data_out_reg <= s_real_payload_size_reg( 15 DOWNTO 8 );
|
| 599 |
|
|
WHEN "00100" => s_data_out_reg <= s_real_payload_size_reg( 23 DOWNTO 16 );
|
| 600 |
|
|
WHEN "00011" => s_data_out_reg <= s_real_payload_size_reg( 31 DOWNTO 24 );
|
| 601 |
|
|
WHEN "00010" => s_data_out_reg <= "0000000"&s_can_tx_complete_message_reg;
|
| 602 |
|
|
WHEN "00001" |
|
| 603 |
|
|
"00000" |
|
| 604 |
|
|
"11111" => s_data_out_reg <= X"00";
|
| 605 |
|
|
WHEN OTHERS => s_data_out_reg <= s_tx_fifo_data_reg;
|
| 606 |
|
|
END CASE;
|
| 607 |
|
|
END IF;
|
| 608 |
|
|
END PROCESS make_fx2_data_reg;
|
| 609 |
|
|
|
| 610 |
|
|
make_n_we_reg : PROCESS( clock_48MHz , s_usbtmc_state_reg ,
|
| 611 |
|
|
s_send_payload_byte )
|
| 612 |
|
|
BEGIN
|
| 613 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 614 |
|
|
IF (s_usbtmc_state_reg = SEND_HEADER OR
|
| 615 |
|
|
s_send_payload_byte = '1') THEN
|
| 616 |
|
|
s_ep_n_we_reg <= '0';
|
| 617 |
|
|
ELSE
|
| 618 |
|
|
s_ep_n_we_reg <= '1';
|
| 619 |
|
|
END IF;
|
| 620 |
|
|
END IF;
|
| 621 |
|
|
END PROCESS make_n_we_reg;
|
| 622 |
|
|
|
| 623 |
|
|
make_ep_pkt_end_reg : PROCESS( clock_48MHz , s_usbtmc_state_reg )
|
| 624 |
|
|
BEGIN
|
| 625 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 626 |
|
|
IF (s_usbtmc_state_reg = SEND_PKT_END) THEN s_ep_pkt_end_reg <= '0';
|
| 627 |
|
|
ELSE s_ep_pkt_end_reg <= '1';
|
| 628 |
|
|
END IF;
|
| 629 |
|
|
END IF;
|
| 630 |
|
|
END PROCESS make_ep_pkt_end_reg;
|
| 631 |
|
|
|
| 632 |
|
|
make_pip_regs : PROCESS( clock_48MHz )
|
| 633 |
|
|
BEGIN
|
| 634 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 635 |
|
|
s_wf_push <= wf_push;
|
| 636 |
|
|
s_wf_push_data <= wf_push_data;
|
| 637 |
|
|
s_wf_push_size <= wf_push_size_bit;
|
| 638 |
|
|
END IF;
|
| 639 |
|
|
END PROCESS make_pip_regs;
|
| 640 |
|
|
|
| 641 |
|
|
tx_fifo : fifo_2kb
|
| 642 |
|
|
PORT MAP ( clock => clock_48MHz,
|
| 643 |
|
|
reset => s_reset,
|
| 644 |
|
|
-- push port
|
| 645 |
|
|
push => s_wf_push,
|
| 646 |
|
|
push_data => s_wf_push_data,
|
| 647 |
|
|
push_size => s_wf_push_size,
|
| 648 |
|
|
-- pop port
|
| 649 |
|
|
pop => s_tx_fifo_pop,
|
| 650 |
|
|
pop_data => s_tx_pop_data,
|
| 651 |
|
|
pop_size => s_tx_pop_size,
|
| 652 |
|
|
-- control port
|
| 653 |
|
|
fifo_full => wf_fifo_full,
|
| 654 |
|
|
fifo_empty => s_tx_fifo_empty );
|
| 655 |
|
|
|
| 656 |
|
|
--------------------------------------------------------------------------------
|
| 657 |
|
|
-- Here the payload copying is defined --
|
| 658 |
|
|
--------------------------------------------------------------------------------
|
| 659 |
|
|
|
| 660 |
|
|
s_resting_buffer_bytes <= unsigned(c_high_speed_packet_size) -
|
| 661 |
|
|
unsigned(s_nr_of_bytes_req_cnt_reg)
|
| 662 |
|
|
WHEN FX2_hi_speed = '1' ELSE
|
| 663 |
|
|
unsigned(c_full_speed_packet_size) -
|
| 664 |
|
|
unsigned(s_nr_of_bytes_req_cnt_reg);
|
| 665 |
|
|
s_can_rx_all <= '0' WHEN s_rx_payload_cnt_reg(31 DOWNTO 10) /=
|
| 666 |
|
|
"0000000000000000000000" OR
|
| 667 |
|
|
unsigned(s_resting_buffer_bytes) <
|
| 668 |
|
|
unsigned(s_rx_payload_cnt_reg(9 DOWNTO 0))
|
| 669 |
|
|
ELSE '1';
|
| 670 |
|
|
s_req_payload_byte <= '1' WHEN s_usbtmc_state_reg = REQUEST_PAYLOAD_BYTES AND
|
| 671 |
|
|
s_rx_cnt_reg(9) = '0' ELSE '0';
|
| 672 |
|
|
s_rx_payload_cnt_next <= unsigned(s_rx_payload_cnt_reg) - 1;
|
| 673 |
|
|
s_last_message_byte <= s_rx_payload_cnt_next(32) AND
|
| 674 |
|
|
s_req_payload_byte AND
|
| 675 |
|
|
s_eom_bit_reg;
|
| 676 |
|
|
|
| 677 |
|
|
make_nr_of_bytes_req_cnt_reg : PROCESS( clock_48MHz , s_usbtmc_state_reg )
|
| 678 |
|
|
BEGIN
|
| 679 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 680 |
|
|
IF (s_usbtmc_state_reg = WAIT_HEADER OR
|
| 681 |
|
|
s_usbtmc_state_reg = CHECK_PAYLOAD_BYTES) THEN
|
| 682 |
|
|
s_nr_of_bytes_req_cnt_reg <= (OTHERS => '0');
|
| 683 |
|
|
ELSIF (s_request_header_byte = '1' OR
|
| 684 |
|
|
s_req_payload_byte = '1') THEN
|
| 685 |
|
|
s_nr_of_bytes_req_cnt_reg <= unsigned(s_nr_of_bytes_req_cnt_reg) + 1;
|
| 686 |
|
|
END IF;
|
| 687 |
|
|
END IF;
|
| 688 |
|
|
END PROCESS make_nr_of_bytes_req_cnt_reg;
|
| 689 |
|
|
|
| 690 |
|
|
make_rx_payload_cnt_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg,
|
| 691 |
|
|
s_transfer_size_reg )
|
| 692 |
|
|
BEGIN
|
| 693 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 694 |
|
|
IF (s_reset = '1') THEN s_rx_payload_cnt_reg <= (OTHERS => '0');
|
| 695 |
|
|
ELSIF (s_usbtmc_state_reg = INIT_COPY_PAYLOAD) THEN
|
| 696 |
|
|
s_rx_payload_cnt_reg <= unsigned("0"&s_transfer_size_reg) - 1;
|
| 697 |
|
|
ELSIF (s_req_payload_byte = '1') THEN
|
| 698 |
|
|
s_rx_payload_cnt_reg <= s_rx_payload_cnt_next;
|
| 699 |
|
|
END IF;
|
| 700 |
|
|
END IF;
|
| 701 |
|
|
END PROCESS make_rx_payload_cnt_reg;
|
| 702 |
|
|
|
| 703 |
|
|
make_rx_cnt_reg : PROCESS( clock_48MHz , s_reset , s_usbtmc_state_reg )
|
| 704 |
|
|
BEGIN
|
| 705 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 706 |
|
|
IF (s_reset = '1') THEN s_rx_cnt_reg <= (OTHERS => '0');
|
| 707 |
|
|
ELSIF (s_usbtmc_state_reg = DET_RX_SIZE) THEN
|
| 708 |
|
|
IF (s_can_rx_all = '1') THEN
|
| 709 |
|
|
s_rx_cnt_reg <= s_rx_payload_cnt_reg(9 DOWNTO 0);
|
| 710 |
|
|
ELSE
|
| 711 |
|
|
s_rx_cnt_reg <= unsigned(s_resting_buffer_bytes)-1;
|
| 712 |
|
|
END IF;
|
| 713 |
|
|
ELSIF (s_req_payload_byte = '1') THEN
|
| 714 |
|
|
s_rx_cnt_reg <= unsigned(s_rx_cnt_reg) - 1;
|
| 715 |
|
|
END IF;
|
| 716 |
|
|
END IF;
|
| 717 |
|
|
END PROCESS make_rx_cnt_reg;
|
| 718 |
|
|
|
| 719 |
|
|
make_rx_pending_regs : PROCESS( clock_96MHz , s_reset )
|
| 720 |
|
|
BEGIN
|
| 721 |
|
|
IF (clock_96MHz'event AND (clock_96MHz = '1')) THEN
|
| 722 |
|
|
IF (s_reset = '1') THEN s_rx_pending_pipe_reg <= "00";
|
| 723 |
|
|
s_lmb_pipe_reg <= "00";
|
| 724 |
|
|
ELSIF (s_ena_out_ffs = '1') THEN
|
| 725 |
|
|
s_rx_pending_pipe_reg(0) <= s_req_payload_byte;
|
| 726 |
|
|
s_lmb_pipe_reg(0) <= s_last_message_byte;
|
| 727 |
|
|
ELSIF (s_ena_in_ffs = '1') THEN
|
| 728 |
|
|
s_rx_pending_pipe_reg(1) <= s_rx_pending_pipe_reg(0);
|
| 729 |
|
|
s_lmb_pipe_reg(1) <= s_lmb_pipe_reg(0);
|
| 730 |
|
|
END IF;
|
| 731 |
|
|
END IF;
|
| 732 |
|
|
END PROCESS make_rx_pending_regs;
|
| 733 |
|
|
|
| 734 |
|
|
make_dummy_read_cnt_reg : PROCESS( clock_48MHz , s_reset ,
|
| 735 |
|
|
s_usbtmc_state_reg )
|
| 736 |
|
|
BEGIN
|
| 737 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 738 |
|
|
IF (s_reset = '1') THEN s_dummy_read_cnt_reg <= "000";
|
| 739 |
|
|
ELSIF (s_usbtmc_state_reg = INIT_DUMMY_READ) THEN
|
| 740 |
|
|
CASE (s_transfer_size_reg( 1 DOWNTO 0 )) IS
|
| 741 |
|
|
WHEN "01" => s_dummy_read_cnt_reg <= "001";
|
| 742 |
|
|
WHEN "10" => s_dummy_read_cnt_reg <= "000";
|
| 743 |
|
|
WHEN OTHERS => s_dummy_read_cnt_reg <= "111";
|
| 744 |
|
|
END CASE;
|
| 745 |
|
|
ELSIF (s_usbtmc_state_reg = DO_DUMMY_READ) THEN
|
| 746 |
|
|
s_dummy_read_cnt_reg <= unsigned(s_dummy_read_cnt_reg) - 1;
|
| 747 |
|
|
END IF;
|
| 748 |
|
|
END IF;
|
| 749 |
|
|
END PROCESS make_dummy_read_cnt_reg;
|
| 750 |
|
|
|
| 751 |
|
|
read_fifo : fifo_2kb_ef
|
| 752 |
|
|
PORT MAP ( clock => clock_48MHz,
|
| 753 |
|
|
reset => s_reset,
|
| 754 |
|
|
high_speed => FX2_hi_speed,
|
| 755 |
|
|
-- push port
|
| 756 |
|
|
push => s_rx_pending_pipe_reg(1),
|
| 757 |
|
|
push_data => s_data_in,
|
| 758 |
|
|
push_last => s_lmb_pipe_reg(1),
|
| 759 |
|
|
-- pop port
|
| 760 |
|
|
pop => rf_pop,
|
| 761 |
|
|
pop_data => rf_pop_data,
|
| 762 |
|
|
pop_last => s_rf_last_data_byte,
|
| 763 |
|
|
-- control port
|
| 764 |
|
|
fifo_full => OPEN,
|
| 765 |
|
|
early_full => s_read_fifo_full,
|
| 766 |
|
|
fifo_empty => rf_fifo_empty );
|
| 767 |
|
|
|
| 768 |
|
|
--------------------------------------------------------------------------------
|
| 769 |
|
|
-- Here the header read is defined --
|
| 770 |
|
|
--------------------------------------------------------------------------------
|
| 771 |
|
|
s_header_request_done <= '1' WHEN s_header_byte_request_id = X"B" ELSE '0';
|
| 772 |
|
|
s_request_header_byte <= '1' WHEN s_usbtmc_state_reg = READ_HEADER ELSE '0';
|
| 773 |
|
|
s_header_error_next <= '0' WHEN s_usbtmc_state_reg = INIT_READ_HEADER OR
|
| 774 |
|
|
s_reset = '1'
|
| 775 |
|
|
ELSE
|
| 776 |
|
|
'1' WHEN s_known_Message_ID = '0' OR
|
| 777 |
|
|
s_bTag_error = '1' OR
|
| 778 |
|
|
s_reserved_3_error = '1' OR
|
| 779 |
|
|
(s_zero_payload_size_reg = '1' AND
|
| 780 |
|
|
s_header_byte_valid_id = X"8" AND
|
| 781 |
|
|
s_header_byte_valid = '1')
|
| 782 |
|
|
ELSE s_header_error_reg;
|
| 783 |
|
|
s_known_Message_ID <= '1' WHEN s_Message_ID_reg = X"01" OR
|
| 784 |
|
|
s_Message_ID_reg = X"02" OR
|
| 785 |
|
|
s_Message_ID_reg = X"7E" OR
|
| 786 |
|
|
s_Message_ID_reg = X"7F" ELSE '0';
|
| 787 |
|
|
s_bTag_inverse <= NOT(s_bTag_reg);
|
| 788 |
|
|
s_bTag_error <= '1' WHEN s_bTag_inverse /= s_data_in AND
|
| 789 |
|
|
s_header_byte_valid = '1' AND
|
| 790 |
|
|
s_header_byte_valid_id = X"2" ELSE '0';
|
| 791 |
|
|
s_data_in_is_zero <= '1' WHEN s_data_in = X"00" ELSE '0';
|
| 792 |
|
|
s_reserved_3_error <= '1' WHEN s_data_in_is_zero = '0' AND
|
| 793 |
|
|
s_header_byte_valid = '1' AND
|
| 794 |
|
|
(s_header_byte_valid_id = X"3" OR
|
| 795 |
|
|
s_header_byte_valid_id = X"A" OR
|
| 796 |
|
|
s_header_byte_valid_id = X"B") ELSE '0';
|
| 797 |
|
|
|
| 798 |
|
|
|
| 799 |
|
|
make_header_byte_request_id : PROCESS( s_reset , clock_48MHz ,
|
| 800 |
|
|
s_usbtmc_state_reg )
|
| 801 |
|
|
BEGIN
|
| 802 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 803 |
|
|
IF (s_usbtmc_state_reg = INIT_READ_HEADER OR
|
| 804 |
|
|
s_reset = '1') THEN
|
| 805 |
|
|
s_header_byte_request_id <= X"0";
|
| 806 |
|
|
ELSIF (s_usbtmc_state_reg = READ_HEADER) THEN
|
| 807 |
|
|
s_header_byte_request_id <= unsigned(s_header_byte_request_id)+1;
|
| 808 |
|
|
END IF;
|
| 809 |
|
|
END IF;
|
| 810 |
|
|
END PROCESS make_header_byte_request_id;
|
| 811 |
|
|
|
| 812 |
|
|
make_pending_regs : PROCESS( s_reset , clock_96MHz , s_ena_out_ffs ,
|
| 813 |
|
|
s_request_header_byte , s_header_byte_request_id )
|
| 814 |
|
|
BEGIN
|
| 815 |
|
|
IF (clock_96MHz'event AND (clock_96MHz = '1')) THEN
|
| 816 |
|
|
IF (s_reset = '1') THEN s_header_byte_request_pending <= '0';
|
| 817 |
|
|
s_header_byte_pending_id <= X"0";
|
| 818 |
|
|
ELSIF (s_ena_out_ffs = '1') THEN
|
| 819 |
|
|
s_header_byte_request_pending <= s_request_header_byte;
|
| 820 |
|
|
s_header_byte_pending_id <= s_header_byte_request_id;
|
| 821 |
|
|
END IF;
|
| 822 |
|
|
END IF;
|
| 823 |
|
|
END PROCESS make_pending_regs;
|
| 824 |
|
|
|
| 825 |
|
|
make_valid_regs : PROCESS( s_reset , clock_96MHz , s_ena_in_ffs ,
|
| 826 |
|
|
s_header_byte_request_pending ,
|
| 827 |
|
|
s_header_byte_pending_id )
|
| 828 |
|
|
BEGIN
|
| 829 |
|
|
IF (clock_96MHz'event AND (clock_96MHz = '1')) THEN
|
| 830 |
|
|
IF (s_reset = '1') THEN s_header_byte_valid <= '0';
|
| 831 |
|
|
s_header_byte_valid_id <= X"0";
|
| 832 |
|
|
ELSIF (s_ena_in_ffs = '1') THEN
|
| 833 |
|
|
s_header_byte_valid <= s_header_byte_request_pending;
|
| 834 |
|
|
s_header_byte_valid_id <= s_header_byte_pending_id;
|
| 835 |
|
|
END IF;
|
| 836 |
|
|
END IF;
|
| 837 |
|
|
END PROCESS make_valid_regs;
|
| 838 |
|
|
|
| 839 |
|
|
make_header_error_reg : PROCESS( clock_48MHz , s_header_error_next )
|
| 840 |
|
|
BEGIN
|
| 841 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 842 |
|
|
s_header_error_reg <= s_header_error_next;
|
| 843 |
|
|
END IF;
|
| 844 |
|
|
END PROCESS make_header_error_reg;
|
| 845 |
|
|
|
| 846 |
|
|
make_message_id_reg : PROCESS( clock_48MHz , s_reset , s_data_in ,
|
| 847 |
|
|
s_header_byte_valid , s_header_byte_valid_id )
|
| 848 |
|
|
BEGIN
|
| 849 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 850 |
|
|
IF (s_reset = '1') THEN s_Message_ID_reg <= X"01";
|
| 851 |
|
|
ELSIF (s_header_byte_valid = '1' AND
|
| 852 |
|
|
s_header_byte_valid_id = X"0") THEN
|
| 853 |
|
|
s_Message_ID_reg <= s_data_in;
|
| 854 |
|
|
END IF;
|
| 855 |
|
|
END IF;
|
| 856 |
|
|
END PROCESS make_message_id_reg;
|
| 857 |
|
|
|
| 858 |
|
|
make_btag_reg : PROCESS( clock_48MHz , s_reset , s_data_in ,
|
| 859 |
|
|
s_header_byte_valid , s_header_byte_valid_id )
|
| 860 |
|
|
BEGIN
|
| 861 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 862 |
|
|
IF (s_reset = '1') THEN s_bTag_reg <= X"00";
|
| 863 |
|
|
ELSIF (s_header_byte_valid = '1' AND
|
| 864 |
|
|
s_header_byte_valid_id = X"1") THEN
|
| 865 |
|
|
s_bTag_reg <= s_data_in;
|
| 866 |
|
|
END IF;
|
| 867 |
|
|
END IF;
|
| 868 |
|
|
END PROCESS make_btag_reg;
|
| 869 |
|
|
|
| 870 |
|
|
make_transfer_size_reg : PROCESS( clock_48MHz , s_reset , s_data_in ,
|
| 871 |
|
|
s_header_byte_valid , s_header_byte_valid_id )
|
| 872 |
|
|
BEGIN
|
| 873 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 874 |
|
|
IF (s_reset = '1') THEN s_transfer_size_reg <= (OTHERS => '0');
|
| 875 |
|
|
ELSIF (s_header_byte_valid = '1') THEN
|
| 876 |
|
|
CASE (s_header_byte_valid_id) IS
|
| 877 |
|
|
WHEN X"4" => s_transfer_size_reg( 7 DOWNTO 0 ) <= s_data_in;
|
| 878 |
|
|
WHEN X"5" => s_transfer_size_reg( 15 DOWNTO 8 ) <= s_data_in;
|
| 879 |
|
|
WHEN X"6" => s_transfer_size_reg( 23 DOWNTO 16 ) <= s_data_in;
|
| 880 |
|
|
WHEN X"7" => s_transfer_size_reg( 31 DOWNTO 24 ) <= s_data_in;
|
| 881 |
|
|
WHEN OTHERS => NULL;
|
| 882 |
|
|
END CASE;
|
| 883 |
|
|
END IF;
|
| 884 |
|
|
END IF;
|
| 885 |
|
|
END PROCESS make_transfer_size_reg;
|
| 886 |
|
|
|
| 887 |
|
|
make_zero_payload_size_reg : PROCESS( clock_48MHz , s_reset ,
|
| 888 |
|
|
s_data_in_is_zero , s_header_byte_valid ,
|
| 889 |
|
|
s_header_byte_valid_id ,
|
| 890 |
|
|
s_usbtmc_state_reg )
|
| 891 |
|
|
BEGIN
|
| 892 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 893 |
|
|
IF (s_usbtmc_state_reg = INIT_READ_HEADER OR
|
| 894 |
|
|
s_reset = '1') THEN s_zero_payload_size_reg <= '1';
|
| 895 |
|
|
ELSIF ((s_header_byte_valid_id = X"4" OR
|
| 896 |
|
|
s_header_byte_valid_id = X"5" OR
|
| 897 |
|
|
s_header_byte_valid_id = X"6" OR
|
| 898 |
|
|
s_header_byte_valid_id = X"7") AND
|
| 899 |
|
|
s_data_in_is_zero = '0') THEN s_zero_payload_size_reg <= '0';
|
| 900 |
|
|
END IF;
|
| 901 |
|
|
END IF;
|
| 902 |
|
|
END PROCESS make_zero_payload_size_reg;
|
| 903 |
|
|
|
| 904 |
|
|
make_eom_bit_reg : PROCESS( clock_48MHz , s_reset , s_header_byte_valid ,
|
| 905 |
|
|
s_header_byte_valid_id , s_data_in )
|
| 906 |
|
|
BEGIN
|
| 907 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 908 |
|
|
IF (s_reset = '1') THEN s_eom_bit_reg <= '1';
|
| 909 |
|
|
s_rx_message_in_progress_reg <= '0';
|
| 910 |
|
|
ELSIF (s_header_byte_valid = '1' AND
|
| 911 |
|
|
s_header_byte_valid_id = X"8") THEN
|
| 912 |
|
|
IF (s_Message_ID_reg = X"01") THEN
|
| 913 |
|
|
s_rx_message_in_progress_reg <= NOT(s_data_in(0));
|
| 914 |
|
|
s_eom_bit_reg <= s_data_in(0);
|
| 915 |
|
|
ELSE
|
| 916 |
|
|
s_rx_message_in_progress_reg <= '0';
|
| 917 |
|
|
s_eom_bit_reg <= '1';
|
| 918 |
|
|
END IF;
|
| 919 |
|
|
END IF;
|
| 920 |
|
|
END IF;
|
| 921 |
|
|
END PROCESS make_eom_bit_reg;
|
| 922 |
|
|
|
| 923 |
|
|
--------------------------------------------------------------------------------
|
| 924 |
|
|
-- Define the synchronized clock signal for this module --
|
| 925 |
|
|
--------------------------------------------------------------------------------
|
| 926 |
|
|
s_reset <= s_reset_count_reg(2);
|
| 927 |
|
|
|
| 928 |
|
|
make_reset_count_reg : PROCESS( cpu_reset , clock_48MHz , FX2_n_ready ,
|
| 929 |
|
|
s_reset_count_reg , s_reset )
|
| 930 |
|
|
BEGIN
|
| 931 |
|
|
IF (cpu_reset = '1' OR
|
| 932 |
|
|
FX2_n_ready = '1') THEN s_reset_count_reg <= (OTHERS => '1');
|
| 933 |
|
|
ELSIF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 934 |
|
|
IF (s_reset = '1') THEN
|
| 935 |
|
|
s_reset_count_reg <= unsigned(s_reset_count_reg) - 1;
|
| 936 |
|
|
END IF;
|
| 937 |
|
|
END IF;
|
| 938 |
|
|
END PROCESS make_reset_count_reg;
|
| 939 |
|
|
|
| 940 |
|
|
--------------------------------------------------------------------------------
|
| 941 |
|
|
-- Define the clock of the FX2 FIFOs --
|
| 942 |
|
|
--------------------------------------------------------------------------------
|
| 943 |
|
|
make_fifo_clock_reg : PROCESS( clock_96MHz , cpu_reset , s_fifo_clock_reg )
|
| 944 |
|
|
BEGIN
|
| 945 |
|
|
IF (cpu_reset = '1') THEN s_fifo_clock_reg <= '1';
|
| 946 |
|
|
ELSIF (clock_96MHz'event AND (clock_96MHz = '1')) THEN
|
| 947 |
|
|
s_fifo_clock_reg <= NOT(s_fifo_clock_reg);
|
| 948 |
|
|
END IF;
|
| 949 |
|
|
END PROCESS make_fifo_clock_reg;
|
| 950 |
|
|
|
| 951 |
|
|
--------------------------------------------------------------------------------
|
| 952 |
|
|
--- Define the fx2 data reporting ---
|
| 953 |
|
|
--------------------------------------------------------------------------------
|
| 954 |
|
|
make_fx2_data_nibble : PROCESS( clock_48MHz , s_fx2_data_select ,
|
| 955 |
|
|
status_nibble , s_bTag_reg )
|
| 956 |
|
|
BEGIN
|
| 957 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 958 |
|
|
CASE (s_fx2_data_select) IS
|
| 959 |
|
|
WHEN X"C" => s_fx2_data_nibble <= s_bTag_reg( 3 DOWNTO 0 );
|
| 960 |
|
|
WHEN X"D" => s_fx2_data_nibble <= s_bTag_reg( 7 DOWNTO 4 );
|
| 961 |
|
|
WHEN X"F" => s_fx2_data_nibble <= status_nibble;
|
| 962 |
|
|
WHEN OTHERS => s_fx2_data_nibble <= X"F";
|
| 963 |
|
|
END CASE;
|
| 964 |
|
|
END IF;
|
| 965 |
|
|
END PROCESS make_fx2_data_nibble;
|
| 966 |
|
|
|
| 967 |
|
|
make_ind_pipe_reg : PROCESS( clock_48MHz , s_reset , s_fx2_data_select )
|
| 968 |
|
|
BEGIN
|
| 969 |
|
|
IF (clock_48MHz'event AND (clock_48MHz = '1')) THEN
|
| 970 |
|
|
IF (s_reset = '1') THEN s_ind_pipe_reg <= "00";
|
| 971 |
|
|
ELSE
|
| 972 |
|
|
s_ind_pipe_reg(1) <= s_ind_pipe_reg(0);
|
| 973 |
|
|
IF (s_fx2_data_select = X"E") THEN
|
| 974 |
|
|
s_ind_pipe_reg(0) <= '1';
|
| 975 |
|
|
ELSE
|
| 976 |
|
|
s_ind_pipe_reg(0) <= '0';
|
| 977 |
|
|
END IF;
|
| 978 |
|
|
END IF;
|
| 979 |
|
|
END IF;
|
| 980 |
|
|
END PROCESS make_ind_pipe_reg;
|
| 981 |
|
|
|
| 982 |
|
|
--------------------------------------------------------------------------------
|
| 983 |
|
|
-- Define the IOB flipflops and tri-state buffers used --
|
| 984 |
|
|
--------------------------------------------------------------------------------
|
| 985 |
|
|
gen_data_nibble : FOR n IN 3 DOWNTO 0 GENERATE
|
| 986 |
|
|
in_ff : FD
|
| 987 |
|
|
GENERIC MAP ( INIT => '1' )
|
| 988 |
|
|
PORT MAP ( Q => s_fx2_data_select(n),
|
| 989 |
|
|
C => clock_48MHz,
|
| 990 |
|
|
D => data_select(n) );
|
| 991 |
|
|
out_ff : FD
|
| 992 |
|
|
GENERIC MAP ( INIT => '1' )
|
| 993 |
|
|
PORT MAP ( Q => data_nibble(n),
|
| 994 |
|
|
C => clock_48MHz,
|
| 995 |
|
|
D => s_fx2_data_nibble(n) );
|
| 996 |
|
|
END GENERATE gen_data_nibble;
|
| 997 |
|
|
|
| 998 |
|
|
IFCLK_FF : FD_1
|
| 999 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1000 |
|
|
PORT MAP ( Q => EP_IFCLOCK,
|
| 1001 |
|
|
C => clock_96MHz,
|
| 1002 |
|
|
D => s_fifo_clock_reg );
|
| 1003 |
|
|
EP8_flag_FF : FDE
|
| 1004 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1005 |
|
|
PORT MAP ( Q => s_EP8_not_empty,
|
| 1006 |
|
|
CE => s_ena_in_ffs,
|
| 1007 |
|
|
C => clock_96MHz,
|
| 1008 |
|
|
D => EP8_n_empty );
|
| 1009 |
|
|
EP6_flag_ff : FDE
|
| 1010 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1011 |
|
|
PORT MAP( Q => s_EP6_not_full,
|
| 1012 |
|
|
CE => s_ena_in_ffs,
|
| 1013 |
|
|
C => clock_96MHz,
|
| 1014 |
|
|
D => EP6_n_full );
|
| 1015 |
|
|
EP_n_WE_FF : FDE
|
| 1016 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1017 |
|
|
PORT MAP ( Q => EP_n_WE,
|
| 1018 |
|
|
CE => s_ena_out_ffs,
|
| 1019 |
|
|
C => clock_96MHz,
|
| 1020 |
|
|
D => s_ep_n_we_reg );
|
| 1021 |
|
|
EP_n_PKTEND_FF : FDE
|
| 1022 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1023 |
|
|
PORT MAP ( Q => EP_n_PKTEND,
|
| 1024 |
|
|
CE => s_ena_out_ffs,
|
| 1025 |
|
|
C => clock_96MHz,
|
| 1026 |
|
|
D => s_ep_pkt_end_reg );
|
| 1027 |
|
|
make_addr_ff : FOR n IN 1 DOWNTO 0 GENERATE
|
| 1028 |
|
|
one_ff : FDE
|
| 1029 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1030 |
|
|
PORT MAP ( Q => EP_address(n),
|
| 1031 |
|
|
CE => s_ena_out_ffs,
|
| 1032 |
|
|
C => clock_96MHz,
|
| 1033 |
|
|
D => s_endpoint_addr_next(n) );
|
| 1034 |
|
|
END GENERATE make_addr_ff;
|
| 1035 |
|
|
n_oe_ff : FDE
|
| 1036 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1037 |
|
|
PORT MAP ( Q => EP_n_OE,
|
| 1038 |
|
|
CE => s_ena_out_ffs,
|
| 1039 |
|
|
C => clock_96MHz,
|
| 1040 |
|
|
D => s_endpoint_n_oe_next );
|
| 1041 |
|
|
n_re_ff : FDE
|
| 1042 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1043 |
|
|
PORT MAP ( Q => EP_n_RE,
|
| 1044 |
|
|
CE => s_ena_out_ffs,
|
| 1045 |
|
|
C => clock_96MHz,
|
| 1046 |
|
|
D => s_endpoint_n_re_next );
|
| 1047 |
|
|
make_data_in_ff : FOR n IN 7 DOWNTO 0 GENERATE
|
| 1048 |
|
|
one_ff : FDE
|
| 1049 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1050 |
|
|
PORT MAP ( Q => s_data_in(n),
|
| 1051 |
|
|
CE => s_ena_data_in,
|
| 1052 |
|
|
C => clock_96MHz,
|
| 1053 |
|
|
D => EP_data_in(n) );
|
| 1054 |
|
|
out_ff : FDE
|
| 1055 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1056 |
|
|
PORT MAP ( Q => EP_data_out(n),
|
| 1057 |
|
|
CE => s_ena_out_ffs,
|
| 1058 |
|
|
C => clock_96MHz,
|
| 1059 |
|
|
D => s_data_out_reg(n) );
|
| 1060 |
|
|
tri_ff : FDE
|
| 1061 |
|
|
GENERIC MAP ( INIT => '0' )
|
| 1062 |
|
|
PORT MAP( Q => EP_n_tri_out(n),
|
| 1063 |
|
|
CE => s_ena_out_ffs,
|
| 1064 |
|
|
C => clock_96MHz,
|
| 1065 |
|
|
D => s_ep_n_tri_next );
|
| 1066 |
|
|
END GENERATE make_data_in_ff;
|
| 1067 |
|
|
END xilinx;
|
