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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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library UNISIM;
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use UNISIM.VComponents.all;
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ARCHITECTURE xilinx OF spi_if IS
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TYPE STATE_TYPE IS (IDLE,INIT_READ,WAIT_READ,ALL_DONE,
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INIT_PAGE_LOAD,WAIT_I2C_DONE,INIT_STATE_REG_1,
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POLL_STATE_REG_1,INIT_WRITE,WAIT_WRITE, INIT_WRITE_BACK ,
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WAIT_WRITE_BACK,INIT_STATE_REG_2,POLL_STATE_REG_2);
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COMPONENT SPI_ACCESS
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GENERIC ( SIM_DEVICE : string );
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PORT( MISO : OUT std_ulogic;
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CLK : IN std_ulogic;
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CSB : IN std_ulogic;
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MOSI : IN std_ulogic );
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END COMPONENT;
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COMPONENT RAM32X1S
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PORT ( O : OUT std_logic;
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A0 : IN std_logic;
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A1 : IN std_logic;
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A2 : IN std_logic;
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A3 : IN std_logic;
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A4 : IN std_logic;
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D : IN std_logic;
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WCLK : IN std_logic;
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WE : IN std_logic);
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END COMPONENT;
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SIGNAL s_state_reg : STATE_TYPE;
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SIGNAL s_spi_shift_reg : std_logic_vector(31 DOWNTO 0 );
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SIGNAL s_spi_shift_next : std_logic_vector(31 DOWNTO 0 );
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SIGNAL s_spi_shift_load : std_logic_vector(31 DOWNTO 0 );
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SIGNAL s_n_ena_spi : std_logic;
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SIGNAL s_spi_miso : std_logic;
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SIGNAL s_spi_count_reg : std_logic_vector( 9 DOWNTO 0 );
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SIGNAL s_spi_count_load : std_logic_vector( 9 DOWNTO 0 );
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SIGNAL s_start_spi_action : std_logic;
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SIGNAL s_spi_clk_reg : std_logic;
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SIGNAL s_spi_mosi : std_logic;
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SIGNAL s_spi_ram_index_reg : std_logic_vector( 4 DOWNTO 0 );
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SIGNAL s_spi_size_reg : std_logic_vector( 5 DOWNTO 0 );
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SIGNAL s_spi_address_reg : std_logic_vector(11 DOWNTO 0 );
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SIGNAL s_load_data_byte : std_logic;
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SIGNAL s_buffer_data : std_logic_vector( 7 DOWNTO 0 );
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BEGIN
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-- Assign outputs
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data_out <= s_spi_shift_reg( 7 DOWNTO 0 );
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done <= '1' WHEN s_state_reg = ALL_DONE ELSE '0';
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busy <= '0' WHEN s_state_reg = IDLE OR
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s_state_reg = INIT_READ OR
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s_state_reg = WAIT_READ OR
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s_state_reg = ALL_DONE ELSE '1';
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-- Assign control signals
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s_start_spi_action <= '1' WHEN s_state_reg = INIT_READ OR
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s_state_reg = INIT_PAGE_LOAD OR
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s_state_reg = INIT_STATE_REG_1 OR
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s_state_reg = INIT_WRITE OR
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s_state_reg = INIT_WRITE_BACK OR
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s_state_reg = INIT_STATE_REG_2 ELSE '0';
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s_n_ena_spi <= s_spi_count_reg(9) AND NOT(s_spi_count_reg(0));
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s_load_data_byte <= '1' WHEN s_state_reg = WAIT_WRITE AND
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s_spi_count_reg( 2 DOWNTO 0 ) = "000" AND
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s_spi_clk_reg = '1' ELSE '0';
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s_spi_shift_next <= s_spi_shift_load
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WHEN s_start_spi_action = '1' ELSE
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s_spi_shift_reg WHEN s_n_ena_spi = '1' OR
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s_spi_clk_reg = '0' ELSE
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s_spi_shift_reg(30 DOWNTO 7)&s_buffer_data
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WHEN s_load_data_byte = '1' ELSE
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s_spi_shift_reg(30 DOWNTO 0)&s_spi_miso;
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-- map processes
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make_spi_load_values : PROCESS( s_state_reg , address ,
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s_spi_address_reg )
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VARIABLE v_select : std_logic_vector( 1 DOWNTO 0 );
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VARIABLE v_add : std_logic_vector( 5 DOWNTO 0 );
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BEGIN
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CASE (s_state_reg) IS
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WHEN INIT_READ => s_spi_shift_load <= X"030F"&"111"&
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s_spi_address_reg(11 DOWNTO 8)&"0"&
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s_spi_address_reg(7 DOWNTO 0);
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s_spi_count_load <= "0000100111";
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WHEN INIT_PAGE_LOAD => s_spi_shift_load <= X"530F"&"111"&
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s_spi_address_reg(11 DOWNTO 8)&"0"&
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X"00";
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s_spi_count_load <= "0000011111";
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WHEN INIT_STATE_REG_1 |
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INIT_STATE_REG_2=> s_spi_shift_load <= X"D7000000";
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s_spi_count_load <= "0000001111";
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WHEN INIT_WRITE => s_spi_shift_load <= X"840000"&s_spi_address_reg(7 DOWNTO 0);
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v_add := unsigned(s_spi_size_reg) + 3;
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s_spi_count_load <= "0"&v_add&"111";
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WHEN INIT_WRITE_BACK => s_spi_shift_load <= X"830F"&"111"&
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s_spi_address_reg(11 DOWNTO 8)&"0"&
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X"00";
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s_spi_count_load <= "0000011111";
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WHEN OTHERS => s_spi_shift_load <= X"00000000";
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s_spi_count_load <= "1111111110";
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END CASE;
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END PROCESS make_spi_load_values;
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make_state_machine : PROCESS( clock , reset , s_state_reg ,
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read_request , s_spi_count_reg ,
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write_request , i2c_write_done ,
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s_spi_shift_reg )
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VARIABLE v_next_state : STATE_TYPE;
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BEGIN
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CASE (s_state_reg) IS
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WHEN IDLE => IF (read_request = '1') THEN
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v_next_state := INIT_READ;
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ELSIF (write_request = '1') THEN
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v_next_state := INIT_PAGE_LOAD;
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ELSE
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v_next_state := IDLE;
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END IF;
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WHEN INIT_READ => v_next_state := WAIT_READ;
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WHEN WAIT_READ => IF (s_spi_count_reg(9) = '1') THEN
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v_next_state := ALL_DONE;
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ELSE
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v_next_state := WAIT_READ;
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END IF;
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WHEN INIT_PAGE_LOAD => v_next_state := WAIT_I2C_DONE;
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WHEN WAIT_I2C_DONE => IF (i2c_write_done = '1') THEN
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v_next_state := INIT_STATE_REG_1;
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ELSE
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v_next_state := WAIT_I2C_DONE;
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END IF;
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WHEN INIT_STATE_REG_1 => v_next_state := POLL_STATE_REG_1;
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WHEN POLL_STATE_REG_1 => IF (s_spi_count_reg(9) = '1' AND
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s_spi_count_reg(0) = '0') THEN
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IF (s_spi_shift_reg(7) = '0') THEN
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v_next_state := INIT_STATE_REG_1;
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ELSE
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v_next_state := INIT_WRITE;
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END IF;
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ELSE
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v_next_state := POLL_STATE_REG_1;
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END IF;
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WHEN INIT_WRITE => v_next_state := WAIT_WRITE;
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WHEN WAIT_WRITE => IF (s_spi_count_reg(9) = '1' AND
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s_spi_count_reg(0) = '0') THEN
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v_next_state := INIT_WRITE_BACK;
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ELSE
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v_next_state := WAIT_WRITE;
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END IF;
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WHEN INIT_WRITE_BACK => v_next_state := WAIT_WRITE_BACK;
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WHEN WAIT_WRITE_BACK => IF (s_spi_count_reg(9) = '1' AND
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s_spi_count_reg(0) = '0') THEN
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v_next_state := INIT_STATE_REG_2;
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ELSE
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v_next_state := WAIT_WRITE_BACK;
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END IF;
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WHEN INIT_STATE_REG_2 => v_next_state := POLL_STATE_REG_2;
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WHEN POLL_STATE_REG_2 => IF (s_spi_count_reg(9) = '1' AND
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s_spi_count_reg(0) = '0') THEN
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IF (s_spi_shift_reg(7) = '0') THEN
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v_next_state := INIT_STATE_REG_2;
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ELSE
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v_next_state := ALL_DONE;
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END IF;
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ELSE
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v_next_state := POLL_STATE_REG_2;
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END IF;
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WHEN OTHERS => v_next_state := IDLE;
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END CASE;
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_state_reg <= IDLE;
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ELSE s_state_reg <= v_next_state;
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END IF;
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END IF;
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END PROCESS make_state_machine;
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make_spi_count_reg : PROCESS( clock , reset , s_spi_count_reg ,
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s_start_spi_action )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_spi_count_reg <= (0 => '0' , OTHERS => '1');
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ELSIF (s_start_spi_action = '1') THEN s_spi_count_reg <= s_spi_count_load;
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ELSIF ((s_spi_count_reg(9) = '0' OR
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s_spi_count_reg(0) = '1') AND
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(s_spi_clk_reg = '0' OR
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(s_spi_count_reg(9) = '1' AND
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s_spi_count_reg(0) = '1'))) THEN
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s_spi_count_reg <= unsigned(s_spi_count_reg) - 1;
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END IF;
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END IF;
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END PROCESS make_spi_count_reg;
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make_spi_shift_reg : PROCESS( clock , s_spi_shift_next )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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s_spi_shift_reg <= s_spi_shift_next;
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END IF;
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END PROCESS make_spi_shift_reg;
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make_spi_clock_reg : PROCESS( clock , s_spi_count_reg , reset )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_spi_count_reg(9) = '1') THEN s_spi_clk_reg <= '1';
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ELSE s_spi_clk_reg <= NOT(s_spi_clk_reg);
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END IF;
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END IF;
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END PROCESS make_spi_clock_reg;
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make_spi_mosi : PROCESS( clock , s_spi_clk_reg , s_spi_shift_reg ,
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reset )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_spi_clk_reg = '1') THEN s_spi_mosi <= s_spi_shift_reg(31);
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END IF;
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END IF;
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END PROCESS make_spi_mosi;
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make_spi_ram_index_reg : PROCESS( clock , reset , s_state_reg ,
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write_request , s_load_data_byte )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1' OR
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s_state_reg = ALL_DONE OR
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s_state_reg = INIT_WRITE) THEN s_spi_ram_index_reg <= (OTHERS => '0');
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IF (s_state_reg /= INIT_WRITE) THEN
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s_spi_size_reg <= (OTHERS => '0');
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END IF;
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ELSIF (write_request = '1' OR
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s_load_data_byte = '1') THEN
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s_spi_ram_index_reg <= unsigned(s_spi_ram_index_reg) + 1;
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IF (s_spi_size_reg(5) = '0') THEN
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s_spi_size_reg <= unsigned(s_spi_size_reg) + 1;
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END IF;
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END IF;
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END IF;
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END PROCESS make_spi_ram_index_reg;
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make_spi_address_reg : PROCESS( clock , s_state_reg , write_request ,
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address , read_request )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF ((write_request = '1' AND
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s_state_reg = IDLE) OR
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read_request = '1') THEN
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s_spi_address_reg <= address;
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END IF;
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END IF;
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END PROCESS make_spi_address_reg;
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| 285 |
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-- map components
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spiif: SPI_ACCESS
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GENERIC MAP ( SIM_DEVICE => "3S200AN" )
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PORT MAP ( MISO => s_spi_miso,
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CLK => s_spi_clk_reg,
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CSB => s_n_ena_spi,
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MOSI => s_spi_mosi );
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write_buffer : FOR n IN 7 DOWNTO 0 GENERATE
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bufbit : RAM32X1S
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PORT MAP ( O => s_buffer_data(n),
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A0 => s_spi_ram_index_reg(0),
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A1 => s_spi_ram_index_reg(1),
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| 297 |
|
|
A2 => s_spi_ram_index_reg(2),
|
| 298 |
|
|
A3 => s_spi_ram_index_reg(3),
|
| 299 |
|
|
A4 => s_spi_ram_index_reg(4),
|
| 300 |
|
|
D => data_in(n),
|
| 301 |
|
|
WCLK => clock,
|
| 302 |
|
|
WE => write_request);
|
| 303 |
|
|
END GENERATE write_buffer;
|
| 304 |
|
|
|
| 305 |
|
|
END xilinx;
|
