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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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ARCHITECTURE no_target_specific OF status_controller IS
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TYPE STATUS_STATE_TYPE IS (IDLE,SIGNAL_DONE,SIGNAL_ERROR,CLEAR,
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GET_VALUE,STORE_VALUE,LATCH_RESULT,SET_OPC,
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CALC_100,CALC_10,INIT_SEND,DO_SEND,
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SET_TRANSPARENT);
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CONSTANT c_100 : std_logic_vector( 6 DOWNTO 0 ) := "1100100";
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CONSTANT c_10 : std_logic_vector( 3 DOWNTO 0 ) := X"A";
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SIGNAL s_command_state_reg : STATUS_STATE_TYPE;
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SIGNAL s_standard_event_status_register : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_standard_event_status_next : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_standard_event_status_enable_register : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_service_request_enable_register : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_status_byte_register : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_transparent_reg : std_logic;
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SIGNAL s_pop : std_logic;
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SIGNAL s_valid_data : std_logic;
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SIGNAL s_value_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_overflow : std_logic;
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SIGNAL s_result_reg : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_100_remain_reg : std_logic_vector( 6 DOWNTO 0 );
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SIGNAL s_100_div_reg : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL s_10_remain_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_10_div_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_send_cnt_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_push : std_logic;
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BEGIN
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--------------------------------------------------------------------------------
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--- Here the outputs are defined ---
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--------------------------------------------------------------------------------
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cmd_error <= '1' WHEN s_command_state_reg = SIGNAL_ERROR ELSE '0';
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done <= '1' WHEN s_command_state_reg = SIGNAL_DONE ELSE '0';
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pop <= s_pop;
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push <= s_push;
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push_size <= '1' WHEN s_send_cnt_reg = X"4" ELSE '0';
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transparent <= s_transparent_reg;
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status_nibble <= s_status_byte_register( 5 DOWNTO 2 );
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make_push_data : PROCESS( s_send_cnt_reg , s_10_div_reg , s_100_div_reg ,
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s_10_remain_reg )
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BEGIN
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CASE (s_send_cnt_reg) IS
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WHEN X"4" => IF (s_10_div_reg = X"0" AND
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s_100_div_reg = "00") THEN
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push_data <= X"02";
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ELSIF (s_100_div_reg = "00") THEN
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push_data <= X"03";
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ELSE
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push_data <= X"04";
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END IF;
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WHEN X"3" => push_data <= X"3"&"00"&s_100_div_reg;
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WHEN X"2" => push_data <= X"3"&s_10_div_reg;
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WHEN X"1" => push_data <= X"3"&s_10_remain_reg;
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WHEN X"0" => push_data <= X"0A";
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WHEN OTHERS => push_data <= X"00";
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END CASE;
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END PROCESS make_push_data;
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--------------------------------------------------------------------------------
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--- Here the control signals are defined ---
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--------------------------------------------------------------------------------
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s_pop <= '1' WHEN s_command_state_reg = GET_VALUE AND
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pop_empty = '0' ELSE '0';
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s_push <= '1' WHEN s_send_cnt_reg(3) = '0' AND
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push_full = '0' ELSE '0';
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s_valid_data <= '1' WHEN (pop_data = X"30" OR
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pop_data = X"31" OR
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pop_data = X"32" OR
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pop_data = X"33" OR
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pop_data = X"34" OR
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pop_data = X"35" OR
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pop_data = X"36" OR
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pop_data = X"37" OR
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pop_data = X"38" OR
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pop_data = X"39") AND
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s_pop = '1' ELSE '0';
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s_status_byte_register(7) <= '0';
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s_status_byte_register(6) <= (s_service_request_enable_register(7) AND
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s_status_byte_register(7))
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OR
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(s_service_request_enable_register(5) AND
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s_status_byte_register(5))
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OR
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(s_service_request_enable_register(4) AND
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s_status_byte_register(4))
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OR
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(s_service_request_enable_register(3) AND
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s_status_byte_register(3))
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OR
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(s_service_request_enable_register(2) AND
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s_status_byte_register(2))
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OR
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(s_service_request_enable_register(1) AND
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s_status_byte_register(1))
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OR
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(s_service_request_enable_register(0) AND
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s_status_byte_register(0));
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s_status_byte_register(5) <= ((s_standard_event_status_register(0) AND
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s_standard_event_status_enable_register(0))
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OR
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(s_standard_event_status_register(1) AND
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s_standard_event_status_enable_register(1))
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OR
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(s_standard_event_status_register(2) AND
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s_standard_event_status_enable_register(2))
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OR
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(s_standard_event_status_register(3) AND
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s_standard_event_status_enable_register(3))
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OR
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(s_standard_event_status_register(4) AND
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s_standard_event_status_enable_register(4))
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OR
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(s_standard_event_status_register(5) AND
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s_standard_event_status_enable_register(5))
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OR
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(s_standard_event_status_register(6) AND
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s_standard_event_status_enable_register(6))
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OR
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(s_standard_event_status_register(7) AND
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s_standard_event_status_enable_register(7)))
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WHEN s_transparent_reg = '0' ELSE
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ESB_bit;
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s_status_byte_register(4) <= NOT(push_empty); -- MAV bit
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s_status_byte_register(3) <= STATUS3_bit WHEN s_transparent_reg = '1' ELSE
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fpga_configured;
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s_status_byte_register(2) <= s_transparent_reg;
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s_status_byte_register(1) <= '0';
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s_status_byte_register(0) <= '0';
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s_standard_event_status_next(0) <= '1' WHEN s_command_state_reg = SET_OPC ELSE
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s_standard_event_status_register(0);
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s_standard_event_status_next(1) <= s_standard_event_status_register(1);
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s_standard_event_status_next(2) <= s_standard_event_status_register(2);
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s_standard_event_status_next(3) <= s_standard_event_status_register(3);
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s_standard_event_status_next(4) <= s_standard_event_status_register(4) OR
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execution_error;
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s_standard_event_status_next(5) <= s_standard_event_status_register(5) OR
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command_error;
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s_standard_event_status_next(6) <= s_standard_event_status_register(6);
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s_standard_event_status_next(7) <= s_standard_event_status_register(7);
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--------------------------------------------------------------------------------
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--- Here the state machine is defined ---
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--------------------------------------------------------------------------------
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make_state_machine : PROCESS( clock , reset , s_command_state_reg , start ,
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command )
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VARIABLE v_next_state : STATUS_STATE_TYPE;
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BEGIN
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CASE (s_command_state_reg) IS
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WHEN IDLE => IF (start = '1') THEN
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CASE (command) IS
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WHEN "0000010" => v_next_state := CLEAR;
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WHEN "0000110" |
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"0010000" => v_next_state := GET_VALUE;
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WHEN "0000111" |
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"0001000" |
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"0010001" |
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"0010010" |
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"0001100" |
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"0010100" |
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"0001010" => v_next_state := LATCH_RESULT;
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WHEN "0001011" => v_next_state := SET_OPC;
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WHEN "0010101" => v_next_state := SIGNAL_DONE;
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WHEN "0110011" => v_next_state := SET_TRANSPARENT;
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WHEN OTHERS => v_next_state := IDLE;
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END CASE;
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ELSE
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v_next_state := IDLE;
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END IF;
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WHEN CLEAR => v_next_state := SIGNAL_DONE;
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WHEN GET_VALUE => IF (s_overflow = '1') THEN
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v_next_state := SIGNAL_ERROR;
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ELSIF (s_pop = '1') THEN
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IF (pop_data = X"0A" OR
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pop_data = X"3B" OR
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(pop_last = '1' AND
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(s_valid_data = '1' OR
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pop_data = X"20"))) THEN
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v_next_state := STORE_VALUE;
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ELSIF (pop_last = '0' AND
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(s_valid_data = '1' OR
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pop_data = X"20")) THEN
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v_next_state := GET_VALUE;
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ELSE
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v_next_state := SIGNAL_ERROR;
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END IF;
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ELSE
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v_next_state := GET_VALUE;
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END IF;
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WHEN STORE_VALUE => v_next_state := SIGNAL_DONE;
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WHEN LATCH_RESULT => v_next_state := CALC_100;
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WHEN CALC_100 => v_next_state := CALC_10;
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WHEN CALC_10 => v_next_state := INIT_SEND;
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WHEN INIT_SEND => v_next_state := DO_SEND;
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WHEN DO_SEND => IF (s_send_cnt_reg(3) = '1') THEN
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v_next_state := SIGNAL_DONE;
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ELSE
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v_next_state := DO_SEND;
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END IF;
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WHEN SET_OPC => v_next_state := SIGNAL_DONE;
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WHEN SET_TRANSPARENT => IF (fpga_configured = '1') THEN
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v_next_state := SIGNAL_DONE;
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ELSE
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v_next_state := SIGNAL_ERROR;
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END IF;
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WHEN OTHERS => v_next_state := IDLE;
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END CASE;
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_command_state_reg <= IDLE;
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ELSE s_command_state_reg <= v_next_state;
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END IF;
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END IF;
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END PROCESS make_state_machine;
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--------------------------------------------------------------------------------
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--- Here the value handling is defined ---
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--------------------------------------------------------------------------------
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make_value_reg : PROCESS( clock , s_command_state_reg , pop_data ,
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s_valid_data )
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VARIABLE v_add_1 : std_logic_vector(11 DOWNTO 0 );
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VARIABLE v_add_2 : std_logic_vector(11 DOWNTO 0 );
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VARIABLE v_add_3 : std_logic_vector(11 DOWNTO 0 );
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VARIABLE v_sum : std_logic_vector(11 DOWNTO 0 );
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (s_command_state_reg = IDLE) THEN
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s_value_reg <= X"00";
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s_overflow <= '0';
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ELSIF (s_valid_data = '1') THEN
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v_add_1 := X"00"&pop_data( 3 DOWNTO 0 );
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v_add_2 := "000"&s_value_reg&"0";
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v_add_3 := "0"&s_value_reg&"000";
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v_sum := unsigned(v_add_1) + unsigned(v_add_2) + unsigned(v_add_3);
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s_value_reg <= v_sum( 7 DOWNTO 0 );
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s_overflow <= v_sum(8) OR v_sum(9) OR v_sum(10) OR v_sum(11);
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END IF;
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END IF;
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END PROCESS make_value_reg;
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--------------------------------------------------------------------------------
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--- Here the query handling is defined ---
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--------------------------------------------------------------------------------
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make_result_reg : PROCESS( clock , s_command_state_reg , reset )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN s_result_reg <= X"00";
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ELSIF (s_command_state_reg = LATCH_RESULT) THEN
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CASE (command) IS
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WHEN "0000111" => s_result_reg <= s_standard_event_status_enable_register;
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WHEN "0001000" => s_result_reg <= s_standard_event_status_register;
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WHEN "0010001" => s_result_reg <= s_service_request_enable_register;
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WHEN "0010010" => s_result_reg <= s_status_byte_register;
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WHEN "0001100" => s_result_reg <= X"01";
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WHEN OTHERS => s_result_reg <= X"00";
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END CASE;
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END IF;
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END IF;
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END PROCESS make_result_reg;
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make_100_regs : PROCESS( clock , s_result_reg )
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VARIABLE v_sub_1_1 : std_logic_vector( 8 DOWNTO 0 );
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VARIABLE v_sub_1_2 : std_logic_vector( 8 DOWNTO 0 );
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VARIABLE v_sub_1 : std_logic_vector( 8 DOWNTO 0 );
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VARIABLE v_sub_2_1 : std_logic_vector( 7 DOWNTO 0 );
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VARIABLE v_sub_2_2 : std_logic_vector( 7 DOWNTO 0 );
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VARIABLE v_sub_2 : std_logic_vector( 7 DOWNTO 0 );
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BEGIN
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v_sub_1_1 := "0"&s_result_reg;
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v_sub_1_2 := "0"&c_100&"0";
|
306 |
|
|
v_sub_1 := unsigned(v_sub_1_1)-unsigned(v_sub_1_2);
|
307 |
|
|
IF (v_sub_1(8) = '0') THEN v_sub_2_1 := v_sub_1( 7 DOWNTO 0 );
|
308 |
|
|
ELSE v_sub_2_1 := s_result_reg;
|
309 |
|
|
END IF;
|
310 |
|
|
v_sub_2_2 := "0"&c_100;
|
311 |
|
|
v_sub_2 := unsigned(v_sub_2_1) - unsigned(v_sub_2_2);
|
312 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
313 |
|
|
IF (v_sub_2(7) = '0') THEN s_100_remain_reg <= v_sub_2( 6 DOWNTO 0 );
|
314 |
|
|
ELSE s_100_remain_reg <= v_sub_2_1( 6 DOWNTO 0 );
|
315 |
|
|
END IF;
|
316 |
|
|
s_100_div_reg(1) <= NOT(v_sub_1(8));
|
317 |
|
|
s_100_div_reg(0) <= NOT(v_sub_2(7));
|
318 |
|
|
END IF;
|
319 |
|
|
END PROCESS make_100_regs;
|
320 |
|
|
|
321 |
|
|
make_10_regs : PROCESS( clock , s_100_remain_reg )
|
322 |
|
|
VARIABLE v_sub_1 : std_logic_vector( 4 DOWNTO 0 );
|
323 |
|
|
VARIABLE v_remain_1 : std_logic_vector( 4 DOWNTO 0 );
|
324 |
|
|
VARIABLE v_sub_2 : std_logic_vector( 4 DOWNTO 0 );
|
325 |
|
|
VARIABLE v_remain_2 : std_logic_vector( 4 DOWNTO 0 );
|
326 |
|
|
VARIABLE v_sub_3 : std_logic_vector( 4 DOWNTO 0 );
|
327 |
|
|
VARIABLE v_remain_3 : std_logic_vector( 4 DOWNTO 0 );
|
328 |
|
|
VARIABLE v_sub_4 : std_logic_vector( 4 DOWNTO 0 );
|
329 |
|
|
BEGIN
|
330 |
|
|
v_sub_1 := unsigned("0"&s_100_remain_reg(6 DOWNTO 3)) -
|
331 |
|
|
unsigned("0"&c_10);
|
332 |
|
|
IF (v_sub_1(4) = '0') THEN
|
333 |
|
|
v_remain_1 := v_sub_1(3 DOWNTO 0)&s_100_remain_reg(2);
|
334 |
|
|
ELSE
|
335 |
|
|
v_remain_1 := s_100_remain_reg(6 DOWNTO 2);
|
336 |
|
|
END IF;
|
337 |
|
|
v_sub_2 := unsigned(v_remain_1) - unsigned("0"&c_10);
|
338 |
|
|
IF (v_sub_2(4) = '0') THEN
|
339 |
|
|
v_remain_2 := v_sub_2(3 DOWNTO 0)&s_100_remain_reg(1);
|
340 |
|
|
ELSE
|
341 |
|
|
v_remain_2 := v_remain_1(3 DOWNTO 0)&s_100_remain_reg(1);
|
342 |
|
|
END IF;
|
343 |
|
|
v_sub_3 := unsigned(v_remain_2) - unsigned("0"&c_10);
|
344 |
|
|
IF (v_sub_3(4) = '0') THEN
|
345 |
|
|
v_remain_3 := v_sub_3(3 DOWNTO 0)&s_100_remain_reg(0);
|
346 |
|
|
ELSE
|
347 |
|
|
v_remain_3 := v_remain_2(3 DOWNTO 0)&s_100_remain_reg(0);
|
348 |
|
|
END IF;
|
349 |
|
|
v_sub_4 := unsigned(v_remain_3) - unsigned("0"&c_10);
|
350 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
351 |
|
|
IF (v_sub_4(4) = '0') THEN s_10_remain_reg <= v_sub_4(3 DOWNTO 0);
|
352 |
|
|
ELSE s_10_remain_reg <= v_remain_3(3 DOWNTO 0);
|
353 |
|
|
END IF;
|
354 |
|
|
s_10_div_reg(3) <= NOT(v_sub_1(4));
|
355 |
|
|
s_10_div_reg(2) <= NOT(v_sub_2(4));
|
356 |
|
|
s_10_div_reg(1) <= NOT(v_sub_3(4));
|
357 |
|
|
s_10_div_reg(0) <= NOT(v_sub_4(4));
|
358 |
|
|
END IF;
|
359 |
|
|
END PROCESS make_10_regs;
|
360 |
|
|
|
361 |
|
|
--------------------------------------------------------------------------------
|
362 |
|
|
--- Here the data sending is defined ---
|
363 |
|
|
--------------------------------------------------------------------------------
|
364 |
|
|
make_send_cnt_reg : PROCESS( clock , reset , s_command_state_reg , s_push )
|
365 |
|
|
BEGIN
|
366 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
367 |
|
|
IF (reset = '1') THEN s_send_cnt_reg <= (OTHERS => '1');
|
368 |
|
|
ELSIF (s_command_state_reg = INIT_SEND) THEN
|
369 |
|
|
s_send_cnt_reg <= X"4";
|
370 |
|
|
ELSIF (s_push = '1') THEN
|
371 |
|
|
CASE (s_send_cnt_reg) IS
|
372 |
|
|
WHEN X"4" => IF (s_10_div_reg = X"0" AND
|
373 |
|
|
s_100_div_reg = "00") THEN
|
374 |
|
|
s_send_cnt_reg <= X"1";
|
375 |
|
|
ELSIF (s_100_div_reg = "00") THEN
|
376 |
|
|
s_send_cnt_reg <= X"2";
|
377 |
|
|
ELSE
|
378 |
|
|
s_send_cnt_reg <= X"3";
|
379 |
|
|
END IF;
|
380 |
|
|
WHEN OTHERS => s_send_cnt_reg <= unsigned(s_send_cnt_reg) - 1;
|
381 |
|
|
END CASE;
|
382 |
|
|
END IF;
|
383 |
|
|
END IF;
|
384 |
|
|
END PROCESS make_send_cnt_reg;
|
385 |
|
|
|
386 |
|
|
--------------------------------------------------------------------------------
|
387 |
|
|
--- Here all registers are defined ---
|
388 |
|
|
--------------------------------------------------------------------------------
|
389 |
|
|
make_seser : PROCESS( clock , reset , s_command_state_reg ,
|
390 |
|
|
command , s_value_reg)
|
391 |
|
|
BEGIN
|
392 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
393 |
|
|
IF (reset = '1') THEN s_standard_event_status_enable_register <= X"00";
|
394 |
|
|
ELSIF (s_command_state_reg = STORE_VALUE AND
|
395 |
|
|
command = "0000110" ) THEN
|
396 |
|
|
s_standard_event_status_enable_register <= s_value_reg;
|
397 |
|
|
END IF;
|
398 |
|
|
END IF;
|
399 |
|
|
END PROCESS make_seser;
|
400 |
|
|
|
401 |
|
|
make_sesr : PROCESS( clock , reset , s_command_state_reg ,
|
402 |
|
|
s_standard_event_status_next )
|
403 |
|
|
BEGIN
|
404 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
405 |
|
|
IF (reset = '1') THEN s_standard_event_status_register <= X"80";
|
406 |
|
|
ELSIF (s_command_state_reg = CLEAR OR
|
407 |
|
|
(s_command_state_reg = LATCH_RESULT AND
|
408 |
|
|
command = "0001000")) THEN
|
409 |
|
|
s_standard_event_status_register <= X"00";
|
410 |
|
|
ELSE
|
411 |
|
|
s_standard_event_status_register <= s_standard_event_status_next;
|
412 |
|
|
END IF;
|
413 |
|
|
END IF;
|
414 |
|
|
END PROCESS make_sesr;
|
415 |
|
|
|
416 |
|
|
make_srer : PROCESS( clock , reset , s_command_state_reg ,
|
417 |
|
|
command , s_value_reg)
|
418 |
|
|
BEGIN
|
419 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
420 |
|
|
IF (reset = '1') THEN s_service_request_enable_register <= X"00";
|
421 |
|
|
ELSIF (s_command_state_reg = STORE_VALUE AND
|
422 |
|
|
command = "0010000" ) THEN
|
423 |
|
|
s_service_request_enable_register <= s_value_reg;
|
424 |
|
|
END IF;
|
425 |
|
|
END IF;
|
426 |
|
|
END PROCESS make_srer;
|
427 |
|
|
|
428 |
|
|
make_transparent_reg : PROCESS( clock , reset , s_command_state_reg )
|
429 |
|
|
BEGIN
|
430 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
431 |
|
|
IF (s_command_state_reg = CLEAR OR
|
432 |
|
|
reset = '1') THEN s_transparent_reg <= '0';
|
433 |
|
|
ELSIF (s_command_state_reg = SET_TRANSPARENT AND
|
434 |
|
|
fpga_configured = '1') THEN
|
435 |
|
|
s_transparent_reg <= '1';
|
436 |
|
|
END IF;
|
437 |
|
|
END IF;
|
438 |
|
|
END PROCESS make_transparent_reg;
|
439 |
|
|
|
440 |
|
|
END no_target_specific;
|