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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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-- The unisim library is used for simulation of the xilinx specific components
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-- For generic usage please use:
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-- LIBRARY work;
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-- USE work.xilinx_generic.all;
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-- And use the xilinx generic package found in the xilinx generic module
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LIBRARY unisim;
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USE unisim.all;
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ARCHITECTURE xilinx OF SCPI_INTERFACE IS
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COMPONENT RAM16X1S
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GENERIC ( INIT : bit_vector(15 DOWNTO 0 ) );
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PORT ( O : OUT std_ulogic;
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A0 : IN std_ulogic;
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A1 : IN std_ulogic;
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A2 : IN std_ulogic;
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A3 : IN std_ulogic;
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D : IN std_ulogic;
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WCLK : IN std_ulogic;
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WE : IN std_ulogic );
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END COMPONENT;
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COMPONENT RAMB16_S9
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GENERIC ( INIT_00 : bit_vector;
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INIT_01 : bit_vector;
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INIT_02 : bit_vector;
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INIT_03 : bit_vector;
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INIT_04 : bit_vector;
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INIT_05 : bit_vector;
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INIT_06 : bit_vector;
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INIT_07 : bit_vector;
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INIT_08 : bit_vector;
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INIT_09 : bit_vector;
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INIT_0A : bit_vector;
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INIT_0B : bit_vector;
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INIT_0C : bit_vector;
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INIT_0D : bit_vector;
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INIT_0E : bit_vector;
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INIT_0F : bit_vector;
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INIT_10 : bit_vector;
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INIT_11 : bit_vector;
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INIT_12 : bit_vector;
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INIT_13 : bit_vector;
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INIT_14 : bit_vector;
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INIT_15 : bit_vector;
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INIT_16 : bit_vector;
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INIT_17 : bit_vector;
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INIT_18 : bit_vector;
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INIT_19 : bit_vector;
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INIT_1A : bit_vector;
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INIT_1B : bit_vector;
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INIT_1C : bit_vector;
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INIT_1D : bit_vector;
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INIT_1E : bit_vector;
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INIT_1F : bit_vector;
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INIT_20 : bit_vector;
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INIT_21 : bit_vector;
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INIT_22 : bit_vector;
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INIT_23 : bit_vector;
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INIT_24 : bit_vector;
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INIT_25 : bit_vector;
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INIT_26 : bit_vector;
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INIT_27 : bit_vector;
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INIT_28 : bit_vector;
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INIT_29 : bit_vector;
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INIT_2A : bit_vector;
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INIT_2B : bit_vector;
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INIT_2C : bit_vector;
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INIT_2D : bit_vector;
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INIT_2E : bit_vector;
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INIT_2F : bit_vector;
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INIT_30 : bit_vector;
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INIT_31 : bit_vector;
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INIT_32 : bit_vector;
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INIT_33 : bit_vector;
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INIT_34 : bit_vector;
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INIT_35 : bit_vector;
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INIT_36 : bit_vector;
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INIT_37 : bit_vector;
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INIT_38 : bit_vector;
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INIT_39 : bit_vector;
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INIT_3A : bit_vector;
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INIT_3B : bit_vector;
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INIT_3C : bit_vector;
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INIT_3D : bit_vector;
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INIT_3E : bit_vector;
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INIT_3F : bit_vector);
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PORT ( DO : OUT std_logic_vector( 7 DOWNTO 0 );
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DOP : OUT std_logic_vector( 0 DOWNTO 0 );
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ADDR : IN std_logic_vector( 10 DOWNTO 0 );
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DI : IN std_logic_vector( 7 DOWNTO 0 );
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DIP : IN std_logic_vector( 0 DOWNTO 0 );
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EN : IN std_logic;
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WE : IN std_logic;
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CLK : IN std_logic;
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SSR : IN std_logic );
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END COMPONENT;
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TYPE SCPI_STATES IS (IDLE,INIT_COMMAND_READ,READ_ONE_COMMAND,
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FLUSH_MESSAGE,SIGNAL_ERROR,
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INIT_COMMAND_SEARCH_7 , COMMAND_SEARCH_7 ,
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INIT_COMMAND_SEARCH_6 , COMMAND_SEARCH_6 ,
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INIT_COMMAND_SEARCH_5 , COMMAND_SEARCH_5 ,
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INIT_COMMAND_SEARCH_4 , COMMAND_SEARCH_4 ,
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INIT_COMMAND_SEARCH_3 , COMMAND_SEARCH_3 ,
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INIT_COMMAND_SEARCH_2 , COMMAND_SEARCH_2 ,
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INIT_COMMAND_SEARCH_1 , COMMAND_SEARCH_1 ,
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INIT_COMMAND_SEARCH_0 , COMMAND_SEARCH_0 ,
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FETCH_COMMAND_ID , WAIT_FOR_DONE );
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CONSTANT c_small_a_1 : std_logic_vector( 7 DOWNTO 0 ) := X"60";
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CONSTANT c_small_z_1 : std_logic_vector( 7 DOWNTO 0 ) := X"7B";
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SIGNAL s_scpi_state_machine : SCPI_STATES;
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SIGNAL s_n_clock : std_logic;
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SIGNAL s_pop_byte : std_logic;
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SIGNAL s_upcased_char : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_is_lower_case : std_logic;
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SIGNAL s_is_command_seperator : std_logic;
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SIGNAL s_command_buffer_address_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_write_byte : std_logic;
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SIGNAL s_command_too_long : std_logic;
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SIGNAL s_command_stored : std_logic;
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SIGNAL s_command_byte : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_command_char : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_command_rom_search_addr : std_logic_vector( 10 DOWNTO 0 );
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SIGNAL s_command_rom_data : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_rom_data_zero : std_logic;
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SIGNAL s_buffer_data_zero : std_logic;
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SIGNAL s_command_match : std_logic;
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SIGNAL s_command_smaller : std_logic;
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SIGNAL s_command_bigger : std_logic;
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SIGNAL s_search_command : std_logic;
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SIGNAL s_cmd_gen_respons_reg : std_logic;
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SIGNAL s_message_in_progress_reg : std_logic;
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BEGIN
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--------------------------------------------------------------------------------
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--- Here the outputs are defined ---
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--------------------------------------------------------------------------------
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pop <= s_pop_byte OR slave_pop;
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unknown_command <= '1' WHEN s_scpi_state_machine = COMMAND_SEARCH_0 AND
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(s_command_smaller = '1' OR
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s_command_bigger = '1') ELSE '0';
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make_command : PROCESS( clock , reset , s_scpi_state_machine ,
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s_command_rom_data , s_cmd_gen_respons_reg )
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BEGIN
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IF (clock'event AND (clock = '1')) THEN
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IF (reset = '1') THEN start_command <= '0';
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command_id <= (OTHERS => '0');
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cmd_gen_respons <= '0';
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ELSE
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IF (s_scpi_state_machine = FETCH_COMMAND_ID) THEN
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start_command <= '1';
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command_id <= s_command_rom_data( 6 DOWNTO 0 );
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cmd_gen_respons <= s_cmd_gen_respons_reg;
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ELSE
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start_command <= '0';
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cmd_gen_respons <= '0';
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END IF;
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END IF;
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END IF;
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END PROCESS make_command;
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--------------------------------------------------------------------------------
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--- Here the state machine is defined ---
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--------------------------------------------------------------------------------
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make_scpi_state_machine : PROCESS( clock , reset , s_scpi_state_machine ,
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transparent_mode , pop_empty,
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s_command_too_long ,
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s_command_stored , s_command_match ,
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s_command_bigger , s_command_smaller )
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VARIABLE v_next_state : SCPI_STATES;
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BEGIN
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CASE (s_scpi_state_machine) IS
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WHEN IDLE => IF (transparent_mode = '0' AND
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pop_empty = '0') THEN
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v_next_state := INIT_COMMAND_READ;
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ELSE
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v_next_state := IDLE;
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END IF;
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WHEN INIT_COMMAND_READ => v_next_state := READ_ONE_COMMAND;
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WHEN READ_ONE_COMMAND => IF (s_command_too_long = '1') THEN
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v_next_state := FLUSH_MESSAGE;
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ELSIF (s_command_stored = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_7;
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ELSIF (pop_last = '1' AND
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pop_empty = '0') THEN
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v_next_state := SIGNAL_ERROR;
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ELSE
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v_next_state := READ_ONE_COMMAND;
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END IF;
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WHEN INIT_COMMAND_SEARCH_7 => v_next_state := COMMAND_SEARCH_7;
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WHEN COMMAND_SEARCH_7 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_6;
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ELSE
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v_next_state := COMMAND_SEARCH_7;
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END IF;
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WHEN INIT_COMMAND_SEARCH_6 => v_next_state := COMMAND_SEARCH_6;
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WHEN COMMAND_SEARCH_6 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_5;
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ELSE
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v_next_state := COMMAND_SEARCH_6;
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END IF;
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WHEN INIT_COMMAND_SEARCH_5 => v_next_state := COMMAND_SEARCH_5;
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WHEN COMMAND_SEARCH_5 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_4;
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ELSE
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v_next_state := COMMAND_SEARCH_5;
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END IF;
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WHEN INIT_COMMAND_SEARCH_4 => v_next_state := COMMAND_SEARCH_4;
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WHEN COMMAND_SEARCH_4 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_3;
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ELSE
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v_next_state := COMMAND_SEARCH_4;
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END IF;
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WHEN INIT_COMMAND_SEARCH_3 => v_next_state := COMMAND_SEARCH_3;
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WHEN COMMAND_SEARCH_3 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_2;
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ELSE
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v_next_state := COMMAND_SEARCH_3;
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END IF;
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WHEN INIT_COMMAND_SEARCH_2 => v_next_state := COMMAND_SEARCH_2;
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WHEN COMMAND_SEARCH_2 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_1;
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ELSE
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v_next_state := COMMAND_SEARCH_2;
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END IF;
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WHEN INIT_COMMAND_SEARCH_1 => v_next_state := COMMAND_SEARCH_1;
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WHEN COMMAND_SEARCH_1 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := INIT_COMMAND_SEARCH_0;
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ELSE
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v_next_state := COMMAND_SEARCH_1;
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END IF;
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WHEN INIT_COMMAND_SEARCH_0 => v_next_state := COMMAND_SEARCH_0;
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WHEN COMMAND_SEARCH_0 => IF (s_command_match = '1') THEN
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v_next_state := FETCH_COMMAND_ID;
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ELSIF (s_command_smaller = '1' OR
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s_command_bigger = '1') THEN
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v_next_state := FLUSH_MESSAGE;
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ELSE
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v_next_state := COMMAND_SEARCH_0;
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END IF;
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WHEN FETCH_COMMAND_ID => v_next_state := WAIT_FOR_DONE;
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WHEN WAIT_FOR_DONE => IF (command_error = '1') THEN
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v_next_state := FLUSH_MESSAGE;
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| 300 |
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ELSIF (command_done = '1') THEN
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v_next_state := IDLE;
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|
|
ELSE
|
| 303 |
|
|
v_next_state := WAIT_FOR_DONE;
|
| 304 |
|
|
END IF;
|
| 305 |
|
|
WHEN FLUSH_MESSAGE => IF (s_message_in_progress_reg = '1') THEN
|
| 306 |
|
|
v_next_state := FLUSH_MESSAGE;
|
| 307 |
|
|
ELSE
|
| 308 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 309 |
|
|
END IF;
|
| 310 |
|
|
WHEN OTHERS => v_next_state := IDLE;
|
| 311 |
|
|
END CASE;
|
| 312 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 313 |
|
|
IF (reset = '1') THEN s_scpi_state_machine <= IDLE;
|
| 314 |
|
|
ELSE s_scpi_state_machine <= v_next_state;
|
| 315 |
|
|
END IF;
|
| 316 |
|
|
END IF;
|
| 317 |
|
|
END PROCESS make_scpi_state_machine;
|
| 318 |
|
|
|
| 319 |
|
|
--------------------------------------------------------------------------------
|
| 320 |
|
|
--- Here the message in progress reg is defined ---
|
| 321 |
|
|
--------------------------------------------------------------------------------
|
| 322 |
|
|
make_message_in_progress_reg : PROCESS( clock , reset ,
|
| 323 |
|
|
s_scpi_state_machine )
|
| 324 |
|
|
BEGIN
|
| 325 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 326 |
|
|
IF (reset = '1' OR
|
| 327 |
|
|
(pop_last = '1' AND
|
| 328 |
|
|
(s_pop_byte = '1' OR
|
| 329 |
|
|
slave_pop = '1'))) THEN s_message_in_progress_reg <= '0';
|
| 330 |
|
|
ELSIF (s_scpi_state_machine = INIT_COMMAND_READ) THEN
|
| 331 |
|
|
s_message_in_progress_reg <= '1';
|
| 332 |
|
|
END IF;
|
| 333 |
|
|
END IF;
|
| 334 |
|
|
END PROCESS make_message_in_progress_reg;
|
| 335 |
|
|
|
| 336 |
|
|
--------------------------------------------------------------------------------
|
| 337 |
|
|
--- Here the input fifo handling is defined ---
|
| 338 |
|
|
--------------------------------------------------------------------------------
|
| 339 |
|
|
s_pop_byte <= '1' WHEN (s_scpi_state_machine = READ_ONE_COMMAND OR
|
| 340 |
|
|
(s_scpi_state_machine = FLUSH_MESSAGE AND
|
| 341 |
|
|
s_message_in_progress_reg = '1')) AND
|
| 342 |
|
|
pop_empty = '0'
|
| 343 |
|
|
ELSE '0';
|
| 344 |
|
|
|
| 345 |
|
|
--------------------------------------------------------------------------------
|
| 346 |
|
|
--- Here the command buffer handling is defined ---
|
| 347 |
|
|
--------------------------------------------------------------------------------
|
| 348 |
|
|
s_n_clock <= NOT( clock );
|
| 349 |
|
|
s_upcased_char(7 DOWNTO 6) <= pop_data(7 DOWNTO 6);
|
| 350 |
|
|
s_upcased_char( 5) <= pop_data(5) XOR s_is_lower_case;
|
| 351 |
|
|
s_upcased_char(4 DOWNTO 0) <= pop_data(4 DOWNTO 0);
|
| 352 |
|
|
s_command_rom_search_addr( 3 DOWNTO 0 ) <= s_command_buffer_address_reg;
|
| 353 |
|
|
|
| 354 |
|
|
|
| 355 |
|
|
s_is_lower_case <= '1' WHEN
|
| 356 |
|
|
(unsigned(pop_data) > unsigned(c_small_a_1)) AND
|
| 357 |
|
|
(unsigned(pop_data) < unsigned(c_small_z_1)) ELSE '0';
|
| 358 |
|
|
s_is_command_seperator <= '1' WHEN pop_data = X"0A" OR
|
| 359 |
|
|
pop_data = X"20" OR
|
| 360 |
|
|
pop_data = X"3B" ELSE '0';
|
| 361 |
|
|
s_write_byte <= '1' WHEN
|
| 362 |
|
|
(s_is_command_seperator = '0' AND
|
| 363 |
|
|
s_pop_byte = '1' AND
|
| 364 |
|
|
s_scpi_state_machine = READ_ONE_COMMAND) OR
|
| 365 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_7 ELSE '0';
|
| 366 |
|
|
s_command_too_long <= '1' WHEN s_is_command_seperator = '0' AND
|
| 367 |
|
|
pop_empty = '0' AND
|
| 368 |
|
|
s_command_buffer_address_reg = X"F"
|
| 369 |
|
|
ELSE '0';
|
| 370 |
|
|
s_command_stored <= '1' WHEN
|
| 371 |
|
|
(s_pop_byte = '1' AND
|
| 372 |
|
|
s_is_command_seperator = '1' AND
|
| 373 |
|
|
s_command_buffer_address_reg /= X"0")
|
| 374 |
|
|
ELSE '0';
|
| 375 |
|
|
s_command_byte <= X"00" WHEN s_scpi_state_machine = INIT_COMMAND_SEARCH_7
|
| 376 |
|
|
ELSE s_upcased_char;
|
| 377 |
|
|
s_rom_data_zero <= '1' WHEN s_command_rom_data = X"00" ELSE '0';
|
| 378 |
|
|
s_buffer_data_zero <= '1' WHEN s_command_char = X"00" ELSE '0';
|
| 379 |
|
|
s_command_match <= s_rom_data_zero AND s_buffer_data_zero;
|
| 380 |
|
|
s_command_smaller <= '1' WHEN unsigned(s_command_char) <
|
| 381 |
|
|
unsigned(s_command_rom_data) ELSE '0';
|
| 382 |
|
|
s_command_bigger <= '1' WHEN unsigned(s_command_char) >
|
| 383 |
|
|
unsigned(s_command_rom_data) ELSE '0';
|
| 384 |
|
|
s_search_command <= '1' WHEN
|
| 385 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_7 OR
|
| 386 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_6 OR
|
| 387 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_5 OR
|
| 388 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_4 OR
|
| 389 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_3 OR
|
| 390 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_2 OR
|
| 391 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_1 OR
|
| 392 |
|
|
s_scpi_state_machine = COMMAND_SEARCH_0
|
| 393 |
|
|
ELSE '0';
|
| 394 |
|
|
|
| 395 |
|
|
make_cmd_gen_respons_reg : PROCESS( clock , reset , s_scpi_state_machine ,
|
| 396 |
|
|
s_command_byte , s_write_byte )
|
| 397 |
|
|
BEGIN
|
| 398 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 399 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_READ OR
|
| 400 |
|
|
reset = '1') THEN s_cmd_gen_respons_reg <= '0';
|
| 401 |
|
|
ELSIF (s_write_byte = '1' AND
|
| 402 |
|
|
s_command_byte = X"3F") THEN
|
| 403 |
|
|
s_cmd_gen_respons_reg <= '1';
|
| 404 |
|
|
END IF;
|
| 405 |
|
|
END IF;
|
| 406 |
|
|
END PROCESS make_cmd_gen_respons_reg;
|
| 407 |
|
|
|
| 408 |
|
|
make_command_rom_search_addr_7 : PROCESS( clock , reset ,
|
| 409 |
|
|
s_scpi_state_machine ,
|
| 410 |
|
|
s_command_smaller )
|
| 411 |
|
|
BEGIN
|
| 412 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 413 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 414 |
|
|
reset = '1') THEN s_command_rom_search_addr(10) <= '1';
|
| 415 |
|
|
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_7 AND
|
| 416 |
|
|
s_command_smaller = '1') THEN
|
| 417 |
|
|
s_command_rom_search_addr(10) <= '0';
|
| 418 |
|
|
END IF;
|
| 419 |
|
|
END IF;
|
| 420 |
|
|
END PROCESS make_command_rom_search_addr_7;
|
| 421 |
|
|
|
| 422 |
|
|
make_command_rom_search_addr_6 : PROCESS( clock , reset ,
|
| 423 |
|
|
s_scpi_state_machine ,
|
| 424 |
|
|
s_command_smaller )
|
| 425 |
|
|
BEGIN
|
| 426 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 427 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 428 |
|
|
reset = '1') THEN s_command_rom_search_addr(9) <= '0';
|
| 429 |
|
|
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_6) THEN
|
| 430 |
|
|
s_command_rom_search_addr(9) <= '1';
|
| 431 |
|
|
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_6 AND
|
| 432 |
|
|
s_command_smaller = '1') THEN
|
| 433 |
|
|
s_command_rom_search_addr(9) <= '0';
|
| 434 |
|
|
END IF;
|
| 435 |
|
|
END IF;
|
| 436 |
|
|
END PROCESS make_command_rom_search_addr_6;
|
| 437 |
|
|
|
| 438 |
|
|
make_command_rom_search_addr_5 : PROCESS( clock , reset ,
|
| 439 |
|
|
s_scpi_state_machine ,
|
| 440 |
|
|
s_command_smaller )
|
| 441 |
|
|
BEGIN
|
| 442 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 443 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 444 |
|
|
reset = '1') THEN s_command_rom_search_addr(8) <= '0';
|
| 445 |
|
|
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_5) THEN
|
| 446 |
|
|
s_command_rom_search_addr(8) <= '1';
|
| 447 |
|
|
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_5 AND
|
| 448 |
|
|
s_command_smaller = '1') THEN
|
| 449 |
|
|
s_command_rom_search_addr(8) <= '0';
|
| 450 |
|
|
END IF;
|
| 451 |
|
|
END IF;
|
| 452 |
|
|
END PROCESS make_command_rom_search_addr_5;
|
| 453 |
|
|
|
| 454 |
|
|
make_command_rom_search_addr_4 : PROCESS( clock , reset ,
|
| 455 |
|
|
s_scpi_state_machine ,
|
| 456 |
|
|
s_command_smaller )
|
| 457 |
|
|
BEGIN
|
| 458 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 459 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 460 |
|
|
reset = '1') THEN s_command_rom_search_addr(7) <= '0';
|
| 461 |
|
|
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_4) THEN
|
| 462 |
|
|
s_command_rom_search_addr(7) <= '1';
|
| 463 |
|
|
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_4 AND
|
| 464 |
|
|
s_command_smaller = '1') THEN
|
| 465 |
|
|
s_command_rom_search_addr(7) <= '0';
|
| 466 |
|
|
END IF;
|
| 467 |
|
|
END IF;
|
| 468 |
|
|
END PROCESS make_command_rom_search_addr_4;
|
| 469 |
|
|
|
| 470 |
|
|
make_command_rom_search_addr_3 : PROCESS( clock , reset ,
|
| 471 |
|
|
s_scpi_state_machine ,
|
| 472 |
|
|
s_command_smaller )
|
| 473 |
|
|
BEGIN
|
| 474 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 475 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 476 |
|
|
reset = '1') THEN s_command_rom_search_addr(6) <= '0';
|
| 477 |
|
|
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_3) THEN
|
| 478 |
|
|
s_command_rom_search_addr(6) <= '1';
|
| 479 |
|
|
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_3 AND
|
| 480 |
|
|
s_command_smaller = '1') THEN
|
| 481 |
|
|
s_command_rom_search_addr(6) <= '0';
|
| 482 |
|
|
END IF;
|
| 483 |
|
|
END IF;
|
| 484 |
|
|
END PROCESS make_command_rom_search_addr_3;
|
| 485 |
|
|
|
| 486 |
|
|
make_command_rom_search_addr_2 : PROCESS( clock , reset ,
|
| 487 |
|
|
s_scpi_state_machine ,
|
| 488 |
|
|
s_command_smaller )
|
| 489 |
|
|
BEGIN
|
| 490 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 491 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 492 |
|
|
reset = '1') THEN s_command_rom_search_addr(5) <= '0';
|
| 493 |
|
|
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_2) THEN
|
| 494 |
|
|
s_command_rom_search_addr(5) <= '1';
|
| 495 |
|
|
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_2 AND
|
| 496 |
|
|
s_command_smaller = '1') THEN
|
| 497 |
|
|
s_command_rom_search_addr(5) <= '0';
|
| 498 |
|
|
END IF;
|
| 499 |
|
|
END IF;
|
| 500 |
|
|
END PROCESS make_command_rom_search_addr_2;
|
| 501 |
|
|
|
| 502 |
|
|
make_command_rom_search_addr_1 : PROCESS( clock , reset ,
|
| 503 |
|
|
s_scpi_state_machine ,
|
| 504 |
|
|
s_command_smaller )
|
| 505 |
|
|
BEGIN
|
| 506 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 507 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 508 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_0 OR
|
| 509 |
|
|
reset = '1') THEN s_command_rom_search_addr(4) <= '0';
|
| 510 |
|
|
ELSIF (s_scpi_state_machine = INIT_COMMAND_SEARCH_1) THEN
|
| 511 |
|
|
s_command_rom_search_addr(4) <= '1';
|
| 512 |
|
|
ELSIF (s_scpi_state_machine = COMMAND_SEARCH_1 AND
|
| 513 |
|
|
s_command_smaller = '1') THEN
|
| 514 |
|
|
s_command_rom_search_addr(4) <= '0';
|
| 515 |
|
|
END IF;
|
| 516 |
|
|
END IF;
|
| 517 |
|
|
END PROCESS make_command_rom_search_addr_1;
|
| 518 |
|
|
|
| 519 |
|
|
make_command_buffer_address_reg : PROCESS( clock , reset , s_write_byte ,
|
| 520 |
|
|
s_scpi_state_machine ,
|
| 521 |
|
|
s_search_command )
|
| 522 |
|
|
BEGIN
|
| 523 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 524 |
|
|
IF (s_scpi_state_machine = INIT_COMMAND_READ OR
|
| 525 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_7 OR
|
| 526 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_6 OR
|
| 527 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_5 OR
|
| 528 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_4 OR
|
| 529 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_3 OR
|
| 530 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_2 OR
|
| 531 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_1 OR
|
| 532 |
|
|
s_scpi_state_machine = INIT_COMMAND_SEARCH_0 OR
|
| 533 |
|
|
reset = '1') THEN s_command_buffer_address_reg <= (OTHERS => '0');
|
| 534 |
|
|
ELSIF (s_write_byte = '1' OR
|
| 535 |
|
|
s_search_command = '1') THEN
|
| 536 |
|
|
s_command_buffer_address_reg <= unsigned(s_command_buffer_address_reg) + 1;
|
| 537 |
|
|
END IF;
|
| 538 |
|
|
END IF;
|
| 539 |
|
|
END PROCESS make_command_buffer_address_reg;
|
| 540 |
|
|
|
| 541 |
|
|
command_buffer : FOR n IN 7 DOWNTO 0 GENERATE
|
| 542 |
|
|
one_bit : RAM16X1S
|
| 543 |
|
|
GENERIC MAP ( INIT => X"0000" )
|
| 544 |
|
|
PORT MAP ( O => s_command_char(n),
|
| 545 |
|
|
A0 => s_command_buffer_address_reg(0),
|
| 546 |
|
|
A1 => s_command_buffer_address_reg(1),
|
| 547 |
|
|
A2 => s_command_buffer_address_reg(2),
|
| 548 |
|
|
A3 => s_command_buffer_address_reg(3),
|
| 549 |
|
|
D => s_command_byte(n),
|
| 550 |
|
|
WCLK => clock,
|
| 551 |
|
|
WE => s_write_byte );
|
| 552 |
|
|
END GENERATE command_buffer;
|
| 553 |
|
|
|
| 554 |
|
|
command_rom : RAMB16_S9
|
| 555 |
|
|
GENERIC MAP ( INIT_00 => X"FFFFFFFFFFFFFFFFFFFF06004553452AFFFFFFFFFFFFFFFFFFFF0200534C432A",
|
| 556 |
|
|
INIT_01 => X"FFFFFFFFFFFFFFFFFF08003F5253452AFFFFFFFFFFFFFFFFFF07003F4553452A",
|
| 557 |
|
|
INIT_02 => X"FFFFFFFFFFFFFFFFFF0A003F5453492AFFFFFFFFFFFFFFFFFF09003F4E44492A",
|
| 558 |
|
|
INIT_03 => X"FFFFFFFFFFFFFFFFFF0C003F43504F2AFFFFFFFFFFFFFFFFFFFF0B0043504F2A",
|
| 559 |
|
|
INIT_04 => X"FFFFFFFFFFFFFFFFFF0E003F4455502AFFFFFFFFFFFFFFFFFFFF0D004455502A",
|
| 560 |
|
|
INIT_05 => X"FFFFFFFFFFFFFFFFFFFF10004552532AFFFFFFFFFFFFFFFFFFFF0F005453522A",
|
| 561 |
|
|
INIT_06 => X"FFFFFFFFFFFFFFFFFF12003F4254532AFFFFFFFFFFFFFFFFFF11003F4552532A",
|
| 562 |
|
|
INIT_07 => X"FFFFFFFFFFFFFFFFFFFF15004941572AFFFFFFFFFFFFFFFFFF14003F5453542A",
|
| 563 |
|
|
INIT_08 => X"FFFFFFFFFF17003F4853414C46544942FFFFFFFFFFFF16004853414C46544942",
|
| 564 |
|
|
INIT_09 => X"FFFFFFFFFFFFFFFF19004749464E4F43FFFFFFFFFFFFFFFF18003F4452414F42",
|
| 565 |
|
|
INIT_0A => X"FFFFFFFFFFFFFFFFFFFF1B004F464946FFFFFFFFFFFFFFFFFF1A004553415245",
|
| 566 |
|
|
INIT_0B => X"FFFFFFFFFFFFFFFFFFFF1D0041475046FFFFFFFFFFFFFFFFFF1C003F4F464946",
|
| 567 |
|
|
INIT_0C => X"FFFFFFFFFF2300484354495753584548FFFFFFFFFFFFFFFFFF1E003F41475046",
|
| 568 |
|
|
INIT_0D => X"FFFFFFFFFFFF2500594649544E454449FFFFFFFF24003F484354495753584548",
|
| 569 |
|
|
INIT_0E => X"FFFFFFFFFF3A00544553455252455355FFFFFFFFFFFFFFFFFF3300534E415254",
|
| 570 |
|
|
INIT_0F => X"FFFFFFFFFF3C005241454C433A414756FFFFFFFFFF3B004C4F4347423A414756",
|
| 571 |
|
|
INIT_10 => X"FFFFFF3E003F524F535255433A414756FFFFFFFF3D00524F535255433A414756",
|
| 572 |
|
|
INIT_11 => X"FFFFFFFF40005254535455503A414756FFFFFFFFFF3F004C4F4347463A414756",
|
| 573 |
|
|
INIT_12 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 574 |
|
|
INIT_13 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 575 |
|
|
INIT_14 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 576 |
|
|
INIT_15 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 577 |
|
|
INIT_16 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 578 |
|
|
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 579 |
|
|
INIT_18 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 580 |
|
|
INIT_19 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 581 |
|
|
INIT_1A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 582 |
|
|
INIT_1B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 583 |
|
|
INIT_1C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 584 |
|
|
INIT_1D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 585 |
|
|
INIT_1E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 586 |
|
|
INIT_1F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 587 |
|
|
INIT_20 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 588 |
|
|
INIT_21 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 589 |
|
|
INIT_22 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 590 |
|
|
INIT_23 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 591 |
|
|
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 592 |
|
|
INIT_25 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 593 |
|
|
INIT_26 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 594 |
|
|
INIT_27 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 595 |
|
|
INIT_28 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 596 |
|
|
INIT_29 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 597 |
|
|
INIT_2A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 598 |
|
|
INIT_2B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 599 |
|
|
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 600 |
|
|
INIT_2D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 601 |
|
|
INIT_2E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 602 |
|
|
INIT_2F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 603 |
|
|
INIT_30 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 604 |
|
|
INIT_31 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 605 |
|
|
INIT_32 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 606 |
|
|
INIT_33 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 607 |
|
|
INIT_34 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 608 |
|
|
INIT_35 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 609 |
|
|
INIT_36 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 610 |
|
|
INIT_37 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 611 |
|
|
INIT_38 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 612 |
|
|
INIT_39 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 613 |
|
|
INIT_3A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 614 |
|
|
INIT_3B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 615 |
|
|
INIT_3C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 616 |
|
|
INIT_3D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 617 |
|
|
INIT_3E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
|
| 618 |
|
|
INIT_3F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE")
|
| 619 |
|
|
PORT MAP ( DO => s_command_rom_data,
|
| 620 |
|
|
DOP => OPEN,
|
| 621 |
|
|
ADDR => s_command_rom_search_addr,
|
| 622 |
|
|
DI => X"00",
|
| 623 |
|
|
DIP => "0",
|
| 624 |
|
|
EN => '1',
|
| 625 |
|
|
WE => '0',
|
| 626 |
|
|
CLK => s_n_clock,
|
| 627 |
|
|
SSR => '0' );
|
| 628 |
|
|
|
| 629 |
|
|
|
| 630 |
|
|
END xilinx;
|
