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[/] [gecko4/] [trunk/] [GECKO4com/] [spartan200_an/] [vhdl/] [user_fifo/] [user_fifo-behavior.vhdl] - Blame information for rev 5

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--------------------------------------------------------------------------------
--            _   _            __   ____                                      --
--           / / | |          / _| |  __|                                     --
--           | |_| |  _   _  / /   | |_                                       --
--           |  _  | | | | | | |   |  _|                                      --
--           | | | | | |_| | \ \_  | |__                                      --
--           |_| |_| \_____|  \__| |____| microLab                            --
--                                                                            --
--           Bern University of Applied Sciences (BFH)                        --
--           Quellgasse 21                                                    --
--           Room HG 4.33                                                     --
--           2501 Biel/Bienne                                                 --
--           Switzerland                                                      --
--                                                                            --
--           http://www.microlab.ch                                           --
--------------------------------------------------------------------------------
--   GECKO4com
--  
--   2010/2011 Dr. Theo Kluter
--  
--   This VHDL code is free code: you can redistribute it and/or modify
--   it under the terms of the GNU General Public License as published by
--   the Free Software Foundation, either version 3 of the License, or
--   (at your option) any later version.
--  
--   This VHDL code is distributed in the hope that it will be useful,
--   but WITHOUT ANY WARRANTY; without even the implied warranty of
--   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--   GNU General Public License for more details. 
--   You should have received a copy of the GNU General Public License
--   along with these sources.  If not, see <http://www.gnu.org/licenses/>.
--
 
--memory map:
-- 0x00 -> TX-fifo write data (WO)
-- 0x01 -> TX-fifo write message size (WO)
-- 0x02 -> Nr. of bytes in TX-fifo (RO)
-- 0x03 -> Max. size in bytes of TX-fifo (RO)
-- 0x04 -> Nr. of shorts in TX-fifo (RO)
-- 0x05 -> Max. size in shorts of TX-fifo (RO)
-- 0x06 -> Nr. of words in TX-fifo (RO)
-- 0x07 -> Max. size in words of TX-fifo (RO)
-- 0x08 -> RX-fifo read data (RO)
-- 0x09 -> RX-fifo read data (RO)
-- 0x0A -> Nr. of bytes in RX-fifo (RO)
-- 0x0B -> Max. size in bytes of RX-fifo (RO)
-- 0x0C -> Nr. of shorts in RX-fifo (RO)
-- 0x0D -> Max. size in shorts of RX-fifo (RO)
-- 0x0E -> Nr. of words in RX-fifo (RO)
-- 0x0F -> Max. size in words of RX-fifo (RO)
 
ARCHITECTURE no_target_specific OF user_fifo IS
 
   COMPONENT fifo_4kb_16w_8r
      PORT ( clock      : IN  std_logic;
             reset      : IN  std_logic;
             -- push port
             push       : IN  std_logic;
             push_data  : IN  std_logic_vector( 15 DOWNTO 0 );
             push_size  : IN  std_logic;
             -- pop port
             pop        : IN  std_logic;
             pop_data   : OUT std_logic_vector(  7 DOWNTO 0 );
             pop_size   : OUT std_logic;
             -- control port
             fifo_full  : OUT std_logic;
             fifo_empty : OUT std_logic;
             byte_cnt   : OUT std_logic_vector( 12 DOWNTO 0 ) );
   END COMPONENT;
 
   COMPONENT fifo_4kb_8w_16r
      PORT ( clock      : IN  std_logic;
             reset      : IN  std_logic;
             -- push port
             push       : IN  std_logic;
             push_data  : IN  std_logic_vector(  7 DOWNTO 0 );
             push_last  : IN  std_logic;
             -- pop port
             pop        : IN  std_logic;
             pop_data   : OUT std_logic_vector( 15 DOWNTO 0 );
             pop_last   : OUT std_logic_vector(  1 DOWNTO 0 );
             -- control port
             fifo_full  : OUT std_logic;
             fifo_empty : OUT std_logic;
             byte_cnt   : OUT std_logic_vector( 12 DOWNTO 0 ) );
   END COMPONENT;
 
   TYPE STATE_TYPE IS (IDLE,SIGNAL_DONE,SIGNAL_ERROR,SIGNAL_REQUEST,
                       GET_SIZE_0,GET_SIZE_1,GET_SIZE_2,GET_SIZE_3,
                       INIT_COPY,FLUSH_TX,COPY_TX_DATA,SIGNAL_MESSAGE,
                       COPY_RX_DATA,INSERT_DUMMY,SIGNAL_AVAILABLE);
 
   SIGNAL s_tx_fifo_byte_count_value   : std_logic_vector( 12 DOWNTO 0 );
   SIGNAL s_n_bus_error_next           : std_logic;
   SIGNAL s_tx_fifo_full               : std_logic;
   SIGNAL s_tx_fifo_empty              : std_logic;
   SIGNAL s_n_bus_error_reg            : std_logic;
   SIGNAL s_burst_cnt_reg              : std_logic_vector(  9 DOWNTO 0 );
   SIGNAL s_burst_cnt_next             : std_logic_vector(  9 DOWNTO 0 );
   SIGNAL s_n_end_reg                  : std_logic;
   SIGNAL s_is_my_write_burst_reg      : std_logic;
   SIGNAL s_do_push                    : std_logic;
 
   SIGNAL s_fifo_state_reg             : STATE_TYPE;
   SIGNAL s_tx_pop                     : std_logic;
   SIGNAL s_tx_pop_size                : std_logic;
   SIGNAL s_tx_pop_data                : std_logic_vector(  7 DOWNTO 0 );
   SIGNAL s_tx_payload_cnt_reg         : std_logic_vector( 32 DOWNTO 0 );
 
   SIGNAL s_rx_fifo_byte_count_value   : std_logic_vector( 12 DOWNTO 0 );
   SIGNAL s_rx_push                    : std_logic;
   SIGNAL s_rx_fifo_full               : std_logic;
   SIGNAL s_rx_byte_cnt_reg            : std_logic_vector(  1 DOWNTO 0 );
   SIGNAL s_pop_data                   : std_logic_vector(  7 DOWNTO 0 );
   SIGNAL s_pop_last                   : std_logic;
   SIGNAL s_dummy_data_reg             : std_logic_vector(  7 DOWNTO 0 );
   SIGNAL s_rx_fifo_empty              : std_logic;
   SIGNAL s_rx_fifo_pop                : std_logic;
   SIGNAL s_rx_fifo_data               : std_logic_vector( 15 DOWNTO 0 );
   SIGNAL s_rx_fifo_last               : std_logic_vector(  1 DOWNTO 0 );
   SIGNAL s_reset                      : std_logic;
 
BEGIN
   s_reset <= reset OR NOT(n_bus_reset);
 
--------------------------------------------------------------------------------
--- Here the signalling is defined                                           ---
--------------------------------------------------------------------------------
   make_error_irq : PROCESS( clock , s_do_push , s_tx_fifo_full ,
                             s_rx_fifo_empty , s_rx_fifo_pop )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF ((s_do_push = '1' AND
              s_tx_fifo_full = '1') OR
             (s_rx_fifo_empty = '1' AND
              s_rx_fifo_pop = '1') OR
             (s_fifo_state_reg = FLUSH_TX)) THEN error_irq <= '1';
                                            ELSE error_irq <= '0';
         END IF;
      END IF;
   END PROCESS make_error_irq;
 
   make_data_req_irg : PROCESS( clock , reset , s_fifo_state_reg )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '0' AND
             s_fifo_state_reg = SIGNAL_REQUEST) THEN data_request_irq <= '1';
                                                ELSE data_request_irq <= '0';
         END IF;
      END IF;
   END PROCESS make_data_req_irg;
 
   make_data_available_irq : PROCESS( clock , reset , s_fifo_state_reg )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '0' AND
             s_fifo_state_reg = SIGNAL_AVAILABLE) THEN data_available_irq <= '1';
                                                  ELSE data_available_irq <= '0';
         END IF;
      END IF;
   END PROCESS make_data_available_irq;
 
--------------------------------------------------------------------------------
--- Here the bus handling is defined                                         ---
--------------------------------------------------------------------------------
   n_start_send           <= '0' WHEN bus_address( 5 DOWNTO 4 ) = "00" AND
                                      n_start_transmission = '0' AND
                                      read_n_write = '0' AND
                                      s_n_bus_error_next = '1' ELSE '1';
   n_bus_error            <= s_n_bus_error_reg;
   n_end_transmission_out <= '0' WHEN s_n_bus_error_reg = '0' OR
                                      s_n_end_reg = '0' ELSE '1';
   make_data_valid : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '0' AND
             n_bus_reset = '1' AND
             s_burst_cnt_reg(9) = '0') THEN
            IF (s_rx_fifo_pop = '1' AND
                s_rx_fifo_last /= "00") THEN n_data_valid_out <= "01";
                                        ELSE n_data_valid_out <= "00";
            END IF;
                                       ELSE n_data_valid_out <= "11";
         END IF;
      END IF;
   END PROCESS make_data_valid;
 
   s_n_bus_error_next <= '0' WHEN bus_address( 5 DOWNTO 4) = "00" AND
                                  n_start_transmission = '0' AND
                                  ((bus_address(3 DOWNTO 1) = "000" AND
                                    (read_n_write = '1' OR
                                     s_tx_fifo_full = '1')) OR
                                   (bus_address(3 DOWNTO 1) /= "000" AND
                                    read_n_write = '0')) ELSE '1';
   s_burst_cnt_next   <= unsigned(s_burst_cnt_reg) - 1;
 
   make_data_out : PROCESS( clock , bus_address , s_tx_fifo_byte_count_value )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (bus_address(5 DOWNTO 4) = "00") THEN
            CASE (bus_address( 3 DOWNTO 0 )) IS
               WHEN  X"2"  => data_out <= "000"&s_tx_fifo_byte_count_value;
               WHEN  X"3"  => data_out <= X"1000";
               WHEN  X"4"  => data_out <= X"0"&s_tx_fifo_byte_count_value( 12 DOWNTO 1);
               WHEN  X"5"  => data_out <= X"0800";
               WHEN  X"6"  => data_out <= X"0"&"0"&s_tx_fifo_byte_count_value( 12 DOWNTO 2);
               WHEN  X"7"  => data_out <= X"0400";
               WHEN  X"8" |
                     X"9"  => data_out <= s_rx_fifo_data;
               WHEN  X"A"  => data_out <= "000"&s_rx_fifo_byte_count_value;
               WHEN  X"B"  => data_out <= X"1000";
               WHEN  X"C"  => data_out <= X"0"&s_rx_fifo_byte_count_value( 12 DOWNTO 1 );
               WHEN  X"D"  => data_out <= X"0800";
               WHEN  X"E"  => data_out <= X"0"&"0"&s_rx_fifo_byte_count_value( 12 DOWNTO 2 );
               WHEN  X"F"  => data_out <= X"0400";
               WHEN OTHERS => data_out <= X"0000";
            END CASE;
                                             ELSE
            data_out <= X"0000";
         END IF;
      END IF;
   END PROCESS make_data_out;
 
   make_n_bus_error_reg : PROCESS( clock , s_n_bus_error_next )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         s_n_bus_error_reg <= s_n_bus_error_next;
      END IF;
   END PROCESS make_n_bus_error_reg;
 
   make_n_end_reg : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg ,
                             s_burst_cnt_next )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '0' AND
             n_bus_reset = '1' AND
             s_burst_cnt_reg(9) = '0' AND
             s_burst_cnt_next(9) = '1') THEN s_n_end_reg <= '0';
                                        ELSE s_n_end_reg <= '1';
         END IF;
      END IF;
   END PROCESS make_n_end_reg;
 
   make_burst_cnt_reg : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (n_bus_reset = '0' OR
             reset = '1') THEN s_burst_cnt_reg <= (OTHERS => '1');
         ELSIF (bus_address( 5 DOWNTO 4 ) = "00" AND
                n_start_transmission = '0' AND
                read_n_write = '1' AND
                s_n_bus_error_next = '1') THEN
            s_burst_cnt_reg <= "0"&burst_size;
         ELSIF (s_burst_cnt_reg(9) = '0') THEN
            s_burst_cnt_reg <= s_burst_cnt_next;
         END IF;
      END IF;
   END PROCESS make_burst_cnt_reg;
 
   make_is_my_write_burst_reg : PROCESS( clock , reset , n_bus_reset )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '1' OR
             n_bus_reset = '0' OR
             n_end_transmission_in = '0') THEN s_is_my_write_burst_reg <= '0';
         ELSIF (bus_address( 5 DOWNTO 4 ) = "00" AND
                n_start_transmission = '0' AND
                read_n_write = '0' AND
                s_n_bus_error_next = '1') THEN s_is_my_write_burst_reg <= '1';
         END IF;
      END IF;
   END PROCESS make_is_my_write_burst_reg;
 
--------------------------------------------------------------------------------
--- Here the usbtmc interface is defined                                     ---
--------------------------------------------------------------------------------
   command_done  <= '1' WHEN s_fifo_state_reg = SIGNAL_DONE OR
                             s_fifo_state_reg = SIGNAL_ERROR ELSE '0';
   command_error <= '1' WHEN s_fifo_state_reg = SIGNAL_ERROR ELSE '0';
   message_available <= '1' WHEN s_fifo_state_reg = SIGNAL_MESSAGE ELSE '0';
 
   make_state_machine : PROCESS( clock , reset , s_fifo_state_reg )
      VARIABLE v_next_state : STATE_TYPE;
   BEGIN
      CASE (s_fifo_state_reg) IS
         WHEN IDLE                        => IF (start_command = '1' AND
                                                 command_id = "0011100") THEN
                                                v_next_state := SIGNAL_REQUEST;
                                             ELSIF ((start_command = '1' AND
                                                     command_id = "0011011") OR
                                                    (transparent_mode = '1' AND
                                                     pop_empty = '0')) THEN
                                                v_next_state := SIGNAL_AVAILABLE;
                                             ELSIF (transparent_mode = '1' AND
                                                    s_tx_fifo_empty = '0') THEN
                                                v_next_state := SIGNAL_MESSAGE;
                                                                  ELSE
                                                v_next_state := IDLE;
                                             END IF;
         WHEN SIGNAL_REQUEST              |
              SIGNAL_MESSAGE              => v_next_state := GET_SIZE_0;
         WHEN GET_SIZE_0                  => IF (s_tx_fifo_empty = '0') THEN
                                                IF (s_tx_pop_size = '0') THEN
                                                   v_next_state := FLUSH_TX;
                                                                         ELSE
                                                   v_next_state := GET_SIZE_1;
                                                END IF;
                                                                        ELSE
                                                v_next_state := GET_SIZE_0;
                                             END IF;
         WHEN GET_SIZE_1                  => IF (s_tx_fifo_empty = '0') THEN
                                                v_next_state := GET_SIZE_2;
                                                                        ELSE
                                                v_next_state := GET_SIZE_1;
                                             END IF;
         WHEN GET_SIZE_2                  => IF (s_tx_fifo_empty = '0') THEN
                                                v_next_state := GET_SIZE_3;
                                                                        ELSE
                                                v_next_state := GET_SIZE_2;
                                             END IF;
         WHEN GET_SIZE_3                  => IF (s_tx_fifo_empty = '0') THEN
                                                v_next_state := INIT_COPY;
                                                                        ELSE
                                                v_next_state := GET_SIZE_3;
                                             END IF;
         WHEN INIT_COPY                   => v_next_state := COPY_TX_DATA;
         WHEN COPY_TX_DATA                => IF (s_tx_payload_cnt_reg(32) = '1') THEN
                                                v_next_state := SIGNAL_DONE;
                                                                                 ELSE
                                                v_next_state := COPY_TX_DATA;
                                             END IF;
         WHEN FLUSH_TX                    => IF (s_tx_fifo_empty = '1') THEN
                                                v_next_state := SIGNAL_ERROR;
                                                                        ELSE
                                                v_next_state := FLUSH_TX;
                                             END IF;
         WHEN SIGNAL_AVAILABLE            => v_next_state := COPY_RX_DATA;
         WHEN COPY_RX_DATA                => IF (s_rx_push = '1' AND
                                                 pop_last = '1') THEN
                                                v_next_state := INSERT_DUMMY;
                                                                 ELSE
                                                v_next_state := COPY_RX_DATA;
                                             END IF;
         WHEN INSERT_DUMMY                => IF (s_rx_byte_cnt_reg = "00") THEN
                                                v_next_state := SIGNAL_DONE;
                                                                           ELSE
                                                v_next_state := INSERT_DUMMY;
                                             END IF;
         WHEN OTHERS                      => v_next_state := IDLE;
      END CASE;
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '1') THEN s_fifo_state_reg <= IDLE;
                          ELSE s_fifo_state_reg <= v_next_state;
         END IF;
      END IF;
   END PROCESS make_state_machine;
 
   make_tx_payload_cnt_reg : PROCESS( clock , reset , s_tx_payload_cnt_reg )
      VARIABLE v_pop_data : std_logic_vector( 7 DOWNTO 0 );
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '1') THEN s_tx_payload_cnt_reg <= (OTHERS => '1');
         ELSIF (s_tx_fifo_empty = '0' AND
                (s_fifo_state_reg = GET_SIZE_0 OR
                 s_fifo_state_reg = GET_SIZE_1 OR
                 s_fifo_state_reg = GET_SIZE_2 OR
                 s_fifo_state_reg = GET_SIZE_3)) THEN
            IF (s_tx_pop = '1') THEN v_pop_data := s_tx_pop_data;
                                ELSE v_pop_data := X"00";
            END IF;
            s_tx_payload_cnt_reg(32) <= '0';
            s_tx_payload_cnt_reg(31 DOWNTO 24) <= v_pop_data;
            s_tx_payload_cnt_reg(23 DOWNTO  0) <= s_tx_payload_cnt_reg(31 DOWNTO 8 );
         ELSIF (s_tx_pop = '1' OR
                s_fifo_state_reg = INIT_COPY) THEN
            s_tx_payload_cnt_reg <= unsigned(s_tx_payload_cnt_reg) - 1;
         END IF;
      END IF;
   END PROCESS make_tx_payload_cnt_reg;
 
   make_rx_byte_cnt_reg : PROCESS( clock , reset , s_fifo_state_reg , s_rx_push)
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '1' OR
             s_fifo_state_reg = IDLE) THEN s_rx_byte_cnt_reg <= "00";
         ELSIF (s_rx_push = '1') THEN
            s_rx_byte_cnt_reg <= unsigned(s_rx_byte_cnt_reg) + 1;
         END IF;
      END IF;
   END PROCESS make_rx_byte_cnt_reg;
 
--------------------------------------------------------------------------------
--- Here the tx-fifo is defined                                              ---
--------------------------------------------------------------------------------
   s_do_push     <= '1' WHEN s_is_my_write_burst_reg = '1' AND
                             n_data_valid_in = "00" ELSE '0';
   s_tx_pop      <= '1' WHEN s_tx_fifo_empty = '0' AND
                             (s_fifo_state_reg = FLUSH_TX OR
                              (s_tx_pop_size = '1' AND
                               (s_fifo_state_reg = GET_SIZE_0 OR
                                s_fifo_state_reg = GET_SIZE_1 OR
                                s_fifo_state_reg = GET_SIZE_2 OR
                                s_fifo_state_reg = GET_SIZE_3)) OR
                              (s_fifo_state_reg = COPY_TX_DATA AND
                               s_tx_payload_cnt_reg(32) = '0' AND
                               fifo_full = '0')) ELSE '0';
   s_rx_push     <= '1' WHEN (s_fifo_state_reg = COPY_RX_DATA AND
                              s_rx_fifo_full = '0' AND
                              pop_empty = '0') OR
                             (s_fifo_state_reg = INSERT_DUMMY AND
                              s_rx_byte_cnt_reg /= "00") ELSE '0';
   pop           <= '1' WHEN s_fifo_state_reg = COPY_RX_DATA AND
                             s_rx_push = '1' ELSE '0';
   s_pop_data    <= s_dummy_data_reg WHEN s_fifo_state_reg = INSERT_DUMMY ELSE pop_data;
   s_pop_last    <= '1' WHEN s_fifo_state_reg = INSERT_DUMMY ELSE pop_last;
   s_rx_fifo_pop <= '1' WHEN s_burst_cnt_reg(9) = '0' AND
                             (bus_address( 3 DOWNTO 0 ) = X"8" OR
                              bus_address( 3 DOWNTO 0 ) = X"9") ELSE '0';
 
   make_scpi_fifo_if : PROCESS( clock , reset )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '1' OR
             s_tx_pop = '0') THEN push      <= '0';
                                  push_size <= '0';
                                  push_data <= (OTHERS => '0');
                             ELSE
            IF (s_fifo_state_reg = FLUSH_TX) THEN push <= '0';
                                             ELSE push <= '1';
            END IF;
            push_size <= s_tx_pop_size;
            push_data <= s_tx_pop_data;
         END IF;
      END IF;
   END PROCESS make_scpi_fifo_if;
 
   make_dummy_data_reg : PROCESS( clock , reset , pop_data , pop_last ,
                                  s_rx_push )
   BEGIN
      IF (clock'event AND (clock = '1')) THEN
         IF (reset = '1') THEN s_dummy_data_reg <= X"00";
         ELSIF (s_rx_push = '1' AND
                pop_last = '1') THEN s_dummy_data_reg <= NOT(pop_data);
         END IF;
      END IF;
   END PROCESS make_dummy_data_reg;
 
   tx_fifo : fifo_4kb_16w_8r
             PORT MAP ( clock      => clock,
                        reset      => s_reset,
                        -- push port
                        push       => s_do_push,
                        push_data  => data_in,
                        push_size  => bus_address(0),
                        -- pop port
                        pop        => s_tx_pop,
                        pop_data   => s_tx_pop_data,
                        pop_size   => s_tx_pop_size,
                        -- control port
                        fifo_full  => s_tx_fifo_full,
                        fifo_empty => s_tx_fifo_empty,
                        byte_cnt   => s_tx_fifo_byte_count_value );
 
   rx_fifo : fifo_4kb_8w_16r
             PORT MAP ( clock      => clock,
                        reset      => s_reset,
                        -- push port
                        push       => s_rx_push,
                        push_data  => s_pop_data,
                        push_last  => s_pop_last,
                        -- pop port
                        pop        => s_rx_fifo_pop,
                        pop_data   => s_rx_fifo_data,
                        pop_last   => s_rx_fifo_last,
                        -- control port
                        fifo_full  => s_rx_fifo_full,
                        fifo_empty => s_rx_fifo_empty,
                        byte_cnt   => s_rx_fifo_byte_count_value );
 
 
END no_target_specific;

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[/] [gecko4/] [trunk/] [GECKO4com/] [spartan200_an/] [vhdl/] [user_fifo/] [user_fifo-behavior.vhdl] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	ktt1	`--------------------------------------------------------------------------------`
2			`-- _ _ __ ____ --`
3			`-- / / \| \| / _\| \| __\| --`
4			`-- \| \|_\| \| _ _ / / \| \|_ --`
5			`-- \| _ \| \| \| \| \| \| \| \| _\| --`
6			`-- \| \| \| \| \| \|_\| \| \ \_ \| \|__ --`
7			`-- \|_\| \|_\| \_____\| \__\| \|____\| microLab --`
8			`-- --`
9			`-- Bern University of Applied Sciences (BFH) --`
10			`-- Quellgasse 21 --`
11			`-- Room HG 4.33 --`
12			`-- 2501 Biel/Bienne --`
13			`-- Switzerland --`
14			`-- --`
15			`-- http://www.microlab.ch --`
16			`--------------------------------------------------------------------------------`
17			`-- GECKO4com`
18			`--`
19			`-- 2010/2011 Dr. Theo Kluter`
20			`--`
21			`-- This VHDL code is free code: you can redistribute it and/or modify`
22			`-- it under the terms of the GNU General Public License as published by`
23			`-- the Free Software Foundation, either version 3 of the License, or`
24			`-- (at your option) any later version.`
25			`--`
26			`-- This VHDL code is distributed in the hope that it will be useful,`
27			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
28			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
29			`-- GNU General Public License for more details.`
30			`-- You should have received a copy of the GNU General Public License`
31			`-- along with these sources. If not, see <http://www.gnu.org/licenses/>.`
32			`--`
33
34			`--memory map:`
35			`-- 0x00 -> TX-fifo write data (WO)`
36			`-- 0x01 -> TX-fifo write message size (WO)`
37			`-- 0x02 -> Nr. of bytes in TX-fifo (RO)`
38			`-- 0x03 -> Max. size in bytes of TX-fifo (RO)`
39			`-- 0x04 -> Nr. of shorts in TX-fifo (RO)`
40			`-- 0x05 -> Max. size in shorts of TX-fifo (RO)`
41			`-- 0x06 -> Nr. of words in TX-fifo (RO)`
42			`-- 0x07 -> Max. size in words of TX-fifo (RO)`
43			`-- 0x08 -> RX-fifo read data (RO)`
44			`-- 0x09 -> RX-fifo read data (RO)`
45			`-- 0x0A -> Nr. of bytes in RX-fifo (RO)`
46			`-- 0x0B -> Max. size in bytes of RX-fifo (RO)`
47			`-- 0x0C -> Nr. of shorts in RX-fifo (RO)`
48			`-- 0x0D -> Max. size in shorts of RX-fifo (RO)`
49			`-- 0x0E -> Nr. of words in RX-fifo (RO)`
50			`-- 0x0F -> Max. size in words of RX-fifo (RO)`
51
52			`ARCHITECTURE no_target_specific OF user_fifo IS`
53
54			`COMPONENT fifo_4kb_16w_8r`
55			`PORT ( clock : IN std_logic;`
56			`reset : IN std_logic;`
57			`-- push port`
58			`push : IN std_logic;`
59			`push_data : IN std_logic_vector( 15 DOWNTO 0 );`
60			`push_size : IN std_logic;`
61			`-- pop port`
62			`pop : IN std_logic;`
63			`pop_data : OUT std_logic_vector( 7 DOWNTO 0 );`
64			`pop_size : OUT std_logic;`
65			`-- control port`
66			`fifo_full : OUT std_logic;`
67			`fifo_empty : OUT std_logic;`
68			`byte_cnt : OUT std_logic_vector( 12 DOWNTO 0 ) );`
69			`END COMPONENT;`
70
71			`COMPONENT fifo_4kb_8w_16r`
72			`PORT ( clock : IN std_logic;`
73			`reset : IN std_logic;`
74			`-- push port`
75			`push : IN std_logic;`
76			`push_data : IN std_logic_vector( 7 DOWNTO 0 );`
77			`push_last : IN std_logic;`
78			`-- pop port`
79			`pop : IN std_logic;`
80			`pop_data : OUT std_logic_vector( 15 DOWNTO 0 );`
81			`pop_last : OUT std_logic_vector( 1 DOWNTO 0 );`
82			`-- control port`
83			`fifo_full : OUT std_logic;`
84			`fifo_empty : OUT std_logic;`
85			`byte_cnt : OUT std_logic_vector( 12 DOWNTO 0 ) );`
86			`END COMPONENT;`
87
88			`TYPE STATE_TYPE IS (IDLE,SIGNAL_DONE,SIGNAL_ERROR,SIGNAL_REQUEST,`
89			`GET_SIZE_0,GET_SIZE_1,GET_SIZE_2,GET_SIZE_3,`
90			`INIT_COPY,FLUSH_TX,COPY_TX_DATA,SIGNAL_MESSAGE,`
91			`COPY_RX_DATA,INSERT_DUMMY,SIGNAL_AVAILABLE);`
92
93			`SIGNAL s_tx_fifo_byte_count_value : std_logic_vector( 12 DOWNTO 0 );`
94			`SIGNAL s_n_bus_error_next : std_logic;`
95			`SIGNAL s_tx_fifo_full : std_logic;`
96			`SIGNAL s_tx_fifo_empty : std_logic;`
97			`SIGNAL s_n_bus_error_reg : std_logic;`
98			`SIGNAL s_burst_cnt_reg : std_logic_vector( 9 DOWNTO 0 );`
99			`SIGNAL s_burst_cnt_next : std_logic_vector( 9 DOWNTO 0 );`
100			`SIGNAL s_n_end_reg : std_logic;`
101			`SIGNAL s_is_my_write_burst_reg : std_logic;`
102			`SIGNAL s_do_push : std_logic;`
103
104			`SIGNAL s_fifo_state_reg : STATE_TYPE;`
105			`SIGNAL s_tx_pop : std_logic;`
106			`SIGNAL s_tx_pop_size : std_logic;`
107			`SIGNAL s_tx_pop_data : std_logic_vector( 7 DOWNTO 0 );`
108			`SIGNAL s_tx_payload_cnt_reg : std_logic_vector( 32 DOWNTO 0 );`
109
110			`SIGNAL s_rx_fifo_byte_count_value : std_logic_vector( 12 DOWNTO 0 );`
111			`SIGNAL s_rx_push : std_logic;`
112			`SIGNAL s_rx_fifo_full : std_logic;`
113			`SIGNAL s_rx_byte_cnt_reg : std_logic_vector( 1 DOWNTO 0 );`
114			`SIGNAL s_pop_data : std_logic_vector( 7 DOWNTO 0 );`
115			`SIGNAL s_pop_last : std_logic;`
116			`SIGNAL s_dummy_data_reg : std_logic_vector( 7 DOWNTO 0 );`
117			`SIGNAL s_rx_fifo_empty : std_logic;`
118			`SIGNAL s_rx_fifo_pop : std_logic;`
119			`SIGNAL s_rx_fifo_data : std_logic_vector( 15 DOWNTO 0 );`
120			`SIGNAL s_rx_fifo_last : std_logic_vector( 1 DOWNTO 0 );`
121			`SIGNAL s_reset : std_logic;`
122
123			`BEGIN`
124			`s_reset <= reset OR NOT(n_bus_reset);`
125
126			`--------------------------------------------------------------------------------`
127			`--- Here the signalling is defined ---`
128			`--------------------------------------------------------------------------------`
129			`make_error_irq : PROCESS( clock , s_do_push , s_tx_fifo_full ,`
130			`s_rx_fifo_empty , s_rx_fifo_pop )`
131			`BEGIN`
132			`IF (clock'event AND (clock = '1')) THEN`
133			`IF ((s_do_push = '1' AND`
134			`s_tx_fifo_full = '1') OR`
135			`(s_rx_fifo_empty = '1' AND`
136			`s_rx_fifo_pop = '1') OR`
137			`(s_fifo_state_reg = FLUSH_TX)) THEN error_irq <= '1';`
138			`ELSE error_irq <= '0';`
139			`END IF;`
140			`END IF;`
141			`END PROCESS make_error_irq;`
142
143			`make_data_req_irg : PROCESS( clock , reset , s_fifo_state_reg )`
144			`BEGIN`
145			`IF (clock'event AND (clock = '1')) THEN`
146			`IF (reset = '0' AND`
147			`s_fifo_state_reg = SIGNAL_REQUEST) THEN data_request_irq <= '1';`
148			`ELSE data_request_irq <= '0';`
149			`END IF;`
150			`END IF;`
151			`END PROCESS make_data_req_irg;`
152
153			`make_data_available_irq : PROCESS( clock , reset , s_fifo_state_reg )`
154			`BEGIN`
155			`IF (clock'event AND (clock = '1')) THEN`
156			`IF (reset = '0' AND`
157			`s_fifo_state_reg = SIGNAL_AVAILABLE) THEN data_available_irq <= '1';`
158			`ELSE data_available_irq <= '0';`
159			`END IF;`
160			`END IF;`
161			`END PROCESS make_data_available_irq;`
162
163			`--------------------------------------------------------------------------------`
164			`--- Here the bus handling is defined ---`
165			`--------------------------------------------------------------------------------`
166			`n_start_send <= '0' WHEN bus_address( 5 DOWNTO 4 ) = "00" AND`
167			`n_start_transmission = '0' AND`
168			`read_n_write = '0' AND`
169			`s_n_bus_error_next = '1' ELSE '1';`
170			`n_bus_error <= s_n_bus_error_reg;`
171			`n_end_transmission_out <= '0' WHEN s_n_bus_error_reg = '0' OR`
172			`s_n_end_reg = '0' ELSE '1';`
173			`make_data_valid : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg )`
174			`BEGIN`
175			`IF (clock'event AND (clock = '1')) THEN`
176			`IF (reset = '0' AND`
177			`n_bus_reset = '1' AND`
178			`s_burst_cnt_reg(9) = '0') THEN`
179			`IF (s_rx_fifo_pop = '1' AND`
180			`s_rx_fifo_last /= "00") THEN n_data_valid_out <= "01";`
181			`ELSE n_data_valid_out <= "00";`
182			`END IF;`
183			`ELSE n_data_valid_out <= "11";`
184			`END IF;`
185			`END IF;`
186			`END PROCESS make_data_valid;`
187
188			`s_n_bus_error_next <= '0' WHEN bus_address( 5 DOWNTO 4) = "00" AND`
189			`n_start_transmission = '0' AND`
190			`((bus_address(3 DOWNTO 1) = "000" AND`
191			`(read_n_write = '1' OR`
192			`s_tx_fifo_full = '1')) OR`
193			`(bus_address(3 DOWNTO 1) /= "000" AND`
194			`read_n_write = '0')) ELSE '1';`
195			`s_burst_cnt_next <= unsigned(s_burst_cnt_reg) - 1;`
196
197			`make_data_out : PROCESS( clock , bus_address , s_tx_fifo_byte_count_value )`
198			`BEGIN`
199			`IF (clock'event AND (clock = '1')) THEN`
200			`IF (bus_address(5 DOWNTO 4) = "00") THEN`
201			`CASE (bus_address( 3 DOWNTO 0 )) IS`
202			`WHEN X"2" => data_out <= "000"&s_tx_fifo_byte_count_value;`
203			`WHEN X"3" => data_out <= X"1000";`
204			`WHEN X"4" => data_out <= X"0"&s_tx_fifo_byte_count_value( 12 DOWNTO 1);`
205			`WHEN X"5" => data_out <= X"0800";`
206			`WHEN X"6" => data_out <= X"0"&"0"&s_tx_fifo_byte_count_value( 12 DOWNTO 2);`
207			`WHEN X"7" => data_out <= X"0400";`
208			`WHEN X"8" \|`
209			`X"9" => data_out <= s_rx_fifo_data;`
210			`WHEN X"A" => data_out <= "000"&s_rx_fifo_byte_count_value;`
211			`WHEN X"B" => data_out <= X"1000";`
212			`WHEN X"C" => data_out <= X"0"&s_rx_fifo_byte_count_value( 12 DOWNTO 1 );`
213			`WHEN X"D" => data_out <= X"0800";`
214			`WHEN X"E" => data_out <= X"0"&"0"&s_rx_fifo_byte_count_value( 12 DOWNTO 2 );`
215			`WHEN X"F" => data_out <= X"0400";`
216			`WHEN OTHERS => data_out <= X"0000";`
217			`END CASE;`
218			`ELSE`
219			`data_out <= X"0000";`
220			`END IF;`
221			`END IF;`
222			`END PROCESS make_data_out;`
223
224			`make_n_bus_error_reg : PROCESS( clock , s_n_bus_error_next )`
225			`BEGIN`
226			`IF (clock'event AND (clock = '1')) THEN`
227			`s_n_bus_error_reg <= s_n_bus_error_next;`
228			`END IF;`
229			`END PROCESS make_n_bus_error_reg;`
230
231			`make_n_end_reg : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg ,`
232			`s_burst_cnt_next )`
233			`BEGIN`
234			`IF (clock'event AND (clock = '1')) THEN`
235			`IF (reset = '0' AND`
236			`n_bus_reset = '1' AND`
237			`s_burst_cnt_reg(9) = '0' AND`
238			`s_burst_cnt_next(9) = '1') THEN s_n_end_reg <= '0';`
239			`ELSE s_n_end_reg <= '1';`
240			`END IF;`
241			`END IF;`
242			`END PROCESS make_n_end_reg;`
243
244			`make_burst_cnt_reg : PROCESS( clock , reset , n_bus_reset , s_burst_cnt_reg )`
245			`BEGIN`
246			`IF (clock'event AND (clock = '1')) THEN`
247			`IF (n_bus_reset = '0' OR`
248			`reset = '1') THEN s_burst_cnt_reg <= (OTHERS => '1');`
249			`ELSIF (bus_address( 5 DOWNTO 4 ) = "00" AND`
250			`n_start_transmission = '0' AND`
251			`read_n_write = '1' AND`
252			`s_n_bus_error_next = '1') THEN`
253			`s_burst_cnt_reg <= "0"&burst_size;`
254			`ELSIF (s_burst_cnt_reg(9) = '0') THEN`
255			`s_burst_cnt_reg <= s_burst_cnt_next;`
256			`END IF;`
257			`END IF;`
258			`END PROCESS make_burst_cnt_reg;`
259
260			`make_is_my_write_burst_reg : PROCESS( clock , reset , n_bus_reset )`
261			`BEGIN`
262			`IF (clock'event AND (clock = '1')) THEN`
263			`IF (reset = '1' OR`
264			`n_bus_reset = '0' OR`
265			`n_end_transmission_in = '0') THEN s_is_my_write_burst_reg <= '0';`
266			`ELSIF (bus_address( 5 DOWNTO 4 ) = "00" AND`
267			`n_start_transmission = '0' AND`
268			`read_n_write = '0' AND`
269			`s_n_bus_error_next = '1') THEN s_is_my_write_burst_reg <= '1';`
270			`END IF;`
271			`END IF;`
272			`END PROCESS make_is_my_write_burst_reg;`
273
274			`--------------------------------------------------------------------------------`
275			`--- Here the usbtmc interface is defined ---`
276			`--------------------------------------------------------------------------------`
277			`command_done <= '1' WHEN s_fifo_state_reg = SIGNAL_DONE OR`
278			`s_fifo_state_reg = SIGNAL_ERROR ELSE '0';`
279			`command_error <= '1' WHEN s_fifo_state_reg = SIGNAL_ERROR ELSE '0';`
280			`message_available <= '1' WHEN s_fifo_state_reg = SIGNAL_MESSAGE ELSE '0';`
281
282			`make_state_machine : PROCESS( clock , reset , s_fifo_state_reg )`
283			`VARIABLE v_next_state : STATE_TYPE;`
284			`BEGIN`
285			`CASE (s_fifo_state_reg) IS`
286			`WHEN IDLE => IF (start_command = '1' AND`
287			`command_id = "0011100") THEN`
288			`v_next_state := SIGNAL_REQUEST;`
289			`ELSIF ((start_command = '1' AND`
290			`command_id = "0011011") OR`
291			`(transparent_mode = '1' AND`
292			`pop_empty = '0')) THEN`
293			`v_next_state := SIGNAL_AVAILABLE;`
294			`ELSIF (transparent_mode = '1' AND`
295			`s_tx_fifo_empty = '0') THEN`
296			`v_next_state := SIGNAL_MESSAGE;`
297			`ELSE`
298			`v_next_state := IDLE;`
299			`END IF;`
300			`WHEN SIGNAL_REQUEST \|`
301			`SIGNAL_MESSAGE => v_next_state := GET_SIZE_0;`
302			`WHEN GET_SIZE_0 => IF (s_tx_fifo_empty = '0') THEN`
303			`IF (s_tx_pop_size = '0') THEN`
304			`v_next_state := FLUSH_TX;`
305			`ELSE`
306			`v_next_state := GET_SIZE_1;`
307			`END IF;`
308			`ELSE`
309			`v_next_state := GET_SIZE_0;`
310			`END IF;`
311			`WHEN GET_SIZE_1 => IF (s_tx_fifo_empty = '0') THEN`
312			`v_next_state := GET_SIZE_2;`
313			`ELSE`
314			`v_next_state := GET_SIZE_1;`
315			`END IF;`
316			`WHEN GET_SIZE_2 => IF (s_tx_fifo_empty = '0') THEN`
317			`v_next_state := GET_SIZE_3;`
318			`ELSE`
319			`v_next_state := GET_SIZE_2;`
320			`END IF;`
321			`WHEN GET_SIZE_3 => IF (s_tx_fifo_empty = '0') THEN`
322			`v_next_state := INIT_COPY;`
323			`ELSE`
324			`v_next_state := GET_SIZE_3;`
325			`END IF;`
326			`WHEN INIT_COPY => v_next_state := COPY_TX_DATA;`
327			`WHEN COPY_TX_DATA => IF (s_tx_payload_cnt_reg(32) = '1') THEN`
328			`v_next_state := SIGNAL_DONE;`
329			`ELSE`
330			`v_next_state := COPY_TX_DATA;`
331			`END IF;`
332			`WHEN FLUSH_TX => IF (s_tx_fifo_empty = '1') THEN`
333			`v_next_state := SIGNAL_ERROR;`
334			`ELSE`
335			`v_next_state := FLUSH_TX;`
336			`END IF;`
337			`WHEN SIGNAL_AVAILABLE => v_next_state := COPY_RX_DATA;`
338			`WHEN COPY_RX_DATA => IF (s_rx_push = '1' AND`
339			`pop_last = '1') THEN`
340			`v_next_state := INSERT_DUMMY;`
341			`ELSE`
342			`v_next_state := COPY_RX_DATA;`
343			`END IF;`
344			`WHEN INSERT_DUMMY => IF (s_rx_byte_cnt_reg = "00") THEN`
345			`v_next_state := SIGNAL_DONE;`
346			`ELSE`
347			`v_next_state := INSERT_DUMMY;`
348			`END IF;`
349			`WHEN OTHERS => v_next_state := IDLE;`
350			`END CASE;`
351			`IF (clock'event AND (clock = '1')) THEN`
352			`IF (reset = '1') THEN s_fifo_state_reg <= IDLE;`
353			`ELSE s_fifo_state_reg <= v_next_state;`
354			`END IF;`
355			`END IF;`
356			`END PROCESS make_state_machine;`
357
358			`make_tx_payload_cnt_reg : PROCESS( clock , reset , s_tx_payload_cnt_reg )`
359			`VARIABLE v_pop_data : std_logic_vector( 7 DOWNTO 0 );`
360			`BEGIN`
361			`IF (clock'event AND (clock = '1')) THEN`
362			`IF (reset = '1') THEN s_tx_payload_cnt_reg <= (OTHERS => '1');`
363			`ELSIF (s_tx_fifo_empty = '0' AND`
364			`(s_fifo_state_reg = GET_SIZE_0 OR`
365			`s_fifo_state_reg = GET_SIZE_1 OR`
366			`s_fifo_state_reg = GET_SIZE_2 OR`
367			`s_fifo_state_reg = GET_SIZE_3)) THEN`
368			`IF (s_tx_pop = '1') THEN v_pop_data := s_tx_pop_data;`
369			`ELSE v_pop_data := X"00";`
370			`END IF;`
371			`s_tx_payload_cnt_reg(32) <= '0';`
372			`s_tx_payload_cnt_reg(31 DOWNTO 24) <= v_pop_data;`
373			`s_tx_payload_cnt_reg(23 DOWNTO 0) <= s_tx_payload_cnt_reg(31 DOWNTO 8 );`
374			`ELSIF (s_tx_pop = '1' OR`
375			`s_fifo_state_reg = INIT_COPY) THEN`
376			`s_tx_payload_cnt_reg <= unsigned(s_tx_payload_cnt_reg) - 1;`
377			`END IF;`
378			`END IF;`
379			`END PROCESS make_tx_payload_cnt_reg;`
380
381			`make_rx_byte_cnt_reg : PROCESS( clock , reset , s_fifo_state_reg , s_rx_push)`
382			`BEGIN`
383			`IF (clock'event AND (clock = '1')) THEN`
384			`IF (reset = '1' OR`
385			`s_fifo_state_reg = IDLE) THEN s_rx_byte_cnt_reg <= "00";`
386			`ELSIF (s_rx_push = '1') THEN`
387			`s_rx_byte_cnt_reg <= unsigned(s_rx_byte_cnt_reg) + 1;`
388			`END IF;`
389			`END IF;`
390			`END PROCESS make_rx_byte_cnt_reg;`
391
392			`--------------------------------------------------------------------------------`
393			`--- Here the tx-fifo is defined ---`
394			`--------------------------------------------------------------------------------`
395			`s_do_push <= '1' WHEN s_is_my_write_burst_reg = '1' AND`
396			`n_data_valid_in = "00" ELSE '0';`
397			`s_tx_pop <= '1' WHEN s_tx_fifo_empty = '0' AND`
398			`(s_fifo_state_reg = FLUSH_TX OR`
399			`(s_tx_pop_size = '1' AND`
400			`(s_fifo_state_reg = GET_SIZE_0 OR`
401			`s_fifo_state_reg = GET_SIZE_1 OR`
402			`s_fifo_state_reg = GET_SIZE_2 OR`
403			`s_fifo_state_reg = GET_SIZE_3)) OR`
404			`(s_fifo_state_reg = COPY_TX_DATA AND`
405			`s_tx_payload_cnt_reg(32) = '0' AND`
406			`fifo_full = '0')) ELSE '0';`
407			`s_rx_push <= '1' WHEN (s_fifo_state_reg = COPY_RX_DATA AND`
408			`s_rx_fifo_full = '0' AND`
409			`pop_empty = '0') OR`
410			`(s_fifo_state_reg = INSERT_DUMMY AND`
411			`s_rx_byte_cnt_reg /= "00") ELSE '0';`
412			`pop <= '1' WHEN s_fifo_state_reg = COPY_RX_DATA AND`
413			`s_rx_push = '1' ELSE '0';`
414			`s_pop_data <= s_dummy_data_reg WHEN s_fifo_state_reg = INSERT_DUMMY ELSE pop_data;`
415			`s_pop_last <= '1' WHEN s_fifo_state_reg = INSERT_DUMMY ELSE pop_last;`
416			`s_rx_fifo_pop <= '1' WHEN s_burst_cnt_reg(9) = '0' AND`
417			`(bus_address( 3 DOWNTO 0 ) = X"8" OR`
418			`bus_address( 3 DOWNTO 0 ) = X"9") ELSE '0';`
419
420			`make_scpi_fifo_if : PROCESS( clock , reset )`
421			`BEGIN`
422			`IF (clock'event AND (clock = '1')) THEN`
423			`IF (reset = '1' OR`
424			`s_tx_pop = '0') THEN push <= '0';`
425			`push_size <= '0';`
426			`push_data <= (OTHERS => '0');`
427			`ELSE`
428			`IF (s_fifo_state_reg = FLUSH_TX) THEN push <= '0';`
429			`ELSE push <= '1';`
430			`END IF;`
431			`push_size <= s_tx_pop_size;`
432			`push_data <= s_tx_pop_data;`
433			`END IF;`
434			`END IF;`
435			`END PROCESS make_scpi_fifo_if;`
436
437			`make_dummy_data_reg : PROCESS( clock , reset , pop_data , pop_last ,`
438			`s_rx_push )`
439			`BEGIN`
440			`IF (clock'event AND (clock = '1')) THEN`
441			`IF (reset = '1') THEN s_dummy_data_reg <= X"00";`
442			`ELSIF (s_rx_push = '1' AND`
443			`pop_last = '1') THEN s_dummy_data_reg <= NOT(pop_data);`
444			`END IF;`
445			`END IF;`
446			`END PROCESS make_dummy_data_reg;`
447
448			`tx_fifo : fifo_4kb_16w_8r`
449			`PORT MAP ( clock => clock,`
450			`reset => s_reset,`
451			`-- push port`
452			`push => s_do_push,`
453			`push_data => data_in,`
454			`push_size => bus_address(0),`
455			`-- pop port`
456			`pop => s_tx_pop,`
457			`pop_data => s_tx_pop_data,`
458			`pop_size => s_tx_pop_size,`
459			`-- control port`
460			`fifo_full => s_tx_fifo_full,`
461			`fifo_empty => s_tx_fifo_empty,`
462			`byte_cnt => s_tx_fifo_byte_count_value );`
463
464			`rx_fifo : fifo_4kb_8w_16r`
465			`PORT MAP ( clock => clock,`
466			`reset => s_reset,`
467			`-- push port`
468			`push => s_rx_push,`
469			`push_data => s_pop_data,`
470			`push_last => s_pop_last,`
471			`-- pop port`
472			`pop => s_rx_fifo_pop,`
473			`pop_data => s_rx_fifo_data,`
474			`pop_last => s_rx_fifo_last,`
475			`-- control port`
476			`fifo_full => s_rx_fifo_full,`
477			`fifo_empty => s_rx_fifo_empty,`
478			`byte_cnt => s_rx_fifo_byte_count_value );`
479
480
481			`END no_target_specific;`