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[/] [gecko4/] [trunk/] [GECKO4com/] [spartan200_an/] [vhdl/] [vga/] [vga_controller-behavior-xilinx.vhdl] - Blame information for rev 5

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1 5 ktt1 
--------------------------------------------------------------------------------
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--            _   _            __   ____                                      --
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--           / / | |          / _| |  __|                                     --
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--           | |_| |  _   _  / /   | |_                                       --
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--           |  _  | | | | | | |   |  _|                                      --
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--           | | | | | |_| | \ \_  | |__                                      --
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--           |_| |_| \_____|  \__| |____| microLab                            --
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--                                                                            --
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--           Bern University of Applied Sciences (BFH)                        --
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--           Quellgasse 21                                                    --
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--           Room HG 4.33                                                     --
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--           2501 Biel/Bienne                                                 --
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--           Switzerland                                                      --
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--                                                                            --
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--           http://www.microlab.ch                                           --
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--------------------------------------------------------------------------------
17 
--   GECKO4com
18 
--
19 
--   2010/2011 Dr. Theo Kluter
20 
--
21 
--   This VHDL code is free code: you can redistribute it and/or modify
22 
--   it under the terms of the GNU General Public License as published by
23 
--   the Free Software Foundation, either version 3 of the License, or
24 
--   (at your option) any later version.
25 
--
26 
--   This VHDL code is distributed in the hope that it will be useful,
27 
--   but WITHOUT ANY WARRANTY; without even the implied warranty of
28 
--   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
29 
--   GNU General Public License for more details.
30 
--   You should have received a copy of the GNU General Public License
31 
--   along with these sources.  If not, see <http://www.gnu.org/licenses/>.
32 
--
33 
 
34 
LIBRARY unisim;
35 
USE unisim.all;
36 
 
37 
ARCHITECTURE xilinx OF vga_controller IS
38 
 
39 
   COMPONENT FDC
40 
      GENERIC ( INIT : bit );
41 
      PORT ( Q   : OUT std_logic;
42 
             C   : IN  std_logic;
43 
             CLR : IN  std_logic;
44 
             D   : IN  std_logic );
45 
   END COMPONENT;
46 
 
47 
   COMPONENT DFF
48 
      PORT ( clock  : IN  std_logic;
49 
             D      : IN  std_logic;
50 
             Q      : OUT std_logic );
51 
   END COMPONENT;
52 
 
53 
   COMPONENT DFF_BUS
54 
      GENERIC ( nr_of_bits : INTEGER );
55 
      PORT ( clock  : IN  std_logic;
56 
             D      : IN  std_logic_vector( (nr_of_bits-1) DOWNTO 0 );
57 
             Q      : OUT std_logic_vector( (nr_of_bits-1) DOWNTO 0 ));
58 
   END COMPONENT;
59 
 
60 
   COMPONENT RAMB16_S9_S9
61 
      PORT ( DOA   : OUT std_logic_vector( 7 DOWNTO 0 );
62 
             DOPA  : OUT std_logic_vector( 0 DOWNTO 0 );
63 
             ADDRA : IN  std_logic_vector(10 DOWNTO 0 );
64 
             CLKA  : IN  std_logic;
65 
             DIA   : IN  std_logic_vector( 7 DOWNTO 0 );
66 
             DIPA  : IN  std_logic_vector( 0 DOWNTO 0 );
67 
             ENA   : IN  std_logic;
68 
             SSRA  : IN  std_logic;
69 
             WEA   : IN  std_logic;
70 
             DOB   : OUT std_logic_vector( 7 DOWNTO 0 );
71 
             DOPB  : OUT std_logic_vector( 0 DOWNTO 0 );
72 
             ADDRB : IN  std_logic_vector(10 DOWNTO 0 );
73 
             CLKB  : IN  std_logic;
74 
             DIB   : IN  std_logic_vector( 7 DOWNTO 0 );
75 
             DIPB  : IN  std_logic_vector( 0 DOWNTO 0 );
76 
             ENB   : IN  std_logic;
77 
             SSRB  : IN  std_logic;
78 
             WEB   : IN  std_logic);
79 
   END COMPONENT;
80 
 
81 
   COMPONENT RAMB16_S1
82 
      PORT ( DO   : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
83 
             ADDR : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
84 
             CLK  : IN STD_ULOGIC;
85 
             DI   : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
86 
             EN   : IN STD_ULOGIC;
87 
             SSR  : IN STD_ULOGIC;
88 
             WE   : IN STD_ULOGIC );
89 
   END COMPONENT;
90 
 
91 
   TYPE HCOUNT_TYPE IS ( HORIZONTAL_FRONT_PORCH , HORIZONTAL_SYNC , HORIZONTAL_BACK_PORCH , HORIZONTAL_PIXELS );
92 
   TYPE VCOUNT_TYPE IS ( VERTICAL_FRONT_PORCH , VERTICAL_SYNC , VERTICAL_BACK_PORCH , VERTICAL_ACTIVE );
93 
   TYPE USBTMC_STATE_TYPE IS (IDLE,INIT_CLEAR_SCREEN,CLEAR_SCREEN,SIGNAL_DONE,
94 
                              GET_BG_COLOR,SET_BG_COLOR,SIGNAL_ERROR,
95 
                              GET_FG_COLOR,SET_FG_COLOR,WRITE_CHAR,NEW_LINE,
96 
                              INIT_CLEAR_LINE,CLEAR_LINE,CLEAR_NOP,
97 
                              INIT_CURSOR_SEND,SEND_CURSOR,INIT_GET_CURSOR,
98 
                              GET_X_CHAR,MULT_10_X,GET_Y_CHAR,MULT_10_Y,
99 
                              UPDATE_CURSOR);
100 
 
101 
   CONSTANT H_FRONT_PORCH_COUNT       : std_logic_vector( 9 DOWNTO 0 ) := "0000010111";
102 
   CONSTANT H_SYNC_COUNT              : std_logic_vector( 9 DOWNTO 0 ) := "0010000111";
103 
   CONSTANT H_BACK_PORCH_COUNT        : std_logic_vector( 9 DOWNTO 0 ) := "0010001111";
104 
   CONSTANT H_PIXEL_COUNT             : std_logic_vector( 9 DOWNTO 0 ) := "1111111111";
105 
   CONSTANT V_FRONT_PORCH_COUNT       : std_logic_vector( 9 DOWNTO 0 ) := "0000000010";
106 
   CONSTANT V_SYNC_COUNT              : std_logic_vector( 9 DOWNTO 0 ) := "0000000101";
107 
   CONSTANT V_BACK_PORCH_COUNT        : std_logic_vector( 9 DOWNTO 0 ) := "0000011100";
108 
   CONSTANT V_ACTIVE_COUNT            : std_logic_vector( 9 DOWNTO 0 ) := "1011111111";
109 
   CONSTANT HIGH_RELOAD               : std_logic_vector(12 DOWNTO 0 ) := "1"&X"D4B"; --(=7499)
110 
   CONSTANT LOW_RELOAD                : std_logic_vector(12 DOWNTO 0 ) := "1"&X"387"; --(=4999)
111 
   CONSTANT c_ten                     : std_logic_vector( 4 DOWNTO 0 ) := "01010";
112 
   CONSTANT c_31                      : std_logic_vector( 6 DOWNTO 0 ) := "0011111";
113 
 
114 
   SIGNAL s_horiz_count_reg           : std_logic_vector( 9 DOWNTO 0 );
115 
   SIGNAL s_horiz_load_value          : std_logic_vector( 9 DOWNTO 0 );
116 
   SIGNAL s_horiz_count_is_zero       : std_logic;
117 
   SIGNAL s_horiz_state_reg           : HCOUNT_TYPE;
118 
   SIGNAL s_next_line                 : std_logic;
119 
   SIGNAL s_next_line_reg             : std_logic;
120 
   SIGNAL s_vert_count_reg            : std_logic_vector( 9 DOWNTO 0 );
121 
   SIGNAL s_vert_load_value           : std_logic_vector( 9 DOWNTO 0 );
122 
   SIGNAL s_vert_count_is_zero        : std_logic;
123 
   SIGNAL s_vert_state_reg            : VCOUNT_TYPE;
124 
   SIGNAL s_vsync                     : std_logic;
125 
   SIGNAL s_hsync                     : std_logic;
126 
   SIGNAL s_n_blank                   : std_logic;
127 
   SIGNAL s_red                       : std_logic;
128 
   SIGNAL s_green                     : std_logic;
129 
   SIGNAL s_blue                      : std_logic;
130 
   SIGNAL s_new_screen                : std_logic;
131 
   SIGNAL s_new_screen_reg            : std_logic;
132 
   SIGNAL s_req_line                  : std_logic;
133 
   SIGNAL s_req_line_reg              : std_logic;
134 
   SIGNAL s_line_counter_reg          : std_logic_vector( 9 DOWNTO 0 );
135 
   SIGNAL s_lookup_address            : std_logic_vector(10 DOWNTO 0 );
136 
   SIGNAL s_is_fpga_cursor_pos        : std_logic;
137 
   SIGNAL s_fpga_lookup_address       : std_logic_vector(10 DOWNTO 0 );
138 
   SIGNAL s_usbtmc_lookup_address     : std_logic_vector(10 DOWNTO 0 );
139 
 
140 
   SIGNAL s_ascii_data_1              : std_logic_vector( 7 DOWNTO 0 );
141 
   SIGNAL s_ascii_data_2              : std_logic_vector( 7 DOWNTO 0 );
142 
   SIGNAL s_ascii_data_3              : std_logic_vector( 7 DOWNTO 0 );
143 
 
144 
   SIGNAL s_stage_1_data_sel_reg      : std_logic_vector( 1 DOWNTO 0 );
145 
   SIGNAL s_stage_1_line_index_reg    : std_logic_vector( 3 DOWNTO 0 );
146 
   SIGNAL s_stage_1_pixel_index_reg   : std_logic_vector( 2 DOWNTO 0 );
147 
   SIGNAL s_stage_1_fg_color_reg      : std_logic_vector( 2 DOWNTO 0 );
148 
   SIGNAL s_stage_1_bg_color_reg      : std_logic_vector( 2 DOWNTO 0 );
149 
   SIGNAL s_stage_1_hsync_reg         : std_logic;
150 
   SIGNAL s_stage_1_vsync_reg         : std_logic;
151 
   SIGNAL s_stage_1_n_blank_reg       : std_logic;
152 
   SIGNAL s_stage_1_cursor_reg        : std_logic;
153 
   SIGNAL s_stage_1_draw_line_reg     : std_logic;
154 
 
155 
   SIGNAL s_stage_1_ascii_data        : std_logic_vector( 7 DOWNTO 0 );
156 
   SIGNAL s_rom_index                 : std_logic_vector(13 DOWNTO 0 );
157 
   SIGNAL s_rom_value_0               : std_logic_vector( 0 DOWNTO 0 );
158 
 
159 
   SIGNAL s_stage_2_fg_color_reg      : std_logic_vector( 2 DOWNTO 0 );
160 
   SIGNAL s_stage_2_bg_color_reg      : std_logic_vector( 2 DOWNTO 0 );
161 
   SIGNAL s_stage_2_hsync_reg         : std_logic;
162 
   SIGNAL s_stage_2_vsync_reg         : std_logic;
163 
   SIGNAL s_stage_2_n_blank_reg       : std_logic;
164 
   SIGNAL s_stage_2_cursor_reg        : std_logic;
165 
   SIGNAL s_stage_2_pixel_inv_reg     : std_logic;
166 
 
167 
   SIGNAL s_stage_2_pixel_set         : std_logic;
168 
 
169 
   SIGNAL s_stage_1_counter_reg       : std_logic_vector( 12 DOWNTO 0 );
170 
   SIGNAL s_stage_1_counter_next      : std_logic_vector( 12 DOWNTO 0 );
171 
   SIGNAL s_stage_1_counter_zero      : std_logic;
172 
   SIGNAL s_stage_1_counter_tick_reg  : std_logic;
173 
   SIGNAL s_stage_1_counter_tick_next : std_logic;
174 
   SIGNAL s_stage_2_counter_reg       : std_logic_vector( 12 DOWNTO 0 );
175 
   SIGNAL s_stage_2_counter_next      : std_logic_vector( 12 DOWNTO 0 );
176 
   SIGNAL s_stage_2_counter_zero      : std_logic;
177 
   SIGNAL s_stage_2_counter_tick_reg  : std_logic;
178 
   SIGNAL s_stage_2_counter_tick_next : std_logic;
179 
   SIGNAL s_blink_reg                 : std_logic;
180 
   SIGNAL s_blink_next                : std_logic;
181 
   SIGNAL s_draw_hor_line             : std_logic;
182 
 
183 
   SIGNAL s_usbtmc_screen_offset_reg  : std_logic_vector( 4 DOWNTO 0 );
184 
   SIGNAL s_usbtmc_cursor_x_reg       : std_logic_vector( 5 DOWNTO 0 );
185 
   SIGNAL s_usbtmc_cursor_y_reg       : std_logic_vector( 4 DOWNTO 0 );
186 
   SIGNAL s_usbtmc_cursor_x_bcd_reg   : std_logic_vector( 6 DOWNTO 0 );
187 
   SIGNAL s_usbtmc_cursor_y_bcd_reg   : std_logic_vector( 5 DOWNTO 0 );
188 
   SIGNAL s_usbtmc_fg_color_reg       : std_logic_vector( 2 DOWNTO 0 );
189 
   SIGNAL s_usbtmc_bg_color_reg       : std_logic_vector( 2 DOWNTO 0 );
190 
   SIGNAL s_is_usbtmc_cursor          : std_logic;
191 
   SIGNAL s_usbtmc_write_address      : std_logic_vector(10 DOWNTO 0 );
192 
   SIGNAL s_usbtmc_write_data         : std_logic_vector( 7 DOWNTO 0 );
193 
   SIGNAL s_usbtmc_write_enable       : std_logic;
194 
   SIGNAL s_usbtmc_state_reg          : USBTMC_STATE_TYPE;
195 
   SIGNAL s_clear_counter_reg         : std_logic_vector(11 DOWNTO 0 );
196 
   SIGNAL s_pop_data                  : std_logic;
197 
   SIGNAL s_pop_data_reg              : std_logic_vector( 7 DOWNTO 0 );
198 
   SIGNAL s_next_cursor_xpos          : std_logic_vector( 6 DOWNTO 0 );
199 
   SIGNAL s_next_cursor_ypos          : std_logic_vector( 5 DOWNTO 0 );
200 
   SIGNAL s_valid_char                : std_logic;
201 
   SIGNAL s_last_char_reg             : std_logic;
202 
   SIGNAL s_push_cnt_reg              : std_logic_vector( 3 DOWNTO 0 );
203 
   SIGNAL s_push                      : std_logic;
204 
   SIGNAL s_new_cursor_x_pos_reg      : std_logic_vector( 5 DOWNTO 0 );
205 
   SIGNAL s_new_cursor_y_pos_reg      : std_logic_vector( 4 DOWNTO 0 );
206 
 
207 
BEGIN
208 
 
209 
-- Assign control signals
210 
   s_horiz_count_is_zero     <= '1' WHEN s_horiz_count_reg = "0000000000" ELSE '0';
211 
   s_vert_count_is_zero      <= '1' WHEN s_vert_count_reg = "0000000000" ELSE '0';
212 
   s_next_line               <= '1' WHEN s_horiz_count_is_zero = '1' AND
213 
                                         s_horiz_state_reg = HORIZONTAL_PIXELS ELSE '0';
214 
   s_n_blank                 <= '1' WHEN s_horiz_state_reg = HORIZONTAL_PIXELS AND
215 
                                         s_vert_state_reg = VERTICAL_ACTIVE ELSE '0';
216 
   s_red                     <= '0' WHEN s_stage_2_n_blank_reg = '0' ELSE
217 
                                s_stage_2_fg_color_reg(2) WHEN s_stage_2_pixel_set = '1' ELSE
218 
                                s_stage_2_bg_color_reg(2);
219 
   s_green                   <= '0' WHEN s_stage_2_n_blank_reg = '0' ELSE
220 
                                s_stage_2_fg_color_reg(1) WHEN s_stage_2_pixel_set = '1' ELSE
221 
                                s_stage_2_bg_color_reg(1);
222 
   s_blue                    <= '0' WHEN s_stage_2_n_blank_reg = '0' ELSE
223 
                                s_stage_2_fg_color_reg(0) WHEN s_stage_2_pixel_set = '1' ELSE
224 
                                s_stage_2_bg_color_reg(0);
225 
   s_new_screen              <= '1' WHEN s_horiz_count_is_zero = '1' AND
226 
                                         s_vert_count_is_zero = '1' AND
227 
                                         s_horiz_state_reg = HORIZONTAL_PIXELS AND
228 
                                         s_vert_state_reg = VERTICAL_FRONT_PORCH ELSE '0';
229 
   s_req_line                <= '1' WHEN (s_horiz_count_is_zero = '1' AND
230 
                                          s_horiz_state_reg = HORIZONTAL_PIXELS AND
231 
                                          s_vert_state_reg = VERTICAL_ACTIVE) ELSE '0';
232 
   s_lookup_address          <= s_line_counter_reg(7 DOWNTO 4)&NOT(s_horiz_count_reg(9 DOWNTO 3));
233 
   s_fpga_lookup_address( 5 DOWNTO 0 ) <= NOT(s_horiz_count_reg(8 DOWNTO 3));
234 
   s_fpga_lookup_address(10 DOWNTO 6 ) <= unsigned(screen_offset)+
235 
                                          unsigned(s_line_counter_reg(9)&
236 
                                                   s_line_counter_reg(7 DOWNTO 4));
237 
   s_usbtmc_lookup_address( 5 DOWNTO 0 ) <= NOT(s_horiz_count_reg(8 DOWNTO 3));
238 
   s_usbtmc_lookup_address(10 DOWNTO 6 ) <= unsigned(s_usbtmc_screen_offset_reg)+
239 
                                            unsigned(s_line_counter_reg(9)&
240 
                                                     s_line_counter_reg(7 DOWNTO 4));
241 
   s_hsync                   <= '1' WHEN s_horiz_state_reg = HORIZONTAL_SYNC ELSE '0';
242 
   s_vsync                   <= '1' WHEN s_vert_state_reg = VERTICAL_SYNC ELSE '0';
243 
   s_is_fpga_cursor_pos      <= '1' WHEN cursor_pos(10 DOWNTO 6) = s_line_counter_reg(9)&s_line_counter_reg(7 DOWNTO 4) AND
244 
                                         cursor_pos( 5 DOWNTO 0) = NOT(s_horiz_count_reg( 8 DOWNTO 3)) ELSE '0';
245 
   s_is_usbtmc_cursor        <= '1' WHEN s_usbtmc_cursor_y_reg = s_line_counter_reg(9)&s_line_counter_reg(7 DOWNTO 4) AND
246 
                                         s_usbtmc_cursor_x_reg = NOT(s_horiz_count_reg( 8 DOWNTO 3)) ELSE '0';
247 
   s_draw_hor_line           <= '1' WHEN s_horiz_count_reg(8 DOWNTO 0) = "0"&X"00" OR
248 
                                         s_horiz_count_reg(8 DOWNTO 0) = "1"&X"FF" ELSE '0';
249 
   s_rom_index(13 DOWNTO 7 ) <= s_stage_1_ascii_data( 6 DOWNTO 0 );
250 
   s_rom_index( 6 DOWNTO 3 ) <= s_stage_1_line_index_reg;
251 
   s_rom_index( 2 DOWNTO 0 ) <= s_stage_1_pixel_index_reg;
252 
   s_stage_2_pixel_set       <= (s_rom_value_0(0) XOR s_stage_2_cursor_reg) XOR s_stage_2_pixel_inv_reg;
253 
   s_stage_1_counter_zero    <= '1' WHEN s_stage_1_counter_reg = "0"&X"000" ELSE '0';
254 
   s_stage_2_counter_zero    <= s_stage_1_counter_tick_reg WHEN s_stage_2_counter_reg = "0"&X"000" ELSE '0';
255 
 
256 
-- Here the update logic is defined
257 
   s_stage_1_counter_next      <= HIGH_RELOAD WHEN s_stage_1_counter_zero = '1' OR
258 
                                                   vga_off = '1' ELSE
259 
                                  unsigned(s_stage_1_counter_reg) - 1;
260 
   s_stage_1_counter_tick_next <= s_stage_1_counter_zero OR vga_off;
261 
   s_stage_2_counter_next      <= LOW_RELOAD WHEN s_stage_2_counter_zero = '1' OR
262 
                                                  vga_off = '1' ELSE
263 
                                  unsigned(s_stage_2_counter_reg) - 1 WHEN s_stage_1_counter_tick_reg = '1' ELSE
264 
                                  s_stage_2_counter_reg;
265 
   s_stage_2_counter_tick_next <= s_stage_2_counter_zero OR vga_off;
266 
   s_blink_next                <= '0' WHEN vga_off = '1' ELSE
267 
                                  NOT(s_blink_reg) WHEN s_stage_2_counter_tick_reg = '1' ELSE s_blink_reg;
268 
 
269 
-- Here the flipflops are instantiated
270 
   stage_1_counter_reg : DFF_BUS
271 
                         GENERIC MAP ( nr_of_bits => 13 )
272 
                         PORT MAP ( clock => clock_75MHz,
273 
                                    D     => s_stage_1_counter_next,
274 
                                    Q     => s_stage_1_counter_reg );
275 
   stage_1_counter_tick_reg : DFF
276 
                              PORT MAP ( clock => clock_75MHz,
277 
                                         D     => s_stage_1_counter_tick_next,
278 
                                         Q     => s_stage_1_counter_tick_reg );
279 
   stage_2_counter_reg : DFF_BUS
280 
                         GENERIC MAP ( nr_of_bits => 13 )
281 
                         PORT MAP ( clock => clock_75MHz,
282 
                                    D     => s_stage_2_counter_next,
283 
                                    Q     => s_stage_2_counter_reg );
284 
   stage_2_counter_tick_reg : DFF
285 
                              PORT MAP ( clock => clock_75MHz,
286 
                                         D     => s_stage_2_counter_tick_next,
287 
                                         Q     => s_stage_2_counter_tick_reg );
288 
   blink_reg : DFF
289 
               PORT MAP ( clock => clock_75MHz,
290 
                          D     => s_blink_next,
291 
                          Q     => s_blink_reg );
292 
 
293 
-- Map processes
294 
 
295 
   make_horiz_count_reg : PROCESS( clock_75MHz , vga_off ,
296 
                                   s_horiz_count_is_zero , s_horiz_load_value )
297 
   BEGIN
298 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
299 
         IF (vga_off = '1') THEN s_horiz_count_reg <= H_FRONT_PORCH_COUNT;
300 
         ELSIF (s_horiz_count_is_zero = '1') THEN
301 
               s_horiz_count_reg <= s_horiz_load_value;
302 
                                             ELSE
303 
               s_horiz_count_reg <= unsigned( s_horiz_count_reg ) - 1;
304 
         END IF;
305 
      END IF;
306 
   END PROCESS make_horiz_count_reg;
307 
 
308 
   make_horiz_load_value : PROCESS( s_horiz_state_reg )
309 
   BEGIN
310 
      CASE (s_horiz_state_reg) IS
311 
         WHEN HORIZONTAL_FRONT_PORCH => s_horiz_load_value <= H_SYNC_COUNT;
312 
         WHEN HORIZONTAL_SYNC        => s_horiz_load_value <= H_BACK_PORCH_COUNT;
313 
         WHEN HORIZONTAL_BACK_PORCH  => s_horiz_load_value <= H_PIXEL_COUNT;
314 
         WHEN OTHERS                 => s_horiz_load_value <= H_FRONT_PORCH_COUNT;
315 
      END CASE;
316 
   END PROCESS make_horiz_load_value;
317 
 
318 
   make_horiz_state_reg : PROCESS( clock_75MHz , s_horiz_state_reg ,
319 
                                   vga_off , s_horiz_count_is_zero )
320 
      VARIABLE v_next_state : HCOUNT_TYPE;
321 
   BEGIN
322 
      CASE (s_horiz_state_reg) IS
323 
         WHEN HORIZONTAL_FRONT_PORCH => v_next_state := HORIZONTAL_SYNC;
324 
         WHEN HORIZONTAL_SYNC        => v_next_state := HORIZONTAL_BACK_PORCH;
325 
         WHEN HORIZONTAL_BACK_PORCH  => v_next_state := HORIZONTAL_PIXELS;
326 
         WHEN OTHERS                 => v_next_state := HORIZONTAL_FRONT_PORCH;
327 
      END CASE;
328 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
329 
         IF (vga_off = '1') THEN s_horiz_state_reg <= HORIZONTAL_FRONT_PORCH;
330 
         ELSIF (s_horiz_count_is_zero = '1') THEN s_horiz_state_reg <= v_next_state;
331 
         END IF;
332 
      END IF;
333 
   END PROCESS make_horiz_state_reg;
334 
 
335 
   make_vert_count_reg : PROCESS( clock_75MHz , vga_off , s_next_line_reg ,
336 
                                  s_vert_count_is_zero , s_vert_load_value )
337 
   BEGIN
338 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
339 
         IF (vga_off = '1') THEN s_vert_count_reg <= V_FRONT_PORCH_COUNT;
340 
         ELSIF (s_next_line_reg = '1') THEN
341 
            IF (s_vert_count_is_zero = '1') THEN
342 
               s_vert_count_reg <= s_vert_load_value;
343 
                                            ELSE
344 
               s_vert_count_reg <= unsigned( s_vert_count_reg ) - 1;
345 
            END IF;
346 
         END IF;
347 
      END IF;
348 
   END PROCESS make_vert_count_reg;
349 
 
350 
   make_vert_load_value : PROCESS( s_vert_state_reg )
351 
   BEGIN
352 
      CASE (s_vert_state_reg) IS
353 
         WHEN VERTICAL_FRONT_PORCH => s_vert_load_value <= V_SYNC_COUNT;
354 
         WHEN VERTICAL_SYNC        => s_vert_load_value <= V_BACK_PORCH_COUNT;
355 
         WHEN VERTICAL_BACK_PORCH  => s_vert_load_value <= V_ACTIVE_COUNT;
356 
         WHEN OTHERS               => s_vert_load_value <= V_FRONT_PORCH_COUNT;
357 
      END CASE;
358 
   END PROCESS make_vert_load_value;
359 
 
360 
   make_vert_state_reg : PROCESS( clock_75MHz , s_vert_state_reg , s_next_line_reg ,
361 
                                  vga_off , s_vert_count_is_zero )
362 
      VARIABLE v_next_state : VCOUNT_TYPE;
363 
   BEGIN
364 
      CASE ( s_vert_state_reg ) IS
365 
         WHEN VERTICAL_FRONT_PORCH => v_next_state := VERTICAL_SYNC;
366 
         WHEN VERTICAL_SYNC        => v_next_state := VERTICAL_BACK_PORCH;
367 
         WHEN VERTICAL_BACK_PORCH  => v_next_state := VERTICAL_ACTIVE;
368 
         WHEN OTHERS               => v_next_state := VERTICAL_FRONT_PORCH;
369 
      END CASE;
370 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
371 
         IF (vga_off = '1') THEN s_vert_state_reg <= VERTICAL_FRONT_PORCH;
372 
         ELSIF (s_next_line_reg = '1' AND
373 
                s_vert_count_is_zero = '1') THEN s_vert_state_reg <= v_next_state;
374 
         END IF;
375 
      END IF;
376 
   END PROCESS make_vert_state_reg;
377 
 
378 
   make_next_line_reg : PROCESS( clock_75MHz , vga_off , s_next_line )
379 
   BEGIN
380 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
381 
         IF (vga_off = '1') THEN s_next_line_reg <= '0';
382 
                            ELSE s_next_line_reg <= s_next_line;
383 
         END IF;
384 
      END IF;
385 
   END PROCESS make_next_line_reg;
386 
 
387 
   make_new_screen_reg : PROCESS( clock_75MHz , vga_off , s_new_screen , s_req_line )
388 
   BEGIN
389 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
390 
         IF (vga_off = '1') THEN s_new_screen_reg <= '0';
391 
                                 s_req_line_reg   <= '0';
392 
                            ELSE s_new_screen_reg <= s_new_screen;
393 
                                 s_req_line_reg   <= s_req_line;
394 
         END IF;
395 
      END IF;
396 
   END PROCESS make_new_screen_reg;
397 
 
398 
   make_line_counter_reg : PROCESS( clock_75MHz , s_new_screen_reg , s_req_line_reg )
399 
   BEGIN
400 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
401 
         IF (s_new_screen_reg = '1') THEN s_line_counter_reg <= (OTHERS => '0');
402 
         ELSIF (s_req_line_reg = '1') THEN s_line_counter_reg <= unsigned(s_line_counter_reg) + 1;
403 
         END IF;
404 
      END IF;
405 
   END PROCESS make_line_counter_reg;
406 
 
407 
   make_stage_1_regs : PROCESS( clock_75MHz , vga_off , s_line_counter_reg ,
408 
                                fg_color , bg_color , s_hsync , s_vsync , s_n_blank ,
409 
                                s_is_fpga_cursor_pos , s_draw_hor_line ,
410 
                                s_vert_count_is_zero , s_is_usbtmc_cursor )
411 
   BEGIN
412 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
413 
         IF (vga_off = '1') THEN
414 
            s_stage_1_data_sel_reg    <= "00";
415 
            s_stage_1_line_index_reg  <= X"0";
416 
            s_stage_1_pixel_index_reg <= "000";
417 
            s_stage_1_fg_color_reg    <= "000";
418 
            s_stage_1_bg_color_reg    <= "000";
419 
            s_stage_1_hsync_reg       <= '0';
420 
            s_stage_1_vsync_reg       <= '0';
421 
            s_stage_1_n_blank_reg     <= '0';
422 
            s_stage_1_cursor_reg      <= '0';
423 
            s_stage_1_draw_line_reg   <= '0';
424 
                            ELSE
425 
            CASE (s_line_counter_reg(9 DOWNTO 8)) IS
426 
               WHEN   "00"  => s_stage_1_data_sel_reg <= "00";
427 
                               IF (s_horiz_count_reg(9) = '0' AND
428 
                                   (s_line_counter_reg(7 DOWNTO 4) /= X"0" AND
429 
                                    s_line_counter_reg(7 DOWNTO 4) /= X"E" AND
430 
                                    s_line_counter_reg(7 DOWNTO 4) /= X"F")) THEN
431 
                                  s_stage_1_fg_color_reg <= "111";
432 
                                  s_stage_1_bg_color_reg <= "000";
433 
                                                               ELSE
434 
                                  s_stage_1_fg_color_reg <= "110";
435 
                                  s_stage_1_bg_color_reg <= "001";
436 
                               END IF;
437 
                               s_stage_1_draw_line_reg<= s_draw_hor_line;
438 
                               s_stage_1_cursor_reg   <= '0';
439 
               WHEN  OTHERS => s_stage_1_data_sel_reg <= "1"&s_horiz_count_reg(9);
440 
                               IF (s_horiz_count_reg(9) = '1') THEN
441 
                                  s_stage_1_fg_color_reg <= s_usbtmc_fg_color_reg;
442 
                                  s_stage_1_bg_color_reg <= s_usbtmc_bg_color_reg;
443 
                                  s_stage_1_cursor_reg   <= s_is_usbtmc_cursor;
444 
                                                               ELSE
445 
                                  s_stage_1_fg_color_reg <= fg_color;
446 
                                  s_stage_1_bg_color_reg <= bg_color;
447 
                                  s_stage_1_cursor_reg   <= s_is_fpga_cursor_pos;
448 
                               END IF;
449 
                               s_stage_1_draw_line_reg <= s_draw_hor_line OR
450 
                                                          s_vert_count_is_zero;
451 
            END CASE;
452 
            s_stage_1_line_index_reg  <= s_line_counter_reg( 3 DOWNTO 0 );
453 
            s_stage_1_pixel_index_reg <= s_horiz_count_reg( 2 DOWNTO 0 );
454 
            s_stage_1_hsync_reg       <= s_hsync;
455 
            s_stage_1_vsync_reg       <= s_vsync;
456 
            s_stage_1_n_blank_reg     <= s_n_blank;
457 
         END IF;
458 
      END IF;
459 
   END PROCESS make_stage_1_regs;
460 
 
461 
   make_stage_1_data : PROCESS( s_stage_1_data_sel_reg ,
462 
                                s_ascii_data_1 , s_ascii_data_2 , s_ascii_data_3 )
463 
   BEGIN
464 
      CASE (s_stage_1_data_sel_reg) IS
465 
         WHEN  "00"  => s_stage_1_ascii_data <= s_ascii_data_1;
466 
         WHEN  "11"  => s_stage_1_ascii_data <= s_ascii_data_2;
467 
         WHEN OTHERS => s_stage_1_ascii_data <= s_ascii_data_3;
468 
      END CASE;
469 
   END PROCESS make_stage_1_data;
470 
 
471 
   make_stage_2_regs : PROCESS( clock_75MHz , vga_off , s_stage_1_fg_color_reg , s_stage_1_bg_color_reg ,
472 
                                s_stage_1_hsync_reg , s_stage_1_vsync_reg , s_stage_1_n_blank_reg ,
473 
                                s_stage_1_cursor_reg , s_stage_1_ascii_data ,
474 
                                s_blink_reg , s_stage_1_draw_line_reg )
475 
   BEGIN
476 
      IF (clock_75MHz'event AND (clock_75MHz = '1')) THEN
477 
         IF (vga_off = '1') THEN
478 
            s_stage_2_fg_color_reg  <= "000";
479 
            s_stage_2_bg_color_reg  <= "000";
480 
            s_stage_2_hsync_reg     <= '0';
481 
            s_stage_2_vsync_reg     <= '0';
482 
            s_stage_2_n_blank_reg   <= '0';
483 
            s_stage_2_cursor_reg    <= '0';
484 
            s_stage_2_pixel_inv_reg <= '0';
485 
                            ELSE
486 
            IF (s_stage_1_draw_line_reg = '1') THEN
487 
               s_stage_2_fg_color_reg  <= "001";
488 
               s_stage_2_bg_color_reg  <= "001";
489 
                                               ELSE
490 
               s_stage_2_fg_color_reg  <= s_stage_1_fg_color_reg;
491 
               s_stage_2_bg_color_reg  <= s_stage_1_bg_color_reg;
492 
            END IF;
493 
            s_stage_2_hsync_reg     <= s_stage_1_hsync_reg;
494 
            s_stage_2_vsync_reg     <= s_stage_1_vsync_reg;
495 
            s_stage_2_n_blank_reg   <= s_stage_1_n_blank_reg;
496 
            s_stage_2_cursor_reg    <= s_stage_1_cursor_reg AND s_blink_reg;
497 
            s_stage_2_pixel_inv_reg <= s_stage_1_ascii_data(7);
498 
         END IF;
499 
      END IF;
500 
   END PROCESS make_stage_2_regs;
501 
 
502 
--------------------------------------------------------------------------------
503 
--- Here the usbtmc handling is defined                                      ---
504 
--------------------------------------------------------------------------------
505 
   command_done  <= '1' WHEN s_usbtmc_state_reg = SIGNAL_DONE OR
506 
                             s_usbtmc_state_reg = SIGNAL_ERROR ELSE '0';
507 
   command_error <= '1' WHEN s_usbtmc_state_reg = SIGNAL_ERROR ELSE '0';
508 
   pop           <= s_pop_data;
509 
   push          <= s_push;
510 
   push_size     <= '1' WHEN s_push_cnt_reg = X"6" ELSE '0';
511 
 
512 
   s_usbtmc_write_address( 10 DOWNTO 6 ) <= unsigned(s_usbtmc_cursor_y_reg)+
513 
                                            unsigned(s_usbtmc_screen_offset_reg)+
514 
                                            unsigned(s_clear_counter_reg(10 DOWNTO 6));
515 
   s_usbtmc_write_address(  5 DOWNTO 0 ) <= unsigned(s_usbtmc_cursor_x_reg)+
516 
                                            unsigned(s_clear_counter_reg( 5 DOWNTO 0));
517 
   s_usbtmc_write_data                   <= X"20" WHEN s_clear_counter_reg(11) = '0'
518 
                                                  ELSE pop_data;
519 
   s_usbtmc_write_enable <= '1' WHEN s_clear_counter_reg(11) = '0' OR
520 
                                     s_valid_char = '1' ELSE '0';
521 
   s_pop_data    <= '1' WHEN (s_usbtmc_state_reg = GET_BG_COLOR OR
522 
                              s_usbtmc_state_reg = GET_FG_COLOR OR
523 
                              (s_usbtmc_state_reg = WRITE_CHAR AND
524 
                               s_last_char_reg = '0') OR
525 
                              s_usbtmc_state_reg = GET_X_CHAR OR
526 
                              s_usbtmc_state_reg = GET_Y_CHAR) AND
527 
                             pop_empty = '0' ELSE '0';
528 
   s_next_cursor_xpos <= "1000000" WHEN s_pop_data = '1' AND
529 
                                        pop_data = X"0A" AND
530 
                                        s_usbtmc_state_reg = WRITE_CHAR ELSE
531 
                         unsigned("0"&s_usbtmc_cursor_x_reg) + 1
532 
                            WHEN s_valid_char = '1' ELSE
533 
                         "0"&s_usbtmc_cursor_x_reg;
534 
   s_next_cursor_ypos <= unsigned("0"&s_usbtmc_cursor_y_reg)+1;
535 
   s_push             <= '1' WHEN s_usbtmc_state_reg = SEND_CURSOR AND
536 
                                  push_full = '0' AND
537 
                                  s_push_cnt_reg(3) = '0' ELSE '0';
538 
   s_valid_char       <= '1' WHEN s_pop_data = '1' AND
539 
                                  s_usbtmc_state_reg = WRITE_CHAR AND
540 
                                  (unsigned(pop_data(6 DOWNTO 0)) >
541 
                                   unsigned(c_31)) ELSE '0';
542 
 
543 
   make_usbtmc_screen_offset_reg : PROCESS( clock , reset , s_usbtmc_state_reg )
544 
   BEGIN
545 
      IF (clock'event AND (clock = '1')) THEN
546 
         IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN OR
547 
             reset = '1') THEN s_usbtmc_screen_offset_reg <= (OTHERS => '0');
548 
         ELSIF (s_next_cursor_ypos(5) = '1' AND
549 
                s_usbtmc_state_reg = NEW_LINE) THEN
550 
            s_usbtmc_screen_offset_reg <= unsigned(s_usbtmc_screen_offset_reg)+1;
551 
         END IF;
552 
      END IF;
553 
   END PROCESS make_usbtmc_screen_offset_reg;
554 
 
555 
   make_usbtmc_cursor_x_reg : PROCESS( clock , reset , s_usbtmc_state_reg ,
556 
                                       s_new_cursor_x_pos_reg )
557 
   BEGIN
558 
      IF (clock'event AND (clock = '1')) THEN
559 
         IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN OR
560 
             reset = '1') THEN s_usbtmc_cursor_x_reg <= (OTHERS => '0');
561 
         ELSIF (s_usbtmc_state_reg = UPDATE_CURSOR) THEN
562 
            s_usbtmc_cursor_x_reg <= s_new_cursor_x_pos_reg;
563 
                                                    ELSE
564 
            s_usbtmc_cursor_x_reg <= s_next_cursor_xpos(5 DOWNTO 0);
565 
         END IF;
566 
      END IF;
567 
   END PROCESS make_usbtmc_cursor_x_reg;
568 
 
569 
   make_usbtmc_cursor_y_reg : PROCESS( clock , reset , s_usbtmc_state_reg ,
570 
                                       s_next_cursor_ypos ,
571 
                                       s_new_cursor_y_pos_reg)
572 
   BEGIN
573 
      IF (clock'event AND (clock = '1')) THEN
574 
         IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN OR
575 
             reset = '1') THEN s_usbtmc_cursor_y_reg <= (OTHERS => '0');
576 
         ELSIF (s_usbtmc_state_reg = NEW_LINE AND
577 
                s_next_cursor_ypos(5) = '0') THEN
578 
            s_usbtmc_cursor_y_reg <= s_next_cursor_ypos( 4 DOWNTO 0 );
579 
         ELSIF (s_usbtmc_state_reg = UPDATE_CURSOR) THEN
580 
            s_usbtmc_cursor_y_reg <= s_new_cursor_y_pos_reg;
581 
         END IF;
582 
      END IF;
583 
   END PROCESS make_usbtmc_cursor_y_reg;
584 
 
585 
   make_usbtmc_fg_color_reg : PROCESS( clock , reset )
586 
   BEGIN
587 
      IF (clock'event AND (clock = '1')) THEN
588 
         IF (reset = '1') THEN s_usbtmc_fg_color_reg <= "111";
589 
         ELSIF (s_usbtmc_state_reg = SET_FG_COLOR) THEN
590 
            s_usbtmc_fg_color_reg <= s_pop_data_reg( 2 DOWNTO 0 );
591 
         END IF;
592 
      END IF;
593 
   END PROCESS make_usbtmc_fg_color_reg;
594 
 
595 
   make_usbtmc_bg_color_reg : PROCESS( clock , reset )
596 
   BEGIN
597 
      IF (clock'event AND (clock = '1')) THEN
598 
         IF (reset = '1') THEN s_usbtmc_bg_color_reg <= "000";
599 
         ELSIF (s_usbtmc_state_reg = SET_BG_COLOR) THEN
600 
            s_usbtmc_bg_color_reg <= s_pop_data_reg( 2 DOWNTO 0 );
601 
         END IF;
602 
      END IF;
603 
   END PROCESS make_usbtmc_bg_color_reg;
604 
 
605 
   make_pop_data_reg : PROCESS( clock , reset , s_pop_data , pop_data )
606 
   BEGIN
607 
      IF (clock'event AND (clock = '1')) THEN
608 
         IF (reset = '1') THEN s_pop_data_reg <= X"00";
609 
         ELSIF (s_pop_data = '1') THEN s_pop_data_reg <= pop_data;
610 
         END IF;
611 
      END IF;
612 
   END PROCESS make_pop_data_reg;
613 
 
614 
   make_clear_counter_reg : PROCESS( clock , reset , s_usbtmc_state_reg )
615 
   BEGIN
616 
      IF (clock'event AND (clock = '1')) THEN
617 
         IF (s_usbtmc_state_reg = INIT_CLEAR_SCREEN) THEN
618 
            s_clear_counter_reg <= "011111111111";
619 
         ELSIF (s_usbtmc_state_reg = INIT_CLEAR_LINE) THEN
620 
            s_clear_counter_reg <= "000000111111";
621 
         ELSIF (s_clear_counter_reg(11) = '0' AND
622 
                reset = '0') THEN
623 
            s_clear_counter_reg <= unsigned(s_clear_counter_reg) - 1;
624 
         ELSIF (reset = '1' OR
625 
                s_clear_counter_reg(11) = '1') THEN
626 
            s_clear_counter_reg <= "100000000000";
627 
         END IF;
628 
      END IF;
629 
   END PROCESS make_clear_counter_reg;
630 
 
631 
   make_last_char_reg : PROCESS( clock , reset , s_usbtmc_state_reg ,
632 
                                 s_pop_data , pop_last )
633 
   BEGIN
634 
      IF (clock'event AND (clock = '1')) THEN
635 
         IF (s_usbtmc_state_reg = IDLE OR
636 
             reset = '1') THEN s_last_char_reg <= '0';
637 
         ELSIF (s_usbtmc_state_reg = WRITE_CHAR AND
638 
                s_pop_data = '1' AND
639 
                pop_last = '1') THEN s_last_char_reg <= '1';
640 
         END IF;
641 
      END IF;
642 
   END PROCESS make_last_char_reg;
643 
 
644 
   make_usbtmc_cursor_x_bcd_reg : PROCESS( clock , s_usbtmc_cursor_x_reg )
645 
      VARIABLE v_sub1   : std_logic_vector( 4 DOWNTO 0 );
646 
      VARIABLE v_rest_1 : std_logic_vector( 4 DOWNTO 0 );
647 
      VARIABLE v_sub2   : std_logic_vector( 4 DOWNTO 0 );
648 
      VARIABLE v_rest_2 : std_logic_vector( 4 DOWNTO 0 );
649 
      VARIABLE v_sub3   : std_logic_vector( 4 DOWNTO 0 );
650 
      VARIABLE v_rest_3 : std_logic_vector( 3 DOWNTO 0 );
651 
   BEGIN
652 
      v_sub1 := unsigned("0"&s_usbtmc_cursor_x_reg(5 DOWNTO 2)) -
653 
                unsigned(c_ten);
654 
      IF (v_sub1(4) = '0') THEN v_rest_1 := v_sub1(3 DOWNTO 0)&
655 
                                            s_usbtmc_cursor_x_reg(1);
656 
                           ELSE v_rest_1 := s_usbtmc_cursor_x_reg(5 DOWNTO 1);
657 
      END IF;
658 
      v_sub2 := unsigned(v_rest_1) - unsigned(c_ten);
659 
      IF (v_sub2(4) = '0') THEN v_rest_2 := v_sub2(3 DOWNTO 0)&
660 
                                            s_usbtmc_cursor_x_reg(0);
661 
                           ELSE v_rest_2 := v_rest_1(3 DOWNTO 0)&
662 
                                            s_usbtmc_cursor_x_reg(0);
663 
      END IF;
664 
      v_sub3 := unsigned(v_rest_2) - unsigned(c_ten);
665 
      IF (v_sub3(4) = '0') THEN v_rest_3 := v_sub3( 3 DOWNTO 0 );
666 
                           ELSE v_rest_3 := v_rest_2( 3 DOWNTO 0 );
667 
      END IF;
668 
      IF (clock'event AND (clock = '1')) THEN
669 
         s_usbtmc_cursor_x_bcd_reg(6) <= NOT(v_sub1(4));
670 
         s_usbtmc_cursor_x_bcd_reg(5) <= NOT(v_sub2(4));
671 
         s_usbtmc_cursor_x_bcd_reg(4) <= NOT(v_sub3(4));
672 
         s_usbtmc_cursor_x_bcd_reg(3 DOWNTO 0) <= v_rest_3;
673 
      END IF;
674 
   END PROCESS make_usbtmc_cursor_x_bcd_reg;
675 
 
676 
   make_usbtmc_cursor_y_bcd_reg : PROCESS( clock , s_usbtmc_cursor_y_reg )
677 
      VARIABLE v_sub1   : std_logic_vector( 4 DOWNTO 0 );
678 
      VARIABLE v_rest_1 : std_logic_vector( 4 DOWNTO 0 );
679 
      VARIABLE v_sub2   : std_logic_vector( 4 DOWNTO 0 );
680 
      VARIABLE v_rest_2 : std_logic_vector( 3 DOWNTO 0 );
681 
   BEGIN
682 
      v_sub1 := unsigned("0"&s_usbtmc_cursor_y_reg(4 DOWNTO 1)) -
683 
                unsigned(c_ten);
684 
      IF (v_sub1(4) = '0') THEN v_rest_1 := v_sub1(3 DOWNTO 0)&
685 
                                            s_usbtmc_cursor_y_reg(0);
686 
                           ELSE v_rest_1 := s_usbtmc_cursor_y_reg(4 DOWNTO 0);
687 
      END IF;
688 
      v_sub2 := unsigned(v_rest_1) - unsigned(c_ten);
689 
      IF (v_sub2(4) = '0') THEN v_rest_2 := v_sub2(3 DOWNTO 0);
690 
                           ELSE v_rest_2 := v_rest_1(3 DOWNTO 0);
691 
      END IF;
692 
      IF (clock'event AND (clock = '1')) THEN
693 
         s_usbtmc_cursor_y_bcd_reg(5) <= NOT(v_sub1(4));
694 
         s_usbtmc_cursor_y_bcd_reg(4) <= NOT(v_sub2(4));
695 
         s_usbtmc_cursor_y_bcd_reg(3 DOWNTO 0) <= v_rest_2;
696 
      END IF;
697 
   END PROCESS make_usbtmc_cursor_y_bcd_reg;
698 
 
699 
   make_push_data : PROCESS( s_push_cnt_reg , s_usbtmc_cursor_x_bcd_reg ,
700 
                             s_usbtmc_cursor_y_bcd_reg)
701 
   BEGIN
702 
      CASE (s_push_cnt_reg) IS
703 
         WHEN  X"6"  => IF (s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4) = "000" AND
704 
                            s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4) = "00") THEN
705 
                           push_data <= X"04";
706 
                        ELSIF (s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4) = "000" OR
707 
                               s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4) = "00") THEN
708 
                           push_data <= X"05";
709 
                                                                             ELSE
710 
                           push_data <= X"06";
711 
                        END IF;
712 
         WHEN  X"5"  => push_data <= X"3"&"0"&s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4);
713 
         WHEN  X"4"  => push_data <= X"3"&s_usbtmc_cursor_x_bcd_reg(3 DOWNTO 0);
714 
         WHEN  X"3"  => push_data <= X"2C";
715 
         WHEN  X"2"  => push_data <= X"3"&"00"&s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4);
716 
         WHEN  X"1"  => push_data <= X"3"&s_usbtmc_cursor_y_bcd_reg(3 DOWNTO 0);
717 
         WHEN  X"0"  => push_data <= X"0A";
718 
         WHEN OTHERS => push_data <= X"00";
719 
      END CASE;
720 
   END PROCESS make_push_data;
721 
 
722 
   make_push_cnt_reg : PROCESS( clock , reset , s_usbtmc_cursor_x_bcd_reg ,
723 
                                s_usbtmc_cursor_y_bcd_reg )
724 
   BEGIN
725 
      IF (clock'event AND (clock = '1')) THEN
726 
         IF (reset = '1') THEN s_push_cnt_reg <= (OTHERS => '1');
727 
         ELSIF (s_usbtmc_state_reg = INIT_CURSOR_SEND) THEN
728 
            s_push_cnt_reg <= X"6";
729 
         ELSIF (s_push = '1') THEN
730 
            CASE (s_push_cnt_reg) IS
731 
               WHEN  X"6"  => IF (s_usbtmc_cursor_x_bcd_reg(6 DOWNTO 4) = "000") THEN
732 
                                 s_push_cnt_reg <= X"4";
733 
                                                                                    ELSE
734 
                                 s_push_cnt_reg <= X"5";
735 
                              END IF;
736 
               WHEN  X"3"  => IF (s_usbtmc_cursor_y_bcd_reg(5 DOWNTO 4) = "00") THEN
737 
                                 s_push_cnt_reg <= X"1";
738 
                                                                                ELSE
739 
                                 s_push_cnt_reg <= X"2";
740 
                              END IF;
741 
               WHEN OTHERS => s_push_cnt_reg <= unsigned(s_push_cnt_reg) - 1;
742 
            END CASE;
743 
         END IF;
744 
      END IF;
745 
   END PROCESS make_push_cnt_reg;
746 
 
747 
   make_new_cursor_x_pos_reg : PROCESS( clock , reset , s_usbtmc_state_reg ,
748 
                                        s_pop_data_reg )
749 
      VARIABLE v_add_1 : std_logic_vector( 5 DOWNTO 0 );
750 
      VARIABLE v_add_2 : std_logic_vector( 5 DOWNTO 0 );
751 
      VARIABLE v_add_3 : std_logic_vector( 5 DOWNTO 0 );
752 
   BEGIN
753 
      IF (clock'event AND (clock = '1')) THEN
754 
         IF (s_usbtmc_state_reg = INIT_GET_CURSOR OR
755 
             reset = '1') THEN
756 
            s_new_cursor_x_pos_reg <= (OTHERS => '0');
757 
         ELSIF (s_usbtmc_state_reg = MULT_10_X) THEN
758 
            v_add_1 := s_new_cursor_x_pos_reg(2 DOWNTO 0)&"000";
759 
            v_add_2 := s_new_cursor_x_pos_reg(4 DOWNTO 0)&"0";
760 
            v_add_3 := "00"&s_pop_data_reg(3 DOWNTO 0);
761 
            s_new_cursor_x_pos_reg <= unsigned(v_add_1) +
762 
                                      unsigned(v_add_2) +
763 
                                      unsigned(v_add_3);
764 
         END IF;
765 
      END IF;
766 
   END PROCESS make_new_cursor_x_pos_reg;
767 
 
768 
   make_new_cursor_y_pos_reg : PROCESS( clock , reset , s_usbtmc_state_reg ,
769 
                                        s_pop_data_reg )
770 
      VARIABLE v_add_1 : std_logic_vector( 4 DOWNTO 0 );
771 
      VARIABLE v_add_2 : std_logic_vector( 4 DOWNTO 0 );
772 
      VARIABLE v_add_3 : std_logic_vector( 4 DOWNTO 0 );
773 
   BEGIN
774 
      IF (clock'event AND (clock = '1')) THEN
775 
         IF (s_usbtmc_state_reg = INIT_GET_CURSOR OR
776 
             reset = '1') THEN
777 
            s_new_cursor_y_pos_reg <= (OTHERS => '0');
778 
         ELSIF (s_usbtmc_state_reg = MULT_10_Y) THEN
779 
            v_add_1 := s_new_cursor_y_pos_reg( 1 DOWNTO 0 )&"000";
780 
            v_add_2 := s_new_cursor_y_pos_reg( 3 DOWNTO 0 )&"0";
781 
            v_add_3 := "0"&s_pop_data_reg( 3 DOWNTO 0 );
782 
            s_new_cursor_y_pos_reg <= unsigned(v_add_1) +
783 
                                      unsigned(v_add_2) +
784 
                                      unsigned(v_add_3);
785 
         END IF;
786 
      END IF;
787 
   END PROCESS make_new_cursor_y_pos_reg;
788 
 
789 
   make_state_reg : PROCESS( clock , reset , s_usbtmc_state_reg , start_command ,
790 
                             command_id , s_clear_counter_reg )
791 
      VARIABLE v_next_state : USBTMC_STATE_TYPE;
792 
   BEGIN
793 
      CASE (s_usbtmc_state_reg) IS
794 
         WHEN IDLE               => IF (start_command = '1') THEN
795 
                                       CASE (command_id) IS
796 
                                          WHEN "0111011" => v_next_state := GET_BG_COLOR;
797 
                                          WHEN "0111100" => v_next_state := INIT_CLEAR_SCREEN;
798 
                                          WHEN "0111101" => v_next_state := INIT_GET_CURSOR;
799 
                                          WHEN "0111110" => v_next_state := INIT_CURSOR_SEND;
800 
                                          WHEN "0111111" => v_next_state := GET_FG_COLOR;
801 
                                          WHEN "1000000" => v_next_state := WRITE_CHAR;
802 
                                          WHEN OTHERS    => v_next_state := IDLE;
803 
                                       END CASE;
804 
                                                             ELSE
805 
                                       v_next_state := IDLE;
806 
                                    END IF;
807 
         WHEN INIT_CLEAR_SCREEN  => v_next_state := CLEAR_SCREEN;
808 
         WHEN CLEAR_SCREEN       => IF (s_clear_counter_reg(11) = '1') THEN
809 
                                       v_next_state := SIGNAL_DONE;
810 
                                                                       ELSE
811 
                                       v_next_state := CLEAR_SCREEN;
812 
                                    END IF;
813 
         WHEN GET_BG_COLOR       => IF (s_pop_data = '1') THEN
814 
                                       IF (pop_data(7 DOWNTO 4) = X"3") THEN
815 
                                          v_next_state := SET_BG_COLOR;
816 
                                       ELSIF (pop_data = X"20" AND
817 
                                              pop_last = '0') THEN
818 
                                          v_next_state := GET_BG_COLOR;
819 
                                                              ELSE
820 
                                          v_next_state := SIGNAL_ERROR;
821 
                                       END IF;
822 
                                                          ELSE
823 
                                       v_next_state := GET_BG_COLOR;
824 
                                    END IF;
825 
         WHEN SET_BG_COLOR       => v_next_state := SIGNAL_DONE;
826 
         WHEN GET_FG_COLOR       => IF (s_pop_data = '1') THEN
827 
                                       IF (pop_data(7 DOWNTO 4) = X"3") THEN
828 
                                          v_next_state := SET_FG_COLOR;
829 
                                       ELSIF (pop_data = X"20" AND
830 
                                              pop_last = '0') THEN
831 
                                          v_next_state := GET_FG_COLOR;
832 
                                                              ELSE
833 
                                          v_next_state := SIGNAL_ERROR;
834 
                                       END IF;
835 
                                                          ELSE
836 
                                       v_next_state := GET_FG_COLOR;
837 
                                    END IF;
838 
         WHEN SET_FG_COLOR       => v_next_state := SIGNAL_DONE;
839 
         WHEN WRITE_CHAR         => IF (s_last_char_reg = '1') THEN
840 
                                        v_next_state := SIGNAL_DONE;
841 
                                    ELSIF (s_next_cursor_xpos(6) = '1') THEN
842 
                                          v_next_state := NEW_LINE;
843 
                                                                        ELSE
844 
                                          v_next_state := WRITE_CHAR;
845 
                                    END IF;
846 
         WHEN NEW_LINE           => IF (s_next_cursor_ypos(5) = '1') THEN
847 
                                       v_next_state := INIT_CLEAR_LINE;
848 
                                                                     ELSE
849 
                                       v_next_state := WRITE_CHAR;
850 
                                    END IF;
851 
         WHEN INIT_CLEAR_LINE    => v_next_state := CLEAR_LINE;
852 
         WHEN CLEAR_LINE         => IF (s_clear_counter_reg(11) = '1') THEN
853 
                                       v_next_state := CLEAR_NOP;
854 
                                                                       ELSE
855 
                                       v_next_state := CLEAR_LINE;
856 
                                    END IF;
857 
         WHEN CLEAR_NOP          => v_next_state := WRITE_CHAR;
858 
         WHEN INIT_CURSOR_SEND   => v_next_state := SEND_CURSOR;
859 
         WHEN SEND_CURSOR        => IF (s_push_cnt_reg(3) = '1') THEN
860 
                                       v_next_state := SIGNAL_DONE;
861 
                                                                 ELSE
862 
                                       v_next_state := SEND_CURSOR;
863 
                                    END IF;
864 
         WHEN INIT_GET_CURSOR    => v_next_state := GET_X_CHAR;
865 
         WHEN GET_X_CHAR         => IF (s_pop_data = '1') THEN
866 
                                       IF (pop_data = X"20" AND
867 
                                           pop_last = '0') THEN
868 
                                          v_next_state := GET_X_CHAR;
869 
                                       ELSIF (pop_data = X"2C" AND
870 
                                              pop_last = '0') THEN
871 
                                          v_next_state := GET_Y_CHAR;
872 
                                       ELSIF (pop_data(7 DOWNTO 4) = X"3" AND
873 
                                              pop_last = '0') THEN
874 
                                          v_next_state := MULT_10_X;
875 
                                                                           ELSE
876 
                                          v_next_state := SIGNAL_ERROR;
877 
                                       END IF;
878 
                                                          ELSE
879 
                                       v_next_state := GET_X_CHAR;
880 
                                    END IF;
881 
         WHEN MULT_10_X          => v_next_state := GET_X_CHAR;
882 
         WHEN GET_Y_CHAR         => IF (s_pop_data = '1') THEN
883 
                                       IF (pop_data = X"20" AND
884 
                                           pop_last = '0') THEN
885 
                                          v_next_state := GET_Y_CHAR;
886 
                                       ELSIF (pop_data = X"0A" AND
887 
                                              pop_last = '1') THEN
888 
                                          v_next_state := UPDATE_CURSOR;
889 
                                       ELSIF (pop_data(7 DOWNTO 4) = X"3" AND
890 
                                              pop_last = '0') THEN
891 
                                          v_next_state := MULT_10_Y;
892 
                                                                           ELSE
893 
                                          v_next_state := SIGNAL_ERROR;
894 
                                       END IF;
895 
                                                          ELSE
896 
                                       v_next_state := GET_Y_CHAR;
897 
                                    END IF;
898 
         WHEN MULT_10_Y          => v_next_state := GET_Y_CHAR;
899 
         WHEN UPDATE_CURSOR      => v_next_state := SIGNAL_DONE;
900 
         WHEN OTHERS             => v_next_state := IDLE;
901 
      END CASE;
902 
      IF (clock'event AND (clock = '1')) THEN
903 
         IF (reset = '1') THEN s_usbtmc_state_reg <= IDLE;
904 
                          ELSE s_usbtmc_state_reg <= v_next_state;
905 
         END IF;
906 
      END IF;
907 
   END PROCESS make_state_reg;
908 
 
909 
-- map components
910 
   hsync_ff : FDC
911 
              GENERIC MAP ( INIT => '0' )
912 
              PORT MAP ( Q   => vga_hsync,
913 
                         C   => clock_75MHz,
914 
                         CLR => vga_off,
915 
                         D   => s_stage_2_hsync_reg );
916 
 
917 
   vsync_ff : FDC
918 
              GENERIC MAP ( INIT => '0' )
919 
              PORT MAP ( Q   => vga_vsync,
920 
                         C   => clock_75MHz,
921 
                         CLR => vga_off,
922 
                         D   => s_stage_2_vsync_reg );
923 
   red_ff : FDC
924 
            GENERIC MAP ( INIT => '0' )
925 
            PORT MAP ( Q   => vga_red,
926 
                       C   => clock_75MHz,
927 
                       CLR => vga_off,
928 
                       D   => s_red );
929 
 
930 
   green_ff : FDC
931 
              GENERIC MAP ( INIT => '0' )
932 
              PORT MAP ( Q   => vga_green,
933 
                         C   => clock_75MHz,
934 
                         CLR => vga_off,
935 
                         D   => s_green );
936 
 
937 
   blue_ff : FDC
938 
             GENERIC MAP ( INIT => '0' )
939 
             PORT MAP ( Q   => vga_blue,
940 
                        C   => clock_75MHz,
941 
                        CLR => vga_off,
942 
                        D   => s_blue );
943 
 
944 
   usbtmc_buf : RAMB16_S9_S9
945 
                PORT MAP ( DOA   => s_ascii_data_2,
946 
                           DOPA  => OPEN,
947 
                           ADDRA => s_usbtmc_lookup_address,
948 
                           CLKA  => clock_75MHz,
949 
                           DIA   => X"00",
950 
                           DIPA  => "0",
951 
                           ENA   => s_n_blank,
952 
                           SSRA  => '0',
953 
                           WEA   => '0',
954 
                           DOB   => OPEN,
955 
                           DOPB  => OPEN,
956 
                           ADDRB => s_usbtmc_write_address,
957 
                           CLKB  => clock,
958 
                           DIB   => s_usbtmc_write_data,
959 
                           DIPB  => "1",
960 
                           ENB   => s_usbtmc_write_enable,
961 
                           SSRB  => '0',
962 
                           WEB   => s_usbtmc_write_enable);
963 
 
964 
   fpga_buf : RAMB16_S9_S9
965 
                PORT MAP ( DOA   => s_ascii_data_3,
966 
                           DOPA  => OPEN,
967 
                           ADDRA => s_fpga_lookup_address,
968 
                           CLKA  => clock_75MHz,
969 
                           DIA   => X"00",
970 
                           DIPA  => "0",
971 
                           ENA   => s_n_blank,
972 
                           SSRA  => '0',
973 
                           WEA   => '0',
974 
                           DOB   => OPEN,
975 
                           DOPB  => OPEN,
976 
                           ADDRB => write_address,
977 
                           CLKB  => clock,
978 
                           DIB   => ascii_data,
979 
                           DIPB  => "1",
980 
                           ENB   => we,
981 
                           SSRB  => '0',
982 
                           WEB   => we);
983 
 
984 
   ascii_buf0 : RAMB16_S9_S9
985 
                PORT MAP ( DOA   => s_ascii_data_1,
986 
                           DOPA  => OPEN,
987 
                           ADDRA => s_lookup_address,
988 
                           CLKA  => clock_75MHz,
989 
                           DIA   => X"00",
990 
                           DIPA  => "0",
991 
                           ENA   => s_n_blank,
992 
                           SSRA  => '0',
993 
                           WEA   => '0',
994 
                           DOB   => OPEN,
995 
                           DOPB  => OPEN,
996 
                           ADDRB => we_addr,
997 
                           CLKB  => clock,
998 
                           DIB   => we_ascii,
999 
                           DIPB  => "1",
1000 
                           ENB   => we_char,
1001 
                           SSRB  => '0',
1002 
                           WEB   => we_char);
1003 
   rom_lo : RAMB16_S1
1004 
      PORT MAP ( DO   => s_rom_value_0,
1005 
                 ADDR => s_rom_index(13 DOWNTO 0),
1006 
                 CLK  => clock_75MHz,
1007 
                 DI   => s_rom_value_0,
1008 
                 EN   => '1',
1009 
                 SSR  => '0',
1010 
                 WE   => '0');
1011 
 
1012 
END xilinx;

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