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[/] [gecko4/] [trunk/] [GECKO4com/] [spartan200_an/] [vhdl/] [vga/] [vga_leds_buttons_bus-behavior.vhdl] - Blame information for rev 5

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1 5 ktt1 
--------------------------------------------------------------------------------
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--            _   _            __   ____                                      --
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--           / / | |          / _| |  __|                                     --
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--           | |_| |  _   _  / /   | |_                                       --
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--           |  _  | | | | | | |   |  _|                                      --
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--           | | | | | |_| | \ \_  | |__                                      --
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--           |_| |_| \_____|  \__| |____| microLab                            --
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--                                                                            --
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--           Bern University of Applied Sciences (BFH)                        --
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--           Quellgasse 21                                                    --
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--           Room HG 4.33                                                     --
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--           2501 Biel/Bienne                                                 --
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--           Switzerland                                                      --
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--                                                                            --
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--           http://www.microlab.ch                                           --
16 
--------------------------------------------------------------------------------
17 
--   GECKO4com
18 
--
19 
--   2010/2011 Dr. Theo Kluter
20 
--
21 
--   This VHDL code is free code: you can redistribute it and/or modify
22 
--   it under the terms of the GNU General Public License as published by
23 
--   the Free Software Foundation, either version 3 of the License, or
24 
--   (at your option) any later version.
25 
--
26 
--   This VHDL code is distributed in the hope that it will be useful,
27 
--   but WITHOUT ANY WARRANTY; without even the implied warranty of
28 
--   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
29 
--   GNU General Public License for more details.
30 
--   You should have received a copy of the GNU General Public License
31 
--   along with these sources.  If not, see <http://www.gnu.org/licenses/>.
32 
--
33 
 
34 
ARCHITECTURE no_target_specific OF vga_bus IS
35 
   TYPE VGA_STATE_TYPE IS (IDLE , INIT_CLEAR_SCREEN , CLEAR_SCREEN ,
36 
                           INIT_CLEAR_LINE );
37 
 
38 
   SIGNAL s_led_0_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
39 
   SIGNAL s_led_1_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
40 
   SIGNAL s_led_2_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
41 
   SIGNAL s_led_3_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
42 
   SIGNAL s_led_4_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
43 
   SIGNAL s_led_5_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
44 
   SIGNAL s_led_6_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
45 
   SIGNAL s_led_7_mode_reg            : std_logic_vector( 3 DOWNTO 0 );
46 
   SIGNAL s_led_delay_cnt_reg         : std_logic_vector( 7 DOWNTO 0 );
47 
   SIGNAL s_led_blink_cnt_reg         : std_logic_vector( 2 DOWNTO 0 );
48 
   SIGNAL s_my_write_burst_active_reg : std_logic;
49 
   SIGNAL s_n_bus_error_reg           : std_logic;
50 
   SIGNAL s_n_bus_error_next          : std_logic;
51 
   SIGNAL s_n_data_valid_reg          : std_logic;
52 
   SIGNAL s_fg_color_reg              : std_logic_vector( 2 DOWNTO 0 );
53 
   SIGNAL s_bg_color_reg              : std_logic_vector( 2 DOWNTO 0 );
54 
   SIGNAL s_cursor_x_pos_reg          : std_logic_vector( 5 DOWNTO 0 );
55 
   SIGNAL s_cursor_y_pos_reg          : std_logic_vector( 4 DOWNTO 0 );
56 
   SIGNAL s_screen_offset_reg         : std_logic_vector( 4 DOWNTO 0 );
57 
   SIGNAL s_clear_screen_cnt_reg      : std_logic_vector(11 DOWNTO 0 );
58 
   SIGNAL s_vga_state_reg             : VGA_STATE_TYPE;
59 
   SIGNAL s_we_ascii                  : std_logic;
60 
   SIGNAL s_next_x_pos                : std_logic_vector( 6 DOWNTO 0 );
61 
   SIGNAL s_next_y_pos                : std_logic_vector( 5 DOWNTO 0 );
62 
   SIGNAL s_write_pending_reg         : std_logic;
63 
 
64 
BEGIN
65 
--------------------------------------------------------------------------------
66 
--- Here the outputs are defined                                             ---
67 
--------------------------------------------------------------------------------
68 
   n_start_send               <= '0' WHEN (n_start_transmission = '0' AND
69 
                                           bus_address(5 DOWNTO 4) = "10" AND
70 
                                           read_n_write = '0' AND
71 
                                           s_n_bus_error_next = '1' AND
72 
                                           s_vga_state_reg = IDLE) OR
73 
                                          (s_write_pending_reg = '1' AND
74 
                                           s_vga_state_reg = IDLE) ELSE '1';
75 
   n_bus_error                <= s_n_bus_error_reg;
76 
   n_end_transmission_out     <= '0' WHEN s_n_bus_error_reg = '0' OR
77 
                                          s_n_data_valid_reg = '0' ELSE '1';
78 
   n_data_valid_out           <= "1"&s_n_data_valid_reg;
79 
   fg_color                   <= s_fg_color_reg;
80 
   bg_color                   <= s_bg_color_reg;
81 
   cursor_pos                 <= s_cursor_y_pos_reg&s_cursor_x_pos_reg;
82 
   write_address(5 DOWNTO 0)  <= unsigned(s_cursor_x_pos_reg)+
83 
                                 unsigned(s_clear_screen_cnt_reg( 5 DOWNTO 0 ));
84 
   write_address(10 DOWNTO 6) <= unsigned(s_screen_offset_reg) +
85 
                                 unsigned(s_cursor_y_pos_reg) +
86 
                                 unsigned(s_clear_screen_cnt_reg(10 DOWNTO 6));
87 
   screen_offset              <= s_screen_offset_reg;
88 
   ascii_data                 <= data_in WHEN s_clear_screen_cnt_reg(11) = '1' ELSE X"20";
89 
   we                         <= '1' WHEN s_clear_screen_cnt_reg(11) = '0' OR
90 
                                          (s_we_ascii = '1' AND
91 
                                           data_in /= X"0A") ELSE '0';
92 
 
93 
--------------------------------------------------------------------------------
94 
--- Here the data out is defined                                             ---
95 
--------------------------------------------------------------------------------
96 
   make_data_out : PROCESS( bus_address , n_button_1 , n_button_2 , n_button_3 ,
97 
                            hexswitch , clock , s_fg_color_reg , s_bg_color_reg,
98 
                            s_led_0_mode_reg , s_led_1_mode_reg , s_led_2_mode_reg ,
99 
                            s_led_3_mode_reg , s_led_4_mode_reg , s_led_5_mode_reg ,
100 
                            s_led_6_mode_reg , s_led_7_mode_reg ,
101 
                            s_cursor_x_pos_reg , s_cursor_y_pos_reg )
102 
   BEGIN
103 
      IF (clock'event AND (clock = '1')) THEN
104 
         IF (bus_address(5 DOWNTO 4) = "10") THEN
105 
            CASE (bus_address(3 DOWNTO 0)) IS
106 
               WHEN  X"0"  => data_out <= X"000"&"0"&s_fg_color_reg;
107 
               WHEN  X"1"  => data_out <= X"000"&"0"&s_bg_color_reg;
108 
               WHEN  X"2"  => data_out <= X"00"&"00"&s_cursor_x_pos_reg;
109 
               WHEN  X"3"  => data_out <= X"00"&"000"&s_cursor_y_pos_reg;
110 
               WHEN  X"6"  => data_out(15 DOWNTO 3) <= (OTHERS => '0');
111 
                              data_out(2) <= NOT(n_button_3);
112 
                              data_out(1) <= NOT(n_button_2);
113 
                              data_out(0) <= NOT(n_button_1);
114 
               WHEN  X"7"  => data_out <= X"000"&hexswitch;
115 
               WHEN  X"8"  => data_out <= X"000"&s_led_0_mode_reg;
116 
               WHEN  X"9"  => data_out <= X"000"&s_led_1_mode_reg;
117 
               WHEN  X"A"  => data_out <= X"000"&s_led_2_mode_reg;
118 
               WHEN  X"B"  => data_out <= X"000"&s_led_3_mode_reg;
119 
               WHEN  X"C"  => data_out <= X"000"&s_led_4_mode_reg;
120 
               WHEN  X"D"  => data_out <= X"000"&s_led_5_mode_reg;
121 
               WHEN  X"E"  => data_out <= X"000"&s_led_6_mode_reg;
122 
               WHEN  X"F"  => data_out <= X"000"&s_led_7_mode_reg;
123 
               WHEN OTHERS => data_out <= X"FFFF";
124 
            END CASE;
125 
                                             ELSE
126 
            data_out <= X"0000";
127 
         END IF;
128 
      END IF;
129 
   END PROCESS make_data_out;
130 
 
131 
--------------------------------------------------------------------------------
132 
--- Here the bus control signals are defined                                 ---
133 
--------------------------------------------------------------------------------
134 
   s_n_bus_error_next <= '0' WHEN bus_address(5 DOWNTO 4) = "10" AND
135 
                                  n_start_transmission = '0' AND
136 
                                  (burst_size /= "000000000" OR
137 
                                   (read_n_write = '1' AND              -- Write only regs
138 
                                    (bus_address(3 DOWNTO 0) = X"4" OR
139 
                                     bus_address(3 DOWNTO 0) = X"5")) OR
140 
                                   (read_n_write = '0' AND              -- Read only regs
141 
                                    (bus_address(3 DOWNTO 0) = X"6" OR
142 
                                     bus_address(3 DOWNTO 0) = X"7"))) ELSE '1';
143 
 
144 
   make_my_write_burst_active_reg : PROCESS( clock , reset , bus_address ,
145 
                                             n_start_transmission ,
146 
                                             n_end_transmission_in ,
147 
                                             n_bus_reset , s_n_bus_error_next )
148 
   BEGIN
149 
      IF (clock'event AND (clock = '1')) THEN
150 
         IF (n_end_transmission_in = '0' OR
151 
             reset = '1' OR
152 
             n_bus_reset = '0') THEN s_my_write_burst_active_reg <= '0';
153 
         ELSIF (n_start_transmission = '0' AND
154 
                bus_address(5 DOWNTO 4) = "10" AND
155 
                read_n_write = '0' AND
156 
                s_n_bus_error_next = '1') THEN
157 
            s_my_write_burst_active_reg <= '1';
158 
         END IF;
159 
      END IF;
160 
   END PROCESS make_my_write_burst_active_reg;
161 
 
162 
 
163 
   make_n_bus_error_reg : PROCESS( clock , s_n_bus_error_next )
164 
   BEGIN
165 
      IF (clock'event AND (clock = '1')) THEN
166 
         s_n_bus_error_reg <= s_n_bus_error_next;
167 
      END IF;
168 
   END PROCESS make_n_bus_error_reg;
169 
 
170 
   make_n_data_valid_reg : PROCESS( clock , bus_address , n_start_transmission ,
171 
                                    burst_size , read_n_write ,
172 
                                    s_n_bus_error_next )
173 
   BEGIN
174 
      IF (clock'event AND (clock = '1')) THEN
175 
         IF (bus_address(5 DOWNTO 4) = "10" AND
176 
             n_start_transmission = '0' AND
177 
             burst_size = "000000000") THEN
178 
                s_n_data_valid_reg <= NOT(read_n_write) OR NOT(s_n_bus_error_next);
179 
                                       ELSE s_n_data_valid_reg <= '1';
180 
         END IF;
181 
      END IF;
182 
   END PROCESS make_n_data_valid_reg;
183 
 
184 
--------------------------------------------------------------------------------
185 
--- Here the vga controller is defined                                       ---
186 
--------------------------------------------------------------------------------
187 
   s_we_ascii <= '1' WHEN n_data_valid_in = '0' AND
188 
                          s_my_write_burst_active_reg = '1' AND
189 
                          bus_address( 3 DOWNTO 0 ) = X"4" ELSE '0';
190 
   s_next_x_pos <= "0"&s_cursor_x_pos_reg WHEN s_we_ascii = '0' ELSE
191 
                   "1000000" WHEN data_in = X"0A" ELSE
192 
                   unsigned("0"&s_cursor_x_pos_reg) + 1;
193 
   s_next_y_pos <= unsigned("0"&s_cursor_y_pos_reg) + 1;
194 
 
195 
   make_write_pending_reg : PROCESS( clock , reset , n_end_transmission_in ,
196 
                                     s_vga_state_reg )
197 
   BEGIN
198 
      IF (clock'event AND (clock = '1')) THEN
199 
         IF (s_vga_state_reg = IDLE OR
200 
             n_end_transmission_in = '0' OR
201 
             reset = '1') THEN s_write_pending_reg <= '0';
202 
         ELSIF (n_start_transmission = '0' AND
203 
                bus_address(5 DOWNTO 4) = "10" AND
204 
                read_n_write = '0' AND
205 
                s_n_bus_error_next = '1' AND
206 
                s_vga_state_reg /= IDLE) THEN
207 
            s_write_pending_reg <= '1';
208 
         END IF;
209 
      END IF;
210 
   END PROCESS make_write_pending_reg;
211 
 
212 
   make_fg_color_reg : PROCESS( clock , reset , n_bus_reset , data_in ,
213 
                                n_data_valid_in , s_my_write_burst_active_reg ,
214 
                                bus_address )
215 
   BEGIN
216 
      IF (clock'event AND (clock = '1')) THEN
217 
         IF (n_bus_reset = '0' OR
218 
             reset = '1') THEN s_fg_color_reg <= "100";
219 
         ELSIF (n_data_valid_in = '0' AND
220 
                s_my_write_burst_active_reg = '1' AND
221 
                bus_address( 3 DOWNTO 0 ) = X"0") THEN
222 
            s_fg_color_reg <= data_in( 2 DOWNTO 0 );
223 
         END IF;
224 
      END IF;
225 
   END PROCESS make_fg_color_reg;
226 
 
227 
   make_bg_color_reg : PROCESS( clock , reset , n_bus_reset , data_in ,
228 
                                n_data_valid_in , s_my_write_burst_active_reg ,
229 
                                bus_address )
230 
   BEGIN
231 
      IF (clock'event AND (clock = '1')) THEN
232 
         IF (n_bus_reset = '0' OR
233 
             reset = '1') THEN s_bg_color_reg <= "000";
234 
         ELSIF (n_data_valid_in = '0' AND
235 
                s_my_write_burst_active_reg = '1' AND
236 
                bus_address( 3 DOWNTO 0 ) = X"1") THEN
237 
            s_bg_color_reg <= data_in( 2 DOWNTO 0 );
238 
         END IF;
239 
      END IF;
240 
   END PROCESS make_bg_color_reg;
241 
 
242 
   make_cursor_x_pos_reg : PROCESS( clock , reset , data_in , s_next_x_pos ,
243 
                                    n_data_valid_in , s_my_write_burst_active_reg ,
244 
                                    bus_address , s_vga_state_reg )
245 
   BEGIN
246 
      IF (clock'event AND (clock = '1')) THEN
247 
         IF (s_vga_state_reg = INIT_CLEAR_SCREEN OR
248 
             reset = '1') THEN s_cursor_x_pos_reg <= (OTHERS => '0');
249 
         ELSIF (n_data_valid_in = '0' AND
250 
                s_my_write_burst_active_reg = '1' AND
251 
                bus_address( 3 DOWNTO 0 ) = X"2") THEN
252 
            s_cursor_x_pos_reg <= data_in( 5 DOWNTO 0 );
253 
                                                  ELSE
254 
            s_cursor_x_pos_reg <= s_next_x_pos( 5 DOWNTO 0 );
255 
         END IF;
256 
      END IF;
257 
   END PROCESS make_cursor_x_pos_reg;
258 
 
259 
   make_cursor_y_pos_reg : PROCESS( clock , reset , data_in , s_vga_state_reg ,
260 
                                    n_data_valid_in , s_my_write_burst_active_reg ,
261 
                                    bus_address )
262 
   BEGIN
263 
      IF (clock'event AND (clock = '1')) THEN
264 
         IF (s_vga_state_reg = INIT_CLEAR_SCREEN OR
265 
             reset = '1') THEN s_cursor_y_pos_reg <= (OTHERS => '0');
266 
         ELSIF (n_data_valid_in = '0' AND
267 
                s_my_write_burst_active_reg = '1' AND
268 
                bus_address( 3 DOWNTO 0 ) = X"3") THEN
269 
            s_cursor_y_pos_reg <= data_in( 4 DOWNTO 0 );
270 
         ELSIF (s_next_x_pos(6) = '1' AND
271 
                s_next_y_pos(5) = '0') THEN
272 
            s_cursor_y_pos_reg <= s_next_y_pos( 4 DOWNTO 0 );
273 
         END IF;
274 
      END IF;
275 
   END PROCESS make_cursor_y_pos_reg;
276 
 
277 
   make_screen_offset_reg : PROCESS( clock , reset , s_vga_state_reg )
278 
   BEGIN
279 
      IF (clock'event AND (clock = '1')) THEN
280 
         IF (s_vga_state_reg = INIT_CLEAR_SCREEN OR
281 
             reset = '1') THEN s_screen_offset_reg <= (OTHERS => '0');
282 
         ELSIF (s_next_x_pos(6) = '1' AND
283 
                s_next_y_pos(5) = '1') THEN
284 
            s_screen_offset_reg <= unsigned(s_screen_offset_reg) + 1;
285 
         END IF;
286 
      END IF;
287 
   END PROCESS make_screen_offset_reg;
288 
 
289 
   make_clear_screen_cnt_reg : PROCESS( clock , reset , s_vga_state_reg )
290 
   BEGIN
291 
      IF (clock'event AND (clock = '1')) THEN
292 
         IF (s_vga_state_reg = INIT_CLEAR_SCREEN) THEN
293 
            s_clear_screen_cnt_reg <= (11 => '0' , OTHERS => '1');
294 
         ELSIF (s_vga_state_reg = INIT_CLEAR_LINE) THEN
295 
            s_clear_screen_cnt_reg <= "000000111111";
296 
         ELSIF (s_clear_screen_cnt_reg(11) = '1' OR
297 
                reset = '1') THEN
298 
            s_clear_screen_cnt_reg <= "100000000000";
299 
         ELSIF (s_clear_screen_cnt_reg(11) = '0') THEN
300 
            s_clear_screen_cnt_reg <= unsigned(s_clear_screen_cnt_reg) - 1;
301 
         END IF;
302 
      END IF;
303 
   END PROCESS make_clear_screen_cnt_reg;
304 
 
305 
   make_vga_state_machine : PROCESS( clock , reset , s_vga_state_reg )
306 
      VARIABLE v_next_state : VGA_STATE_TYPE;
307 
   BEGIN
308 
      CASE (s_vga_state_reg) IS
309 
         WHEN IDLE               => IF (n_data_valid_in = '0' AND
310 
                                        s_my_write_burst_active_reg = '1' AND
311 
                                        bus_address(3 DOWNTO 0) = X"5") THEN
312 
                                       v_next_state := INIT_CLEAR_SCREEN;
313 
                                    ELSIF (s_next_x_pos(6) = '1' AND
314 
                                           s_next_y_pos(5) = '1') THEN
315 
                                       v_next_state := INIT_CLEAR_LINE;
316 
                                                                        ELSE
317 
                                       v_next_state := IDLE;
318 
                                    END IF;
319 
         WHEN INIT_CLEAR_SCREEN  => v_next_state := CLEAR_SCREEN;
320 
         WHEN CLEAR_SCREEN       => IF (s_clear_screen_cnt_reg(11) = '1') THEN
321 
                                       v_next_state := IDLE;
322 
                                                                          ELSE
323 
                                       v_next_state := CLEAR_SCREEN;
324 
                                    END IF;
325 
         WHEN INIT_CLEAR_LINE    => v_next_state := CLEAR_SCREEN;
326 
         WHEN OTHERS             => v_next_state := IDLE;
327 
      END CASE;
328 
      IF (clock'event AND (clock = '1')) THEN
329 
         IF (reset = '1') THEN s_vga_state_reg <= IDLE;
330 
                          ELSE s_vga_state_reg <= v_next_state;
331 
         END IF;
332 
      END IF;
333 
   END PROCESS make_vga_state_machine;
334 
 
335 
--------------------------------------------------------------------------------
336 
--- Here the led control is defined                                          ---
337 
--------------------------------------------------------------------------------
338 
   make_led_0_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
339 
                                  n_data_valid_in , s_my_write_burst_active_reg )
340 
   BEGIN
341 
      IF (clock'event AND (clock = '1')) THEN
342 
         IF (reset = '1' OR
343 
             n_bus_reset = '0') THEN s_led_0_mode_reg <= X"0";
344 
         ELSIF (n_data_valid_in = '0' AND
345 
                bus_address( 3 DOWNTO 0) = X"8" AND
346 
                s_my_write_burst_active_reg = '1') THEN
347 
            s_led_0_mode_reg <= data_in(3 DOWNTO 0);
348 
         END IF;
349 
      END IF;
350 
   END PROCESS make_led_0_mode_reg;
351 
 
352 
   make_led_1_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
353 
                                  n_data_valid_in , s_my_write_burst_active_reg )
354 
   BEGIN
355 
      IF (clock'event AND (clock = '1')) THEN
356 
         IF (reset = '1' OR
357 
             n_bus_reset = '0') THEN s_led_1_mode_reg <= X"0";
358 
         ELSIF (n_data_valid_in = '0' AND
359 
                bus_address( 3 DOWNTO 0) = X"9" AND
360 
                s_my_write_burst_active_reg = '1') THEN
361 
            s_led_1_mode_reg <= data_in(3 DOWNTO 0);
362 
         END IF;
363 
      END IF;
364 
   END PROCESS make_led_1_mode_reg;
365 
 
366 
   make_led_2_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
367 
                                  n_data_valid_in , s_my_write_burst_active_reg )
368 
   BEGIN
369 
      IF (clock'event AND (clock = '1')) THEN
370 
         IF (reset = '1' OR
371 
             n_bus_reset = '0') THEN s_led_2_mode_reg <= X"0";
372 
         ELSIF (n_data_valid_in = '0' AND
373 
                bus_address( 3 DOWNTO 0) = X"A" AND
374 
                s_my_write_burst_active_reg = '1') THEN
375 
            s_led_2_mode_reg <= data_in(3 DOWNTO 0);
376 
         END IF;
377 
      END IF;
378 
   END PROCESS make_led_2_mode_reg;
379 
 
380 
   make_led_3_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
381 
                                  n_data_valid_in , s_my_write_burst_active_reg )
382 
   BEGIN
383 
      IF (clock'event AND (clock = '1')) THEN
384 
         IF (reset = '1' OR
385 
             n_bus_reset = '0') THEN s_led_3_mode_reg <= X"0";
386 
         ELSIF (n_data_valid_in = '0' AND
387 
                bus_address( 3 DOWNTO 0) = X"B" AND
388 
                s_my_write_burst_active_reg = '1') THEN
389 
            s_led_3_mode_reg <= data_in(3 DOWNTO 0);
390 
         END IF;
391 
      END IF;
392 
   END PROCESS make_led_3_mode_reg;
393 
 
394 
   make_led_4_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
395 
                                  n_data_valid_in , s_my_write_burst_active_reg )
396 
   BEGIN
397 
      IF (clock'event AND (clock = '1')) THEN
398 
         IF (reset = '1' OR
399 
             n_bus_reset = '0') THEN s_led_4_mode_reg <= X"0";
400 
         ELSIF (n_data_valid_in = '0' AND
401 
                bus_address( 3 DOWNTO 0) = X"C" AND
402 
                s_my_write_burst_active_reg = '1') THEN
403 
            s_led_4_mode_reg <= data_in(3 DOWNTO 0);
404 
         END IF;
405 
      END IF;
406 
   END PROCESS make_led_4_mode_reg;
407 
 
408 
   make_led_5_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
409 
                                  n_data_valid_in , s_my_write_burst_active_reg )
410 
   BEGIN
411 
      IF (clock'event AND (clock = '1')) THEN
412 
         IF (reset = '1' OR
413 
             n_bus_reset = '0') THEN s_led_5_mode_reg <= X"0";
414 
         ELSIF (n_data_valid_in = '0' AND
415 
                bus_address( 3 DOWNTO 0) = X"D" AND
416 
                s_my_write_burst_active_reg = '1') THEN
417 
            s_led_5_mode_reg <= data_in(3 DOWNTO 0);
418 
         END IF;
419 
      END IF;
420 
   END PROCESS make_led_5_mode_reg;
421 
 
422 
   make_led_6_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
423 
                                  n_data_valid_in , s_my_write_burst_active_reg )
424 
   BEGIN
425 
      IF (clock'event AND (clock = '1')) THEN
426 
         IF (reset = '1' OR
427 
             n_bus_reset = '0') THEN s_led_6_mode_reg <= X"0";
428 
         ELSIF (n_data_valid_in = '0' AND
429 
                bus_address( 3 DOWNTO 0) = X"E" AND
430 
                s_my_write_burst_active_reg = '1') THEN
431 
            s_led_6_mode_reg <= data_in(3 DOWNTO 0);
432 
         END IF;
433 
      END IF;
434 
   END PROCESS make_led_6_mode_reg;
435 
 
436 
   make_led_7_mode_reg : PROCESS( clock , reset , bus_address , data_in ,
437 
                                  n_data_valid_in , s_my_write_burst_active_reg )
438 
   BEGIN
439 
      IF (clock'event AND (clock = '1')) THEN
440 
         IF (reset = '1' OR
441 
             n_bus_reset = '0') THEN s_led_7_mode_reg <= X"0";
442 
         ELSIF (n_data_valid_in = '0' AND
443 
                bus_address( 3 DOWNTO 0) = X"F" AND
444 
                s_my_write_burst_active_reg = '1') THEN
445 
            s_led_7_mode_reg <= data_in(3 DOWNTO 0);
446 
         END IF;
447 
      END IF;
448 
   END PROCESS make_led_7_mode_reg;
449 
 
450 
   make_led_delay_cnt_reg : PROCESS( clock , reset , msec_tick )
451 
   BEGIN
452 
      IF (clock'event AND (clock = '1')) THEN
453 
         IF ((msec_tick = '1' AND
454 
              s_led_delay_cnt_reg = X"00") OR
455 
             reset = '1') THEN s_led_delay_cnt_reg <= X"7C";
456 
         ELSIF (msec_tick = '1') THEN
457 
            s_led_delay_cnt_reg <= unsigned(s_led_delay_cnt_reg) - 1;
458 
         END IF;
459 
      END IF;
460 
   END PROCESS make_led_delay_cnt_reg;
461 
 
462 
   make_led_blink_cnt_reg : PROCESS( clock , reset , msec_tick ,
463 
                                     s_led_delay_cnt_reg )
464 
   BEGIN
465 
      IF (clock'event AND (clock = '1')) THEN
466 
         IF (reset = '1') THEN s_led_blink_cnt_reg <= "000";
467 
         ELSIF (msec_tick = '1' AND
468 
                s_led_delay_cnt_reg = X"00") THEN
469 
            s_led_blink_cnt_reg <= unsigned(s_led_blink_cnt_reg) + 1;
470 
         END IF;
471 
      END IF;
472 
   END PROCESS make_led_blink_cnt_reg;
473 
 
474 
   make_led_0 : PROCESS( s_led_0_mode_reg , s_led_blink_cnt_reg )
475 
   BEGIN
476 
      CASE (s_led_0_mode_reg) IS
477 
         WHEN  X"2"  |
478 
               X"A"  => leds_a(0) <= '0';
479 
                        leds_k(0) <= '1';
480 
         WHEN  X"3"  |
481 
               X"B"  => leds_a(0) <= '1';
482 
                        leds_k(0) <= '0';
483 
         WHEN  X"4"  => leds_a(0) <= '0';
484 
                        leds_k(0) <= s_led_blink_cnt_reg(2);
485 
         WHEN  X"5"  => leds_a(0) <= s_led_blink_cnt_reg(2);
486 
                        leds_k(0) <= '0';
487 
         WHEN  X"6"  |
488 
               X"7"  => leds_a(0) <= s_led_blink_cnt_reg(2);
489 
                        leds_k(0) <= NOT(s_led_blink_cnt_reg(2));
490 
         WHEN  X"C"  => leds_a(0) <= '0';
491 
                        leds_k(0) <= s_led_blink_cnt_reg(0);
492 
         WHEN  X"D"  => leds_a(0) <= s_led_blink_cnt_reg(0);
493 
                        leds_k(0) <= '0';
494 
         WHEN  X"E"  |
495 
               X"F"  => leds_a(0) <= s_led_blink_cnt_reg(0);
496 
                        leds_k(0) <= NOT(s_led_blink_cnt_reg(0));
497 
         WHEN OTHERS => leds_a(0) <= '0';
498 
                        leds_k(0) <= '0';
499 
      END CASE;
500 
   END PROCESS make_led_0;
501 
 
502 
   make_led_1 : PROCESS( s_led_1_mode_reg , s_led_blink_cnt_reg )
503 
   BEGIN
504 
      CASE (s_led_1_mode_reg) IS
505 
         WHEN  X"2"  |
506 
               X"A"  => leds_a(1) <= '0';
507 
                        leds_k(1) <= '1';
508 
         WHEN  X"3"  |
509 
               X"B"  => leds_a(1) <= '1';
510 
                        leds_k(1) <= '0';
511 
         WHEN  X"4"  => leds_a(1) <= '0';
512 
                        leds_k(1) <= s_led_blink_cnt_reg(2);
513 
         WHEN  X"5"  => leds_a(1) <= s_led_blink_cnt_reg(2);
514 
                        leds_k(1) <= '0';
515 
         WHEN  X"6"  |
516 
               X"7"  => leds_a(1) <= s_led_blink_cnt_reg(2);
517 
                        leds_k(1) <= NOT(s_led_blink_cnt_reg(2));
518 
         WHEN  X"C"  => leds_a(1) <= '0';
519 
                        leds_k(1) <= s_led_blink_cnt_reg(0);
520 
         WHEN  X"D"  => leds_a(1) <= s_led_blink_cnt_reg(0);
521 
                        leds_k(1) <= '0';
522 
         WHEN  X"E"  |
523 
               X"F"  => leds_a(1) <= s_led_blink_cnt_reg(0);
524 
                        leds_k(1) <= NOT(s_led_blink_cnt_reg(0));
525 
         WHEN OTHERS => leds_a(1) <= '0';
526 
                        leds_k(1) <= '0';
527 
      END CASE;
528 
   END PROCESS make_led_1;
529 
 
530 
   make_led_2 : PROCESS( s_led_2_mode_reg , s_led_blink_cnt_reg )
531 
   BEGIN
532 
      CASE (s_led_2_mode_reg) IS
533 
         WHEN  X"2"  |
534 
               X"A"  => leds_a(2) <= '0';
535 
                        leds_k(2) <= '1';
536 
         WHEN  X"3"  |
537 
               X"B"  => leds_a(2) <= '1';
538 
                        leds_k(2) <= '0';
539 
         WHEN  X"4"  => leds_a(2) <= '0';
540 
                        leds_k(2) <= s_led_blink_cnt_reg(2);
541 
         WHEN  X"5"  => leds_a(2) <= s_led_blink_cnt_reg(2);
542 
                        leds_k(2) <= '0';
543 
         WHEN  X"6"  |
544 
               X"7"  => leds_a(2) <= s_led_blink_cnt_reg(2);
545 
                        leds_k(2) <= NOT(s_led_blink_cnt_reg(2));
546 
         WHEN  X"C"  => leds_a(2) <= '0';
547 
                        leds_k(2) <= s_led_blink_cnt_reg(0);
548 
         WHEN  X"D"  => leds_a(2) <= s_led_blink_cnt_reg(0);
549 
                        leds_k(2) <= '0';
550 
         WHEN  X"E"  |
551 
               X"F"  => leds_a(2) <= s_led_blink_cnt_reg(0);
552 
                        leds_k(2) <= NOT(s_led_blink_cnt_reg(0));
553 
         WHEN OTHERS => leds_a(2) <= '0';
554 
                        leds_k(2) <= '0';
555 
      END CASE;
556 
   END PROCESS make_led_2;
557 
 
558 
   make_led_3 : PROCESS( s_led_3_mode_reg , s_led_blink_cnt_reg )
559 
   BEGIN
560 
      CASE (s_led_3_mode_reg) IS
561 
         WHEN  X"2"  |
562 
               X"A"  => leds_a(3) <= '0';
563 
                        leds_k(3) <= '1';
564 
         WHEN  X"3"  |
565 
               X"B"  => leds_a(3) <= '1';
566 
                        leds_k(3) <= '0';
567 
         WHEN  X"4"  => leds_a(3) <= '0';
568 
                        leds_k(3) <= s_led_blink_cnt_reg(2);
569 
         WHEN  X"5"  => leds_a(3) <= s_led_blink_cnt_reg(2);
570 
                        leds_k(3) <= '0';
571 
         WHEN  X"6"  |
572 
               X"7"  => leds_a(3) <= s_led_blink_cnt_reg(2);
573 
                        leds_k(3) <= NOT(s_led_blink_cnt_reg(2));
574 
         WHEN  X"C"  => leds_a(3) <= '0';
575 
                        leds_k(3) <= s_led_blink_cnt_reg(0);
576 
         WHEN  X"D"  => leds_a(3) <= s_led_blink_cnt_reg(0);
577 
                        leds_k(3) <= '0';
578 
         WHEN  X"E"  |
579 
               X"F"  => leds_a(3) <= s_led_blink_cnt_reg(0);
580 
                        leds_k(3) <= NOT(s_led_blink_cnt_reg(0));
581 
         WHEN OTHERS => leds_a(3) <= '0';
582 
                        leds_k(3) <= '0';
583 
      END CASE;
584 
   END PROCESS make_led_3;
585 
 
586 
   make_led_4 : PROCESS( s_led_4_mode_reg , s_led_blink_cnt_reg )
587 
   BEGIN
588 
      CASE (s_led_4_mode_reg) IS
589 
         WHEN  X"2"  |
590 
               X"A"  => leds_a(4) <= '0';
591 
                        leds_k(4) <= '1';
592 
         WHEN  X"3"  |
593 
               X"B"  => leds_a(4) <= '1';
594 
                        leds_k(4) <= '0';
595 
         WHEN  X"4"  => leds_a(4) <= '0';
596 
                        leds_k(4) <= s_led_blink_cnt_reg(2);
597 
         WHEN  X"5"  => leds_a(4) <= s_led_blink_cnt_reg(2);
598 
                        leds_k(4) <= '0';
599 
         WHEN  X"6"  |
600 
               X"7"  => leds_a(4) <= s_led_blink_cnt_reg(2);
601 
                        leds_k(4) <= NOT(s_led_blink_cnt_reg(2));
602 
         WHEN  X"C"  => leds_a(4) <= '0';
603 
                        leds_k(4) <= s_led_blink_cnt_reg(0);
604 
         WHEN  X"D"  => leds_a(4) <= s_led_blink_cnt_reg(0);
605 
                        leds_k(4) <= '0';
606 
         WHEN  X"E"  |
607 
               X"F"  => leds_a(4) <= s_led_blink_cnt_reg(0);
608 
                        leds_k(4) <= NOT(s_led_blink_cnt_reg(0));
609 
         WHEN OTHERS => leds_a(4) <= '0';
610 
                        leds_k(4) <= '0';
611 
      END CASE;
612 
   END PROCESS make_led_4;
613 
 
614 
   make_led_5 : PROCESS( s_led_5_mode_reg , s_led_blink_cnt_reg )
615 
   BEGIN
616 
      CASE (s_led_5_mode_reg) IS
617 
         WHEN  X"2"  |
618 
               X"A"  => leds_a(5) <= '0';
619 
                        leds_k(5) <= '1';
620 
         WHEN  X"3"  |
621 
               X"B"  => leds_a(5) <= '1';
622 
                        leds_k(5) <= '0';
623 
         WHEN  X"4"  => leds_a(5) <= '0';
624 
                        leds_k(5) <= s_led_blink_cnt_reg(2);
625 
         WHEN  X"5"  => leds_a(5) <= s_led_blink_cnt_reg(2);
626 
                        leds_k(5) <= '0';
627 
         WHEN  X"6"  |
628 
               X"7"  => leds_a(5) <= s_led_blink_cnt_reg(2);
629 
                        leds_k(5) <= NOT(s_led_blink_cnt_reg(2));
630 
         WHEN  X"C"  => leds_a(5) <= '0';
631 
                        leds_k(5) <= s_led_blink_cnt_reg(0);
632 
         WHEN  X"D"  => leds_a(5) <= s_led_blink_cnt_reg(0);
633 
                        leds_k(5) <= '0';
634 
         WHEN  X"E"  |
635 
               X"F"  => leds_a(5) <= s_led_blink_cnt_reg(0);
636 
                        leds_k(5) <= NOT(s_led_blink_cnt_reg(0));
637 
         WHEN OTHERS => leds_a(5) <= '0';
638 
                        leds_k(5) <= '0';
639 
      END CASE;
640 
   END PROCESS make_led_5;
641 
 
642 
   make_led_6 : PROCESS( s_led_6_mode_reg , s_led_blink_cnt_reg )
643 
   BEGIN
644 
      CASE (s_led_6_mode_reg) IS
645 
         WHEN  X"2"  |
646 
               X"A"  => leds_a(6) <= '0';
647 
                        leds_k(6) <= '1';
648 
         WHEN  X"3"  |
649 
               X"B"  => leds_a(6) <= '1';
650 
                        leds_k(6) <= '0';
651 
         WHEN  X"4"  => leds_a(6) <= '0';
652 
                        leds_k(6) <= s_led_blink_cnt_reg(2);
653 
         WHEN  X"5"  => leds_a(6) <= s_led_blink_cnt_reg(2);
654 
                        leds_k(6) <= '0';
655 
         WHEN  X"6"  |
656 
               X"7"  => leds_a(6) <= s_led_blink_cnt_reg(2);
657 
                        leds_k(6) <= NOT(s_led_blink_cnt_reg(2));
658 
         WHEN  X"C"  => leds_a(6) <= '0';
659 
                        leds_k(6) <= s_led_blink_cnt_reg(0);
660 
         WHEN  X"D"  => leds_a(6) <= s_led_blink_cnt_reg(0);
661 
                        leds_k(6) <= '0';
662 
         WHEN  X"E"  |
663 
               X"F"  => leds_a(6) <= s_led_blink_cnt_reg(0);
664 
                        leds_k(6) <= NOT(s_led_blink_cnt_reg(0));
665 
         WHEN OTHERS => leds_a(6) <= '0';
666 
                        leds_k(6) <= '0';
667 
      END CASE;
668 
   END PROCESS make_led_6;
669 
 
670 
   make_led_7 : PROCESS( s_led_7_mode_reg , s_led_blink_cnt_reg )
671 
   BEGIN
672 
      CASE (s_led_7_mode_reg) IS
673 
         WHEN  X"2"  |
674 
               X"A"  => leds_a(7) <= '0';
675 
                        leds_k(7) <= '1';
676 
         WHEN  X"3"  |
677 
               X"B"  => leds_a(7) <= '1';
678 
                        leds_k(7) <= '0';
679 
         WHEN  X"4"  => leds_a(7) <= '0';
680 
                        leds_k(7) <= s_led_blink_cnt_reg(2);
681 
         WHEN  X"5"  => leds_a(7) <= s_led_blink_cnt_reg(2);
682 
                        leds_k(7) <= '0';
683 
         WHEN  X"6"  |
684 
               X"7"  => leds_a(7) <= s_led_blink_cnt_reg(2);
685 
                        leds_k(7) <= NOT(s_led_blink_cnt_reg(2));
686 
         WHEN  X"C"  => leds_a(7) <= '0';
687 
                        leds_k(7) <= s_led_blink_cnt_reg(0);
688 
         WHEN  X"D"  => leds_a(7) <= s_led_blink_cnt_reg(0);
689 
                        leds_k(7) <= '0';
690 
         WHEN  X"E"  |
691 
               X"F"  => leds_a(7) <= s_led_blink_cnt_reg(0);
692 
                        leds_k(7) <= NOT(s_led_blink_cnt_reg(0));
693 
         WHEN OTHERS => leds_a(7) <= '0';
694 
                        leds_k(7) <= '0';
695 
      END CASE;
696 
   END PROCESS make_led_7;
697 
 
698 
END no_target_specific;

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