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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: 3.6.1
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// \ \ Application: MIG
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// / / Filename: ddr2_phy_dqs_iob.v
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// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
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// \ \ / \ Date Created: Wed Aug 16 2006
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// \___\/\___\
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//
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//Device: Virtex-5
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//Design Name: DDR2
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//Purpose:
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// This module places the data strobes in the IOBs.
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//Reference:
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//Revision History:
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// Rev 1.1 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
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// Rev 1.2 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
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// on IODELAY primitives. PK. 11/27/08
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// Rev 1.3 - IDDR primitve (u_iddr_dq_ce) is replaced with a negative-edge
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// triggered flip-flop. PK. 03/20/09
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// Rev 1.4 - To fix CR 540201, S and syn_preserve attributes are added
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// for dqs_oe_n_r. PK. 01/08/10
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//*****************************************************************************
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`timescale 1ns/1ps
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module ddr2_phy_dqs_iob #
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(
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// Following parameters are for 72-bit RDIMM design (for ML561 Reference
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// board design). Actual values may be different. Actual parameters values
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// are passed from design top module MEMCtrl module. Please refer to
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// the MEMCtrl module for actual values.
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parameter DDR_TYPE = 1,
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parameter HIGH_PERFORMANCE_MODE = "TRUE",
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parameter IODELAY_GRP = "IODELAY_MIG"
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)
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(
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input clk0,
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input clkdiv0,
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input rst0,
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input dlyinc_dqs,
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input dlyce_dqs,
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input dlyrst_dqs,
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input dlyinc_gate,
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input dlyce_gate,
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input dlyrst_gate,
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input dqs_oe_n,
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input dqs_rst_n,
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input en_dqs,
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inout ddr_dqs,
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inout ddr_dqs_n,
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output dq_ce,
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output delayed_dqs
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);
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wire clk180;
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wire dqs_bufio;
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wire dqs_ibuf;
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wire dqs_idelay;
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wire dqs_oe_n_delay;
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(* S = "TRUE" *) wire dqs_oe_n_r /* synthesis syn_preserve = 1*/;
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wire dqs_rst_n_delay;
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reg dqs_rst_n_r /* synthesis syn_preserve = 1*/;
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wire dqs_out;
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wire en_dqs_sync /* synthesis syn_keep = 1 */;
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// for simulation only. Synthesis should ignore this delay
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localparam DQS_NET_DELAY = 0.8;
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assign clk180 = ~clk0;
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// add delta delay to inputs clocked by clk180 to avoid delta-delay
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// simulation issues
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assign dqs_rst_n_delay = dqs_rst_n;
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assign dqs_oe_n_delay = dqs_oe_n;
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//***************************************************************************
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// DQS input-side resources:
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// - IODELAY (pad -> IDELAY)
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// - BUFIO (IDELAY -> BUFIO)
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//***************************************************************************
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// Route DQS from PAD to IDELAY
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(* IODELAY_GROUP = IODELAY_GRP *) IODELAY #
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(
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.DELAY_SRC("I"),
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.IDELAY_TYPE("VARIABLE"),
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.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
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.IDELAY_VALUE(0),
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.ODELAY_VALUE(0)
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)
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u_idelay_dqs
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(
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.DATAOUT (dqs_idelay),
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.C (clkdiv0),
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.CE (dlyce_dqs),
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.DATAIN (),
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.IDATAIN (dqs_ibuf),
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.INC (dlyinc_dqs),
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.ODATAIN (),
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.RST (dlyrst_dqs),
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.T ()
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);
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// From IDELAY to BUFIO
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BUFIO u_bufio_dqs
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(
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.I (dqs_idelay),
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.O (dqs_bufio)
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);
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// To model additional delay of DQS BUFIO + gating network
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// for behavioral simulation. Make sure to select a delay number smaller
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// than half clock cycle (otherwise output will not track input changes
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// because of inertial delay). Duplicate to avoid delta delay issues.
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assign #(DQS_NET_DELAY) i_delayed_dqs = dqs_bufio;
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assign #(DQS_NET_DELAY) delayed_dqs = dqs_bufio;
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//***************************************************************************
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// DQS gate circuit (not supported for all controllers)
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//***************************************************************************
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// Gate routing:
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// en_dqs -> IDELAY -> en_dqs_sync -> IDDR.S -> dq_ce ->
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// capture IDDR.CE
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// Delay CE control so that it's in phase with delayed DQS
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(* IODELAY_GROUP = IODELAY_GRP *) IODELAY #
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(
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.DELAY_SRC ("DATAIN"),
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.IDELAY_TYPE ("VARIABLE"),
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.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
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.IDELAY_VALUE (0),
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.ODELAY_VALUE (0)
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)
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u_iodelay_dq_ce
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(
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.DATAOUT (en_dqs_sync),
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.C (clkdiv0),
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.CE (dlyce_gate),
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.DATAIN (en_dqs),
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.IDATAIN (),
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.INC (dlyinc_gate),
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.ODATAIN (),
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.RST (dlyrst_gate),
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.T ()
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);
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// Generate sync'ed CE to DQ IDDR's using a negative-edge triggered flip-flop
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// clocked by DQS. This flop should be locked to the IOB flip-flop at the same
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// site as IODELAY u_idelay_dqs in order to use the dedicated route from
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// the IODELAY to flip-flop (to keep this route as short as possible)
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(* IOB = "FORCE" *) FDCPE_1 #
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(
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.INIT(1'b0)
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)
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u_iddr_dq_ce
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(
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.Q (dq_ce),
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.C (i_delayed_dqs),
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.CE (1'b1),
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.CLR (1'b0),
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.D (en_dqs_sync),
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.PRE (en_dqs_sync)
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) /* synthesis syn_useioff = 1 */
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/* synthesis syn_replicate = 0 */;
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//***************************************************************************
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// DQS output-side resources
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//***************************************************************************
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// synthesis attribute keep of dqs_rst_n_r is "true"
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always @(posedge clk180)
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dqs_rst_n_r <= dqs_rst_n_delay;
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ODDR #
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(
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.SRTYPE("SYNC"),
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.DDR_CLK_EDGE("OPPOSITE_EDGE")
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)
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u_oddr_dqs
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(
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.Q (dqs_out),
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.C (clk180),
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.CE (1'b1),
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.D1 (dqs_rst_n_r), // keep output deasserted for write preamble
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.D2 (1'b0),
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.R (1'b0),
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.S (1'b0)
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);
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(* IOB = "FORCE" *) FDP u_tri_state_dqs
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(
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.D (dqs_oe_n_delay),
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.Q (dqs_oe_n_r),
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.C (clk180),
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.PRE (rst0)
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) /* synthesis syn_useioff = 1 */;
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//***************************************************************************
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// use either single-ended (for DDR1) or differential (for DDR2) DQS input
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generate
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if (DDR_TYPE > 0) begin: gen_dqs_iob_ddr2
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IOBUFDS u_iobuf_dqs
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(
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.O (dqs_ibuf),
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.IO (ddr_dqs),
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.IOB (ddr_dqs_n),
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.I (dqs_out),
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.T (dqs_oe_n_r)
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);
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end else begin: gen_dqs_iob_ddr1
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IOBUF u_iobuf_dqs
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(
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.O (dqs_ibuf),
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.IO (ddr_dqs),
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.I (dqs_out),
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.T (dqs_oe_n_r)
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);
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end
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endgenerate
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endmodule
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