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pas. |
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" INIT_FILE="gnextrapolator.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="M512" WIDTH_A=16 WIDTHAD_A=5 WRCONTROL_ACLR_A="NONE" address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 9.1SP2 cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END
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-- Copyright (C) 1991-2010 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
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21 |
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WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = M512 1
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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27 |
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SUBDESIGN altsyncram_uv61
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(
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29 |
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address_a[4..0] : input;
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30 |
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clock0 : input;
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31 |
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q_a[15..0] : output;
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)
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VARIABLE
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34 |
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ram_block1a0 : stratixii_ram_block
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WITH (
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36 |
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CONNECTIVITY_CHECKING = "OFF",
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INIT_FILE = "gnextrapolator.mif",
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INIT_FILE_LAYOUT = "port_a",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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40 |
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OPERATION_MODE = "rom",
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PORT_A_ADDRESS_WIDTH = 5,
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PORT_A_DATA_OUT_CLEAR = "none",
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PORT_A_DATA_OUT_CLOCK = "none",
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PORT_A_DATA_WIDTH = 1,
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45 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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PORT_A_FIRST_ADDRESS = 0,
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48 |
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PORT_A_FIRST_BIT_NUMBER = 0,
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49 |
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PORT_A_LAST_ADDRESS = 31,
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50 |
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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RAM_BLOCK_TYPE = "M512"
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);
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ram_block1a1 : stratixii_ram_block
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WITH (
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56 |
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CONNECTIVITY_CHECKING = "OFF",
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INIT_FILE = "gnextrapolator.mif",
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INIT_FILE_LAYOUT = "port_a",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "rom",
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PORT_A_ADDRESS_WIDTH = 5,
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62 |
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PORT_A_DATA_OUT_CLEAR = "none",
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63 |
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PORT_A_DATA_OUT_CLOCK = "none",
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64 |
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PORT_A_DATA_WIDTH = 1,
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65 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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66 |
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PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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67 |
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PORT_A_FIRST_ADDRESS = 0,
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68 |
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PORT_A_FIRST_BIT_NUMBER = 1,
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69 |
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PORT_A_LAST_ADDRESS = 31,
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70 |
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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71 |
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PORT_A_LOGICAL_RAM_WIDTH = 16,
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RAM_BLOCK_TYPE = "M512"
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);
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ram_block1a2 : stratixii_ram_block
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WITH (
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76 |
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CONNECTIVITY_CHECKING = "OFF",
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INIT_FILE = "gnextrapolator.mif",
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78 |
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INIT_FILE_LAYOUT = "port_a",
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79 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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OPERATION_MODE = "rom",
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PORT_A_ADDRESS_WIDTH = 5,
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82 |
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PORT_A_DATA_OUT_CLEAR = "none",
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83 |
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PORT_A_DATA_OUT_CLOCK = "none",
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84 |
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PORT_A_DATA_WIDTH = 1,
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85 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
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86 |
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PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
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87 |
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PORT_A_FIRST_ADDRESS = 0,
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88 |
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PORT_A_FIRST_BIT_NUMBER = 2,
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89 |
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PORT_A_LAST_ADDRESS = 31,
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90 |
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PORT_A_LOGICAL_RAM_DEPTH = 32,
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91 |
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PORT_A_LOGICAL_RAM_WIDTH = 16,
|
92 |
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RAM_BLOCK_TYPE = "M512"
|
93 |
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);
|
94 |
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ram_block1a3 : stratixii_ram_block
|
95 |
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WITH (
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96 |
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CONNECTIVITY_CHECKING = "OFF",
|
97 |
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INIT_FILE = "gnextrapolator.mif",
|
98 |
|
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INIT_FILE_LAYOUT = "port_a",
|
99 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
100 |
|
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OPERATION_MODE = "rom",
|
101 |
|
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PORT_A_ADDRESS_WIDTH = 5,
|
102 |
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PORT_A_DATA_OUT_CLEAR = "none",
|
103 |
|
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PORT_A_DATA_OUT_CLOCK = "none",
|
104 |
|
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PORT_A_DATA_WIDTH = 1,
|
105 |
|
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
106 |
|
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PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
107 |
|
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PORT_A_FIRST_ADDRESS = 0,
|
108 |
|
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PORT_A_FIRST_BIT_NUMBER = 3,
|
109 |
|
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PORT_A_LAST_ADDRESS = 31,
|
110 |
|
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PORT_A_LOGICAL_RAM_DEPTH = 32,
|
111 |
|
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PORT_A_LOGICAL_RAM_WIDTH = 16,
|
112 |
|
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RAM_BLOCK_TYPE = "M512"
|
113 |
|
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);
|
114 |
|
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ram_block1a4 : stratixii_ram_block
|
115 |
|
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WITH (
|
116 |
|
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CONNECTIVITY_CHECKING = "OFF",
|
117 |
|
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INIT_FILE = "gnextrapolator.mif",
|
118 |
|
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INIT_FILE_LAYOUT = "port_a",
|
119 |
|
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
120 |
|
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OPERATION_MODE = "rom",
|
121 |
|
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PORT_A_ADDRESS_WIDTH = 5,
|
122 |
|
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PORT_A_DATA_OUT_CLEAR = "none",
|
123 |
|
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PORT_A_DATA_OUT_CLOCK = "none",
|
124 |
|
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PORT_A_DATA_WIDTH = 1,
|
125 |
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
126 |
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PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
127 |
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PORT_A_FIRST_ADDRESS = 0,
|
128 |
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PORT_A_FIRST_BIT_NUMBER = 4,
|
129 |
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PORT_A_LAST_ADDRESS = 31,
|
130 |
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PORT_A_LOGICAL_RAM_DEPTH = 32,
|
131 |
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PORT_A_LOGICAL_RAM_WIDTH = 16,
|
132 |
|
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RAM_BLOCK_TYPE = "M512"
|
133 |
|
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);
|
134 |
|
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ram_block1a5 : stratixii_ram_block
|
135 |
|
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WITH (
|
136 |
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CONNECTIVITY_CHECKING = "OFF",
|
137 |
|
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INIT_FILE = "gnextrapolator.mif",
|
138 |
|
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INIT_FILE_LAYOUT = "port_a",
|
139 |
|
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
140 |
|
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OPERATION_MODE = "rom",
|
141 |
|
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PORT_A_ADDRESS_WIDTH = 5,
|
142 |
|
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PORT_A_DATA_OUT_CLEAR = "none",
|
143 |
|
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PORT_A_DATA_OUT_CLOCK = "none",
|
144 |
|
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PORT_A_DATA_WIDTH = 1,
|
145 |
|
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PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
146 |
|
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PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
147 |
|
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PORT_A_FIRST_ADDRESS = 0,
|
148 |
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
149 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
150 |
|
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PORT_A_LOGICAL_RAM_DEPTH = 32,
|
151 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
152 |
|
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RAM_BLOCK_TYPE = "M512"
|
153 |
|
|
);
|
154 |
|
|
ram_block1a6 : stratixii_ram_block
|
155 |
|
|
WITH (
|
156 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
157 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
158 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
159 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
160 |
|
|
OPERATION_MODE = "rom",
|
161 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
162 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
163 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
164 |
|
|
PORT_A_DATA_WIDTH = 1,
|
165 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
166 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
167 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
168 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
169 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
170 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
171 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
172 |
|
|
RAM_BLOCK_TYPE = "M512"
|
173 |
|
|
);
|
174 |
|
|
ram_block1a7 : stratixii_ram_block
|
175 |
|
|
WITH (
|
176 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
177 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
178 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
179 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
180 |
|
|
OPERATION_MODE = "rom",
|
181 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
182 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
183 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
184 |
|
|
PORT_A_DATA_WIDTH = 1,
|
185 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
186 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
187 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
188 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
189 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
190 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
191 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
192 |
|
|
RAM_BLOCK_TYPE = "M512"
|
193 |
|
|
);
|
194 |
|
|
ram_block1a8 : stratixii_ram_block
|
195 |
|
|
WITH (
|
196 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
197 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
198 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
199 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
200 |
|
|
OPERATION_MODE = "rom",
|
201 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
202 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
203 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
204 |
|
|
PORT_A_DATA_WIDTH = 1,
|
205 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
206 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
207 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
208 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
209 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
210 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
211 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
212 |
|
|
RAM_BLOCK_TYPE = "M512"
|
213 |
|
|
);
|
214 |
|
|
ram_block1a9 : stratixii_ram_block
|
215 |
|
|
WITH (
|
216 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
217 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
218 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
219 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
220 |
|
|
OPERATION_MODE = "rom",
|
221 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
222 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
223 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
224 |
|
|
PORT_A_DATA_WIDTH = 1,
|
225 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
226 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
227 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
228 |
|
|
PORT_A_FIRST_BIT_NUMBER = 9,
|
229 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
230 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
231 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
232 |
|
|
RAM_BLOCK_TYPE = "M512"
|
233 |
|
|
);
|
234 |
|
|
ram_block1a10 : stratixii_ram_block
|
235 |
|
|
WITH (
|
236 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
237 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
238 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
239 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
240 |
|
|
OPERATION_MODE = "rom",
|
241 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
242 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
243 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
244 |
|
|
PORT_A_DATA_WIDTH = 1,
|
245 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
246 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
247 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
248 |
|
|
PORT_A_FIRST_BIT_NUMBER = 10,
|
249 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
250 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
251 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
252 |
|
|
RAM_BLOCK_TYPE = "M512"
|
253 |
|
|
);
|
254 |
|
|
ram_block1a11 : stratixii_ram_block
|
255 |
|
|
WITH (
|
256 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
257 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
258 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
259 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
260 |
|
|
OPERATION_MODE = "rom",
|
261 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
262 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
263 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
264 |
|
|
PORT_A_DATA_WIDTH = 1,
|
265 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
266 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
267 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
268 |
|
|
PORT_A_FIRST_BIT_NUMBER = 11,
|
269 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
270 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
271 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
272 |
|
|
RAM_BLOCK_TYPE = "M512"
|
273 |
|
|
);
|
274 |
|
|
ram_block1a12 : stratixii_ram_block
|
275 |
|
|
WITH (
|
276 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
277 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
278 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
279 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
280 |
|
|
OPERATION_MODE = "rom",
|
281 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
282 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
283 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
284 |
|
|
PORT_A_DATA_WIDTH = 1,
|
285 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
286 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
287 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
288 |
|
|
PORT_A_FIRST_BIT_NUMBER = 12,
|
289 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
290 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
291 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
292 |
|
|
RAM_BLOCK_TYPE = "M512"
|
293 |
|
|
);
|
294 |
|
|
ram_block1a13 : stratixii_ram_block
|
295 |
|
|
WITH (
|
296 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
297 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
298 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
299 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
300 |
|
|
OPERATION_MODE = "rom",
|
301 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
302 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
303 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
304 |
|
|
PORT_A_DATA_WIDTH = 1,
|
305 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
306 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
307 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
308 |
|
|
PORT_A_FIRST_BIT_NUMBER = 13,
|
309 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
310 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
311 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
312 |
|
|
RAM_BLOCK_TYPE = "M512"
|
313 |
|
|
);
|
314 |
|
|
ram_block1a14 : stratixii_ram_block
|
315 |
|
|
WITH (
|
316 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
317 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
318 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
319 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
320 |
|
|
OPERATION_MODE = "rom",
|
321 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
322 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
323 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
324 |
|
|
PORT_A_DATA_WIDTH = 1,
|
325 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
326 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
327 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
328 |
|
|
PORT_A_FIRST_BIT_NUMBER = 14,
|
329 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
330 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
331 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
332 |
|
|
RAM_BLOCK_TYPE = "M512"
|
333 |
|
|
);
|
334 |
|
|
ram_block1a15 : stratixii_ram_block
|
335 |
|
|
WITH (
|
336 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
337 |
|
|
INIT_FILE = "gnextrapolator.mif",
|
338 |
|
|
INIT_FILE_LAYOUT = "port_a",
|
339 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
340 |
|
|
OPERATION_MODE = "rom",
|
341 |
|
|
PORT_A_ADDRESS_WIDTH = 5,
|
342 |
|
|
PORT_A_DATA_OUT_CLEAR = "none",
|
343 |
|
|
PORT_A_DATA_OUT_CLOCK = "none",
|
344 |
|
|
PORT_A_DATA_WIDTH = 1,
|
345 |
|
|
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
|
346 |
|
|
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
|
347 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
348 |
|
|
PORT_A_FIRST_BIT_NUMBER = 15,
|
349 |
|
|
PORT_A_LAST_ADDRESS = 31,
|
350 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 32,
|
351 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 16,
|
352 |
|
|
RAM_BLOCK_TYPE = "M512"
|
353 |
|
|
);
|
354 |
|
|
address_a_wire[4..0] : WIRE;
|
355 |
|
|
|
356 |
|
|
BEGIN
|
357 |
|
|
ram_block1a[15..0].clk0 = clock0;
|
358 |
|
|
ram_block1a[15..0].portaaddr[] = ( address_a_wire[4..0]);
|
359 |
|
|
address_a_wire[] = address_a[];
|
360 |
|
|
q_a[] = ( ram_block1a[15..0].portadataout[0..0]);
|
361 |
|
|
END;
|
362 |
|
|
--VALID FILE
|