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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_PP.vhd] - Blame information for rev 3

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:04:57 10/03/2011 
-- Design Name: 
-- Module Name:    if_func_PP - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
use work.utilPkg.all;
 
entity if_func_PP is
        port(
                -- device inputs
                clk : in std_logic; -- clock
                -- settings
                lpeUsed : std_logic;
                fixedPpLine : in std_logic_vector (2 downto 0);
                -- local commands
                pon : in std_logic; -- power on
                lpe : in std_logic; -- local poll enable
                ist : in std_logic; -- individual status
                -- state inputs
                ACDS : in std_logic; -- accept data state
                LADS : in std_logic; -- listener address state (L or LE)
                -- data input
                dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
                -- remote command inputs
                IDY : in std_logic; -- identify
                PPE : in std_logic; -- parallel poll enable
                PPD : in std_logic; -- parallel poll disable
                PPC : in std_logic; -- parallel poll configure
                PPU : in std_logic; -- parallel poll unconfigure
                PCG : in std_logic; -- primary command group
                -- remote command outputs
                PPR : out std_logic; -- paralel poll response
                -- PPR command data
                ppBitValue : out std_logic; -- bit value
                ppLineNumber : out std_logic_vector (2 downto 0);
                -- reported states
                PPAS : out std_logic -- parallel poll active state
        );
end if_func_PP;
 
architecture Behavioral of if_func_PP is
 
        -- states
        type PP_STATE_1 is (
                -- parallel poll idle state
                ST_PPIS,
                -- parallel poll standby state
                ST_PPSS,
                -- parallel poll active state
                ST_PPAS
        );
 
        -- states
        type PP_STATE_2 is (
                -- parallel poll unaddressed to configure state
                ST_PUCS,
                -- parallel poll addressed to configure state
                ST_PACS
        );
 
        -- current state
        signal current_state_1 : PP_STATE_1;
        signal current_state_2 : PP_STATE_2;
 
        -- predicates
        signal pred1, pred2, pred3, pred4, pred5 : boolean;
 
        -- memorized PP metadata
        signal S : std_logic;
        signal lineAddr : std_logic_vector (2 downto 0);
 
begin
 
        -- state machine process - PP_STATE_1
        process(pon, clk) begin
                if pon = '1' then
                        current_state_1 <= ST_PPIS;
                elsif rising_edge(clk) then
                        case current_state_1 is
                                ------------------
                                when ST_PPIS =>
                                        if pred1 then
                                                S <= dio_data(3);
                                                lineAddr <= dio_data(2 downto 0);
                                                current_state_1 <= ST_PPSS;
                                        end if;
                                ------------------
                                when ST_PPSS =>
                                        if pred3 then
                                                current_state_1 <= ST_PPAS;
                                        elsif pred2 then
                                                current_state_1 <= ST_PPIS;
                                        end if;
                                ------------------
                                when ST_PPAS =>
                                        if not pred3 then
                                                current_state_1 <= ST_PPSS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_1 <= ST_PPIS;
                        end case;
                end if;
        end process;
 
        -- state machine process - PP_STATE_2
        process(pon, clk) begin
                if pon = '1' then
                        current_state_2 <= ST_PUCS;
                elsif rising_edge(clk) then
                        case current_state_2 is
                                ------------------
                                when ST_PUCS =>
                                        if pred4 then
                                                current_state_2 <= ST_PACS;
                                        end if;
                                ------------------
                                when ST_PACS =>
                                        if pred5 then
                                                current_state_2 <= ST_PUCS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_2 <= ST_PUCS;
                        end case;
                end if;
        end process;
 
        ppBitValue <= (not S xor ist) when lpeUsed='0' else ist;
        ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine;
        PPR <= to_stdl(current_state_1 = ST_PPAS);
        PPAS <= to_stdl(current_state_1 = ST_PPAS);
 
        -- predicates
        with lpeUsed select
                pred1 <=
                        is_1(lpe) when '1',
                        PPE='1' and current_state_2=ST_PACS and ACDS='1' when others;
 
        with lpeUsed select
                pred2 <=
                        is_1(not lpe) when '1',
                        ((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1'
                                when others;
 
        pred3 <= IDY='1';
        pred4 <= PPC='1' and LADS='1' and ACDS='1';
        pred5 <= PCG='1' and PPC='0' and ACDS='1';
 
 
end Behavioral;

Line No.	Rev	Author	Line
1	3	Andrewski	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 01:04:57 10/03/2011`
6			`-- Design Name:`
7			`-- Module Name: if_func_PP - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22
23			`use work.utilPkg.all;`
24
25			`entity if_func_PP is`
26			`port(`
27			`-- device inputs`
28			`clk : in std_logic; -- clock`
29			`-- settings`
30			`lpeUsed : std_logic;`
31			`fixedPpLine : in std_logic_vector (2 downto 0);`
32			`-- local commands`
33			`pon : in std_logic; -- power on`
34			`lpe : in std_logic; -- local poll enable`
35			`ist : in std_logic; -- individual status`
36			`-- state inputs`
37			`ACDS : in std_logic; -- accept data state`
38			`LADS : in std_logic; -- listener address state (L or LE)`
39			`-- data input`
40			`dio_data : in std_logic_vector(3 downto 0); -- byte from data lines`
41			`-- remote command inputs`
42			`IDY : in std_logic; -- identify`
43			`PPE : in std_logic; -- parallel poll enable`
44			`PPD : in std_logic; -- parallel poll disable`
45			`PPC : in std_logic; -- parallel poll configure`
46			`PPU : in std_logic; -- parallel poll unconfigure`
47			`PCG : in std_logic; -- primary command group`
48			`-- remote command outputs`
49			`PPR : out std_logic; -- paralel poll response`
50			`-- PPR command data`
51			`ppBitValue : out std_logic; -- bit value`
52			`ppLineNumber : out std_logic_vector (2 downto 0);`
53			`-- reported states`
54			`PPAS : out std_logic -- parallel poll active state`
55			`);`
56			`end if_func_PP;`
57
58			`architecture Behavioral of if_func_PP is`
59
60			`-- states`
61			`type PP_STATE_1 is (`
62			`-- parallel poll idle state`
63			`ST_PPIS,`
64			`-- parallel poll standby state`
65			`ST_PPSS,`
66			`-- parallel poll active state`
67			`ST_PPAS`
68			`);`
69
70			`-- states`
71			`type PP_STATE_2 is (`
72			`-- parallel poll unaddressed to configure state`
73			`ST_PUCS,`
74			`-- parallel poll addressed to configure state`
75			`ST_PACS`
76			`);`
77
78			`-- current state`
79			`signal current_state_1 : PP_STATE_1;`
80			`signal current_state_2 : PP_STATE_2;`
81
82			`-- predicates`
83			`signal pred1, pred2, pred3, pred4, pred5 : boolean;`
84
85			`-- memorized PP metadata`
86			`signal S : std_logic;`
87			`signal lineAddr : std_logic_vector (2 downto 0);`
88
89			`begin`
90
91			`-- state machine process - PP_STATE_1`
92			`process(pon, clk) begin`
93			`if pon = '1' then`
94			`current_state_1 <= ST_PPIS;`
95			`elsif rising_edge(clk) then`
96			`case current_state_1 is`
97			`------------------`
98			`when ST_PPIS =>`
99			`if pred1 then`
100			`S <= dio_data(3);`
101			`lineAddr <= dio_data(2 downto 0);`
102			`current_state_1 <= ST_PPSS;`
103			`end if;`
104			`------------------`
105			`when ST_PPSS =>`
106			`if pred3 then`
107			`current_state_1 <= ST_PPAS;`
108			`elsif pred2 then`
109			`current_state_1 <= ST_PPIS;`
110			`end if;`
111			`------------------`
112			`when ST_PPAS =>`
113			`if not pred3 then`
114			`current_state_1 <= ST_PPSS;`
115			`end if;`
116			`------------------`
117			`when others =>`
118			`current_state_1 <= ST_PPIS;`
119			`end case;`
120			`end if;`
121			`end process;`
122
123			`-- state machine process - PP_STATE_2`
124			`process(pon, clk) begin`
125			`if pon = '1' then`
126			`current_state_2 <= ST_PUCS;`
127			`elsif rising_edge(clk) then`
128			`case current_state_2 is`
129			`------------------`
130			`when ST_PUCS =>`
131			`if pred4 then`
132			`current_state_2 <= ST_PACS;`
133			`end if;`
134			`------------------`
135			`when ST_PACS =>`
136			`if pred5 then`
137			`current_state_2 <= ST_PUCS;`
138			`end if;`
139			`------------------`
140			`when others =>`
141			`current_state_2 <= ST_PUCS;`
142			`end case;`
143			`end if;`
144			`end process;`
145
146			`ppBitValue <= (not S xor ist) when lpeUsed='0' else ist;`
147			`ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine;`
148			`PPR <= to_stdl(current_state_1 = ST_PPAS);`
149			`PPAS <= to_stdl(current_state_1 = ST_PPAS);`
150
151			`-- predicates`
152			`with lpeUsed select`
153			`pred1 <=`
154			`is_1(lpe) when '1',`
155			`PPE='1' and current_state_2=ST_PACS and ACDS='1' when others;`
156
157			`with lpeUsed select`
158			`pred2 <=`
159			`is_1(not lpe) when '1',`
160			`((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1'`
161			`when others;`
162
163			`pred3 <= IDY='1';`
164			`pred4 <= PPC='1' and LADS='1' and ACDS='1';`
165			`pred5 <= PCG='1' and PPC='0' and ACDS='1';`
166
167
168			`end Behavioral;`

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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_PP.vhd] - Blame information for rev 3