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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_RL.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 3 Andrewski 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    01:04:57 10/03/2011
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-- Design Name:
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-- Module Name:    if_func_RL - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.utilPkg.all;
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entity if_func_RL is
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        port(
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                -- device inputs
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                clk : in std_logic; -- clock
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                pon : in std_logic; -- power on
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                rtl : in std_logic; -- return to local
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                -- state inputs
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                ACDS : in std_logic; -- listener active state (AH)
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                LADS : in std_logic; -- listener addressed state (L or LE)
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                -- instructions
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                REN : in std_logic; -- remote enable
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                LLO : in std_logic; -- local lockout
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                MLA : in std_logic; -- my listen address
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                GTL : in std_logic; -- go to local
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                -- reported state
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                LOCS : out std_logic; -- local state
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                LWLS : out std_logic -- local with lockout state
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        );
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end if_func_RL;
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architecture Behavioral of if_func_RL is
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        -- states
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        type RL_STATE is (
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                -- local state
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                ST_LOCS,
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                -- remote state
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                ST_REMS,
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                -- local with lockout state
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                ST_LWLS,
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                -- remote with lockout state
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                ST_RWLS
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        );
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        -- current state
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        signal current_state : RL_STATE;
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        -- events
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        signal event0, event1, event2, event3, event4, event5 : boolean;
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begin
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        -- state machine process
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        process(pon, clk) begin
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                if pon = '1' then
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                        current_state <= ST_LOCS;
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                elsif rising_edge(clk) then
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                        case current_state is
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                                ------------------
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                                when ST_LOCS =>
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                                        if event0 then
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                                                -- no state change
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                                        elsif event1 then
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                                                current_state <= ST_REMS;
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                                        elsif event3 then
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                                                current_state <= ST_LWLS;
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                                        end if;
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                                ------------------
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                                when ST_REMS =>
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                                        if event0 then
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                                                current_state <= ST_LOCS;
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                                        elsif event2 then
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                                                current_state <= ST_LOCS;
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                                        elsif event3 then
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                                                current_state <= ST_RWLS;
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                                        end if;
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                                ------------------
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                                when ST_RWLS =>
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                                        if event0 then
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                                                current_state <= ST_LOCS;
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                                        elsif event5 then
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                                                current_state <= ST_LWLS;
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                                        end if;
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                                ------------------
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                                when ST_LWLS =>
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                                        if event0 then
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                                                current_state <= ST_LOCS;
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                                        elsif event4 then
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                                                current_state <= ST_RWLS;
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                                        end if;
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                                ------------------
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                                when others =>
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                                        current_state <= ST_LOCS;
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                        end case;
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                end if;
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        end process;
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        -- events
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        event0 <= REN='0';
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        event1 <= rtl='0' and MLA='1' and ACDS='1';
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        event2 <=
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                (GTL='1' and LADS='1' and ACDS='1') or
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                (rtl='1' and not(LLO='1' and ACDS='1'));
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        event3 <= LLO='1' and ACDS='1';
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        event4 <= MLA='1' and ACDS='1';
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        event5 <= GTL='1' and LADS='1' and ACDS='1';
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        -- reported states
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        LOCS <= to_stdl(current_state = ST_LOCS);
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        LWLS <= to_stdl(current_state = ST_LWLS);
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end Behavioral;
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