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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib_helper/] [EdgeDetector.vhd] - Blame information for rev 3

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1 3 Andrewski
--------------------------------------------------------------------------------
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-- Entity: EdgeDetector
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-- Date:2011-11-25  
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-- Author: Administrator     
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--
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.helperComponents.all;
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entity EdgeDetector is
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        generic (
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                RISING : std_logic := '1';
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                FALLING : std_logic := '0';
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                PULSE_WIDTH : integer := 10
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        );
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        port (
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                reset : in std_logic;
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                clk : in std_logic;
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                in_data : in std_logic;
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                pulse : out std_logic
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        );
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end EdgeDetector;
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architecture arch of EdgeDetector is
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        signal t_i, t_o : std_logic;
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        signal lastData : std_logic;
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begin
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        process(reset, clk, t_o, in_data) begin
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                if reset = '1' then
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                        t_i <= t_o;
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                        lastData <= in_data;
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                elsif rising_edge(clk) then
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                        if lastData /= in_data then
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                                if RISING='1' and lastData='0' and in_data='1' then
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                                        t_i <= not t_o;
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                                end if;
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                                if FALLING='1' and lastData='1' and in_data='0' then
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                                        t_i <= not t_o;
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                                end if;
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                        end if;
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                        lastData <= in_data;
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                end if;
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        end process;
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        spg: SinglePulseGenerator generic map (WIDTH => PULSE_WIDTH) port map (
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                reset => reset, clk => clk, t_in => t_i, t_out => t_o, pulse => pulse
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        );
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end arch;
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