OpenCores
URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [wrapper/] [SecAddrReg.vhd] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 Andrewski
--------------------------------------------------------------------------------
2
-- Entity: SecAddrReg
3
-- Date:2011-11-09  
4
-- Author: Administrator     
5
--
6
-- Description ${cursor}
7
--------------------------------------------------------------------------------
8
library ieee;
9
use ieee.std_logic_1164.all;
10
use ieee.std_logic_unsigned.all;
11
 
12
 
13
entity SecAddrReg is
14
        port (
15
                reset : in std_logic;
16
                strobe : in std_logic;
17
                data_in : in std_logic_vector (15 downto 0);
18
                data_out : out std_logic_vector (15 downto 0);
19
                -- gpib
20
                secAddrMask : out std_logic_vector (15 downto 0)
21
        );
22
end SecAddrReg;
23
 
24
architecture arch of SecAddrReg is
25
 
26
        signal inner_buf : std_logic_vector (15 downto 0);
27
 
28
begin
29
 
30
        data_out <= inner_buf;
31
        secAddrMask <= inner_buf;
32
 
33
        process (reset, strobe) begin
34
                if reset = '1' then
35
                        inner_buf <= "0000000000000000";
36
                elsif rising_edge(strobe) then
37
                        inner_buf <= data_in;
38
                end if;
39
        end process;
40
 
41
end arch;
42
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.