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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [wrapper/] [SettingsReg1.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 3 Andrewski
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-- Entity: SettingsReg0
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-- Date:2011-11-09  
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-- Author: Administrator     
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--
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity SettingsReg1 is
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        port (
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                reset : in std_logic;
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                strobe : in std_logic;
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                data_in : in std_logic_vector (15 downto 0);
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                data_out : out std_logic_vector (15 downto 0);
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                -- gpib
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                myAddr : out std_logic_vector (4 downto 0);
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                T1 : out std_logic_vector (7 downto 0)
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        );
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end SettingsReg1;
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architecture arch of SettingsReg1 is
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        signal inner_buf : std_logic_vector (15 downto 0);
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begin
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        inner_buf(15 downto 13) <= "000";
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        data_out <= inner_buf;
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        myAddr <= inner_buf(4 downto 0);
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        T1 <= inner_buf(12 downto 5);
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        process (reset, strobe) begin
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                if reset = '1' then
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                        -- default 132*Tclk = 2uS and addr=1
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                        inner_buf(12 downto 0) <= "1000010000001";
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                elsif rising_edge(strobe) then
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                        inner_buf(12 downto 0) <= data_in(12 downto 0);
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                end if;
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        end process;
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end arch;
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