OpenCores
URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [wrapper/] [WriterControlReg1.vhd] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 Andrewski
--------------------------------------------------------------------------------
2
-- Entity: WriterControlReg1
3
-- Date:2011-11-10  
4
-- Author: Administrator     
5
--
6
-- Description ${cursor}
7
--------------------------------------------------------------------------------
8
library ieee;
9
use ieee.std_logic_1164.all;
10
use ieee.std_logic_unsigned.all;
11
 
12
 
13
entity WriterControlReg1 is
14
        port (
15
                reset : in std_logic;
16
                strobe : in std_logic;
17
                data_in : in std_logic_vector (15 downto 0);
18
                data_out : out std_logic_vector (15 downto 0);
19
                ------------------ gpib --------------------
20
                -- num of bytes available in fifo
21
                bytes_available_in_fifo : in std_logic_vector (10 downto 0)
22
        );
23
end WriterControlReg1;
24
 
25
architecture arch of WriterControlReg1 is
26
 
27
begin
28
 
29
        data_out(10 downto 0) <= bytes_available_in_fifo(10 downto 0);
30
        data_out(15 downto 11) <= "00000";
31
 
32
end arch;
33
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.