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[/] [gpib_controller/] [trunk/] [vhdl/] [test/] [gpib_DC_Test.vhd] - Blame information for rev 3

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1 3 Andrewski
--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
5
-- Create Date:   23:21:05 10/21/2011
6
-- Design Name:   
7
-- Module Name:   /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
8
-- Project Name:  usbToHpib
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: gpibInterface
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19
-- Additional Comments:
20
--
21
-- Notes: 
22
-- This testbench has been automatically generated using types std_logic and
23
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
-- that these types always be used for the top-level I/O of a design in order
25
-- to guarantee that the testbench will bind correctly to the post-implementation 
26
-- simulation model.
27
--------------------------------------------------------------------------------
28
LIBRARY ieee;
29
USE ieee.std_logic_1164.ALL;
30
USE ieee.std_logic_unsigned.all;
31
USE ieee.numeric_std.ALL;
32
 
33
use work.gpibComponents.all;
34
use work.helperComponents.all;
35
 
36
 
37
ENTITY gpib_DC_Test IS
38
END gpib_DC_Test;
39
 
40
ARCHITECTURE behavior OF gpib_DC_Test IS
41
 
42
        -- Component Declaration for the Unit Under Test (UUT)
43
 
44
        component gpibCableEmulator is port (
45
                -- interface signals
46
                DIO_1 : in std_logic_vector (7 downto 0);
47
                output_valid_1 : in std_logic;
48
                DIO_2 : in std_logic_vector (7 downto 0);
49
                output_valid_2 : in std_logic;
50
                DIO : out std_logic_vector (7 downto 0);
51
                -- attention
52
                ATN_1 : in std_logic;
53
                ATN_2 : in std_logic;
54
                ATN : out std_logic;
55
                -- data valid
56
                DAV_1 : in std_logic;
57
                DAV_2 : in std_logic;
58
                DAV : out std_logic;
59
                -- not ready for data
60
                NRFD_1 : in std_logic;
61
                NRFD_2 : in std_logic;
62
                NRFD : out std_logic;
63
                -- no data accepted
64
                NDAC_1 : in std_logic;
65
                NDAC_2 : in std_logic;
66
                NDAC : out std_logic;
67
                -- end or identify
68
                EOI_1 : in std_logic;
69
                EOI_2 : in std_logic;
70
                EOI : out std_logic;
71
                -- service request
72
                SRQ_1 : in std_logic;
73
                SRQ_2 : in std_logic;
74
                SRQ : out std_logic;
75
                -- interface clear
76
                IFC_1 : in std_logic;
77
                IFC_2 : in std_logic;
78
                IFC : out std_logic;
79
                -- remote enable
80
                REN_1 : in std_logic;
81
                REN_2 : in std_logic;
82
                REN : out std_logic
83
        );
84
        end component;
85
 
86
        -- inputs common
87
        signal clk : std_logic := '0';
88
        signal reset : std_logic := '0';
89
        signal T1 : std_logic_vector(7 downto 0) := "00000100";
90
 
91
        -- inputs 1
92
        signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
93
        signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
94
        signal rdy_1 : std_logic := '0';
95
        signal nba_1 : std_logic := '0';
96
        signal ltn_1 : std_logic := '0';
97
        signal lun_1 : std_logic := '0';
98
        signal lon_1 : std_logic := '0';
99
        signal ton_1 : std_logic := '0';
100
        signal endOf_1 : std_logic := '0';
101
        signal gts_1 : std_logic := '0';
102
        signal rpp_1 : std_logic := '0';
103
        signal tcs_1 : std_logic := '0';
104
        signal tca_1 : std_logic := '0';
105
        signal sic_1 : std_logic := '0';
106
        signal rsc_1 : std_logic := '0';
107
        signal sre_1 : std_logic := '0';
108
        signal rtl_1 : std_logic := '0';
109
        signal rsv_1 : std_logic := '0';
110
        signal ist_1 : std_logic := '0';
111
        signal lpe_1 : std_logic := '0';
112
 
113
        -- inputs 2
114
        signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
115
        signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
116
        signal rdy_2 : std_logic := '0';
117
        signal nba_2 : std_logic := '0';
118
        signal ltn_2 : std_logic := '0';
119
        signal lun_2 : std_logic := '0';
120
        signal lon_2 : std_logic := '0';
121
        signal ton_2 : std_logic := '0';
122
        signal endOf_2 : std_logic := '0';
123
        signal gts_2 : std_logic := '0';
124
        signal rpp_2 : std_logic := '0';
125
        signal tcs_2 : std_logic := '0';
126
        signal tca_2 : std_logic := '0';
127
        signal sic_2 : std_logic := '0';
128
        signal rsc_2 : std_logic := '0';
129
        signal sre_2 : std_logic := '0';
130
        signal rtl_2 : std_logic := '0';
131
        signal rsv_2 : std_logic := '0';
132
        signal ist_2 : std_logic := '0';
133
        signal lpe_2 : std_logic := '0';
134
 
135
        -- outputs 1
136
        signal dvd_1 : std_logic;
137
        signal wnc_1 : std_logic;
138
        signal tac_1 : std_logic;
139
        signal cwrc_1 : std_logic;
140
        signal cwrd_1 : std_logic;
141
        signal clr_1 : std_logic;
142
        signal trg_1 : std_logic;
143
        signal atl_1 : std_logic;
144
        signal att_1 : std_logic;
145
        signal mla_1 : std_logic;
146
        signal lsb_1 : std_logic;
147
        signal spa_1 : std_logic;
148
        signal ppr_1 : std_logic;
149
        signal sreq_1 : std_logic;
150
        signal isLocal_1 : std_logic;
151
        signal currentSecAddr_1 : std_logic_vector (4 downto 0);
152
 
153
        -- outputs 2
154
        signal dvd_2 : std_logic;
155
        signal wnc_2 : std_logic;
156
        signal tac_2 : std_logic;
157
        signal cwrc_2 : std_logic;
158
        signal cwrd_2 : std_logic;
159
        signal clr_2 : std_logic;
160
        signal trg_2 : std_logic;
161
        signal atl_2 : std_logic;
162
        signal att_2 : std_logic;
163
        signal mla_2 : std_logic;
164
        signal lsb_2 : std_logic;
165
        signal spa_2 : std_logic;
166
        signal ppr_2 : std_logic;
167
        signal sreq_2 : std_logic;
168
        signal isLocal_2 : std_logic;
169
        signal currentSecAddr_2 : std_logic_vector (4 downto 0);
170
 
171
        -- common
172
        signal DO : std_logic_vector (7 downto 0);
173
        signal DI_1 : std_logic_vector (7 downto 0);
174
        signal output_valid_1 : std_logic;
175
        signal DI_2 : std_logic_vector (7 downto 0);
176
        signal output_valid_2 : std_logic;
177
        signal ATN_1, ATN_2, ATN : std_logic;
178
        signal DAV_1, DAV_2, DAV : std_logic;
179
        signal NRFD_1, NRFD_2, NRFD : std_logic;
180
        signal NDAC_1, NDAC_2, NDAC : std_logic;
181
        signal EOI_1, EOI_2, EOI : std_logic;
182
        signal SRQ_1, SRQ_2, SRQ : std_logic;
183
        signal IFC_1, IFC_2, IFC : std_logic;
184
        signal REN_1, REN_2, REN : std_logic;
185
 
186
        -- gpib reader
187
        signal buf_interrupt : std_logic;
188
        signal data_available : std_logic;
189
        signal last_byte_addr : std_logic_vector (3 downto 0);
190
        signal end_of_stream : std_logic;
191
        signal byte_addr : std_logic_vector (3 downto 0);
192
        signal data_out : std_logic_vector (7 downto 0);
193
        signal reset_buffer : std_logic := '0';
194
        signal dataSecAddr : std_logic_vector (4 downto 0);
195
 
196
        -- gpib writer
197
        signal w_last_byte_addr : std_logic_vector (3 downto 0)
198
                := (others => '0');
199
        signal w_end_of_stream : std_logic := '0';
200
        signal w_data_available : std_logic := '0';
201
        signal w_buf_interrupt : std_logic;
202
        signal w_data_in : std_logic_vector (7 downto 0);
203
        signal w_byte_addr : std_logic_vector (3 downto 0);
204
        signal w_reset_buffer : std_logic := '0';
205
        type WR_BUF_TYPE is
206
                array (0 to 15) of std_logic_vector (7 downto 0);
207
        signal w_write_buffer : WR_BUF_TYPE;
208
 
209
        -- Clock period definitions
210
        constant clk_period : time := 2ps;
211
 
212
BEGIN
213
 
214
        -- Instantiate the Unit Under Test (UUT)
215
        gpib1: gpibInterface PORT MAP (
216
                clk => clk,
217
                reset => reset,
218
                isLE => '0',
219
                isTE => '0',
220
                lpeUsed => '0',
221
                fixedPpLine => "000",
222
                eosUsed => '0',
223
                eosMark => "00000000",
224
                myListAddr => "00001",
225
                myTalkAddr => "00001",
226
                secAddrMask => (others => '0'),
227
                data => data_1,
228
                status_byte => status_byte_1,
229
                T1 => T1,
230
                rdy => rdy_1,
231
                nba => nba_1,
232
                ltn => ltn_1,
233
                lun => lun_1,
234
                lon => lon_1,
235
                ton => ton_1,
236
                endOf => endOf_1,
237
                gts => gts_1,
238
                rpp => rpp_1,
239
                tcs => tcs_1,
240
                tca => tca_1,
241
                sic => sic_1,
242
                rsc => rsc_1,
243
                sre => sre_1,
244
                rtl => rtl_1,
245
                rsv => rsv_1,
246
                ist => ist_1,
247
                lpe => lpe_1,
248
                dvd => dvd_1,
249
                wnc => wnc_1,
250
                tac => tac_1,
251
                cwrc => cwrc_1,
252
                cwrd => cwrd_1,
253
                clr => clr_1,
254
                trg => trg_1,
255
                atl => atl_1,
256
                att => att_1,
257
                mla => mla_1,
258
                lsb => lsb_1,
259
                spa => spa_1,
260
                ppr => ppr_1,
261
                sreq => sreq_1,
262
                isLocal => isLocal_1,
263
                currentSecAddr => currentSecAddr_1,
264
                DI => DO,
265
                DO => DI_1,
266
                output_valid => output_valid_1,
267
                ATN_in => ATN,
268
                ATN_out => ATN_1,
269
                DAV_in => DAV,
270
                DAV_out => DAV_1,
271
                NRFD_in => NRFD,
272
                NRFD_out => NRFD_1,
273
                NDAC_in => NDAC,
274
                NDAC_out => NDAC_1,
275
                EOI_in => EOI,
276
                EOI_out => EOI_1,
277
                SRQ_in => SRQ,
278
                SRQ_out => SRQ_1,
279
                IFC_in => IFC,
280
                IFC_out => IFC_1,
281
                REN_in => REN,
282
                REN_out => REN_1
283
                );
284
 
285
        -- Instantiate the Unit Under Test (UUT)
286
        gpib2: gpibInterface PORT MAP (
287
                clk => clk,
288
                reset => reset,
289
                isLE => '0',
290
                isTE => '0',
291
                lpeUsed => '0',
292
                fixedPpLine => "000",
293
                eosUsed => '0',
294
                eosMark => "00000000",
295
                myListAddr => "00010",
296
                myTalkAddr => "00010",
297
                secAddrMask => (others => '0'),
298
                data => data_2,
299
                status_byte => status_byte_2,
300
                T1 => T1,
301
                rdy => rdy_2,
302
                nba => nba_2,
303
                ltn => ltn_2,
304
                lun => lun_2,
305
                lon => lon_2,
306
                ton => ton_2,
307
                endOf => endOf_2,
308
                gts => gts_2,
309
                rpp => rpp_2,
310
                tcs => tcs_2,
311
                tca => tca_2,
312
                sic => sic_2,
313
                rsc => rsc_2,
314
                sre => sre_2,
315
                rtl => rtl_2,
316
                rsv => rsv_2,
317
                ist => ist_2,
318
                lpe => lpe_2,
319
                dvd => dvd_2,
320
                wnc => wnc_2,
321
                tac => tac_2,
322
                cwrc => cwrc_2,
323
                cwrd => cwrd_2,
324
                clr => clr_2,
325
                trg => trg_2,
326
                atl => atl_2,
327
                att => att_2,
328
                mla => mla_2,
329
                lsb => lsb_2,
330
                spa => spa_2,
331
                ppr => ppr_2,
332
                sreq => sreq_2,
333
                isLocal => isLocal_2,
334
                currentSecAddr => currentSecAddr_2,
335
                DI => DO,
336
                DO => DI_2,
337
                output_valid => output_valid_2,
338
                ATN_in => ATN,
339
                ATN_out => ATN_2,
340
                DAV_in => DAV,
341
                DAV_out => DAV_2,
342
                NRFD_in => NRFD,
343
                NRFD_out => NRFD_2,
344
                NDAC_in => NDAC,
345
                NDAC_out => NDAC_2,
346
                EOI_in => EOI,
347
                EOI_out => EOI_2,
348
                SRQ_in => SRQ,
349
                SRQ_out => SRQ_2,
350
                IFC_in => IFC,
351
                IFC_out => IFC_2,
352
                REN_in => REN,
353
                REN_out => REN_2
354
                );
355
 
356
        ce: gpibCableEmulator port map (
357
                -- interface signals
358
                DIO_1 => DI_1,
359
                output_valid_1 => output_valid_1,
360
                DIO_2 => DI_2,
361
                output_valid_2 => output_valid_2,
362
                DIO => DO,
363
                -- attention
364
                ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
365
                DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
366
                NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
367
                NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
368
                EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
369
                SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
370
                IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
371
                REN_1 => REN_1, REN_2 => REN_2, REN => REN
372
        );
373
 
374
        gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
375
                clk => clk, reset => reset,
376
                ------------------------------------------------------------------------
377
                ------ GPIB interface --------------------------------------------------
378
                ------------------------------------------------------------------------
379
                data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
380
                ------------------------------------------------------------------------
381
                ------ external interface ----------------------------------------------
382
                ------------------------------------------------------------------------
383
                isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
384
                buf_interrupt => buf_interrupt, data_available => data_available,
385
                last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
386
                byte_addr => byte_addr, data_out => data_out,
387
                reset_buffer => reset_buffer
388
        );
389
 
390
        w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
391
 
392
        gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
393
                        clk => clk, reset => reset,
394
                        ------------------------------------------------------------------------
395
                        ------ GPIB interface --------------------------------------------------
396
                        ------------------------------------------------------------------------
397
                        data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
398
                        endOf => endOf_1, att => att_1, cwrc => cwrc_1,
399
                        ------------------------------------------------------------------------
400
                        ------ external interface ----------------------------------------------
401
                        ------------------------------------------------------------------------
402
                        isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
403
                        last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
404
                        data_available => w_data_available, buf_interrupt => w_buf_interrupt,
405
                        data_in => w_data_in, byte_addr => w_byte_addr,
406
                        reset_buffer => w_reset_buffer
407
                );
408
 
409
        -- Clock process definitions
410
        clk_process :process
411
        begin
412
                clk <= '0';
413
                wait for clk_period/2;
414
                clk <= '1';
415
                wait for clk_period/2;
416
        end process;
417
 
418
 
419
        -- Stimulus process
420
        stim_proc: process
421
        begin
422
                -- hold reset state for 10 clock periods.
423
                reset <= '1';
424
                wait for clk_period*10;
425
                reset <= '0';
426
                wait for clk_period*10;
427
 
428
                -- requests system control
429
                rsc_1 <= '1';
430
 
431
                -- interface clear
432
                sic_1 <= '1';
433
                wait until IFC_1 = '1';
434
                sic_1 <= '0';
435
                wait until IFC_1 = '0';
436
 
437
                assert clr_2 = '0';
438
 
439
                -- send DCL (device clear)
440
                w_write_buffer(0) <= "00010100";
441
                w_last_byte_addr <= "0000";
442
                w_data_available <= '1';
443
 
444
                wait until w_buf_interrupt='1';
445
 
446
                assert clr_1 = '1';
447
                assert clr_2 = '1';
448
 
449
                w_reset_buffer <= '1';
450
                wait for clk_period*2;
451
                w_reset_buffer <= '0';
452
 
453
                -- send SDC (selected device clear)
454
                w_write_buffer(0) <= "00000100";
455
                w_last_byte_addr <= "0000";
456
                w_data_available <= '1';
457
 
458
                wait until w_buf_interrupt='1';
459
 
460
                wait for clk_period*2;
461
 
462
                assert clr_1 = '0';
463
                assert clr_2 = '0';
464
 
465
                w_reset_buffer <= '1';
466
                wait for clk_period*2;
467
                w_reset_buffer <= '0';
468
 
469
                -- gpib2 to listen
470
                w_write_buffer(0) <= "00100010";
471
                w_last_byte_addr <= "0000";
472
                w_data_available <= '1';
473
 
474
                wait until w_buf_interrupt='1';
475
 
476
                wait for clk_period*2;
477
 
478
                assert clr_1 = '0';
479
                assert clr_2 = '0';
480
 
481
                w_reset_buffer <= '1';
482
                wait for clk_period*2;
483
                w_reset_buffer <= '0';
484
 
485
                -- send SDC (selected device clear)
486
                w_write_buffer(0) <= "00000100";
487
                w_last_byte_addr <= "0000";
488
                w_data_available <= '1';
489
 
490
                wait until w_buf_interrupt='1';
491
 
492
                wait for clk_period*2;
493
 
494
                assert clr_1 = '0';
495
                assert clr_2 = '1';
496
 
497
                report "$$$ END OF TEST - DC (device clear) $$$";
498
 
499
                wait;
500
        end process;
501
 
502
END;

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