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Release 13.1 Trace  (lin)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

/media/sda9/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3

-fastpaths -xml VGA_Top.twx VGA_Top.ncd -o VGA_Top.twr VGA_Top.pcf -ucf

VGA_Top.ucf

Design file:              VGA_Top.ncd

Physical constraint file: VGA_Top.pcf

Device,package,speed:     xc3s200,ft256,-5 (PRODUCTION 1.39 2011-02-03)

Report level:             verbose report

Environment Variable      Effect

--------------------      ------

NONE                      No environment variables were set

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INFO:Timing:2698 - No timing constraints found, doing default enumeration.

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths

   option. All paths that are not constrained will be reported in the

   unconstrained paths section(s) of the report.

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on

   a 50 Ohm transmission line loading model.  For the details of this model,

   and for more information on accounting for different loading conditions,

   please see the device datasheet.

INFO:Timing:3390 - This architecture does not support a default System Jitter

   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock

   Uncertainty calculation.

INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and

   'Phase Error' calculations, these terms will be zero in the Clock

   Uncertainty calculation.  Please make appropriate modification to

   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase

   Error.

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to clock Clk

------------+------------+------------+------------------+--------+

            |Max Setup to|Max Hold to |                  | Clock  |

Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |

------------+------------+------------+------------------+--------+

button      |    5.893(R)|   -0.176(R)|Clk_BUFGP         |   0.000|

inColor<0>  |    3.235(R)|   -0.422(R)|Clk_BUFGP         |   0.000|

inColor<1>  |    3.864(R)|   -0.926(R)|Clk_BUFGP         |   0.000|

inColor<2>  |    3.952(R)|   -1.232(R)|Clk_BUFGP         |   0.000|

reset       |    6.858(R)|   -0.299(R)|Clk_BUFGP         |   0.000|

------------+------------+------------+------------------+--------+

Clock Clk to Pad

------------+------------+------------------+--------+

            | clk (edge) |                  | Clock  |

Destination |   to PAD   |Internal Clock(s) | Phase  |

------------+------------+------------------+--------+

B           |   17.781(R)|Clk_BUFGP         |   0.000|

Enables<0>  |   10.183(R)|Clk_BUFGP         |   0.000|

Enables<1>  |   10.623(R)|Clk_BUFGP         |   0.000|

Enables<2>  |    9.844(R)|Clk_BUFGP         |   0.000|

Enables<3>  |   10.854(R)|Clk_BUFGP         |   0.000|

G           |   17.810(R)|Clk_BUFGP         |   0.000|

HS          |    9.257(R)|Clk_BUFGP         |   0.000|

LED         |   11.064(R)|Clk_BUFGP         |   0.000|

R           |   17.734(R)|Clk_BUFGP         |   0.000|

Segments<0> |   14.713(R)|Clk_BUFGP         |   0.000|

Segments<1> |   14.558(R)|Clk_BUFGP         |   0.000|

Segments<2> |   15.194(R)|Clk_BUFGP         |   0.000|

Segments<3> |   15.041(R)|Clk_BUFGP         |   0.000|

Segments<4> |   14.937(R)|Clk_BUFGP         |   0.000|

Segments<5> |   14.673(R)|Clk_BUFGP         |   0.000|

Segments<6> |   15.467(R)|Clk_BUFGP         |   0.000|

VS          |   10.350(R)|Clk_BUFGP         |   0.000|

------------+------------+------------------+--------+

Clock to Setup on destination clock Clk

---------------+---------+---------+---------+---------+

               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

Clk            |   12.182|         |         |         |

---------------+---------+---------+---------+---------+

Analysis completed Tue May 17 19:22:43 2011

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Trace Settings:

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Trace Settings

Peak Memory Usage: 83 MB