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ash_riple |
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used solely *
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* for design, simulation, implementation and creation of design files *
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* limited to Xilinx devices or technologies. Use with non-Xilinx *
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* devices or technologies is expressly prohibited and immediately *
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* terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
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* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
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* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
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* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
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* PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support appliances, *
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* devices, or systems. Use in such applications are expressly *
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* prohibited. *
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* *
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* (c) Copyright 1995-2013 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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// You must compile the wrapper file dcfifo_128b_16.v when simulating
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// the core, dcfifo_128b_16. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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// The synthesis directives "translate_off/translate_on" specified below are
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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`timescale 1ns/1ps
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module dcfifo_128b_16(
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rst,
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wr_clk,
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rd_clk,
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din,
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wr_en,
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rd_en,
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dout,
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full,
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empty,
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rd_data_count,
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wr_data_count
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);
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input rst;
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input wr_clk;
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input rd_clk;
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input [127 : 0] din;
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input wr_en;
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input rd_en;
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output [127 : 0] dout;
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output full;
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output empty;
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output [3 : 0] rd_data_count;
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output [3 : 0] wr_data_count;
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// synthesis translate_off
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FIFO_GENERATOR_V9_3 #(
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.C_ADD_NGC_CONSTRAINT(0),
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.C_APPLICATION_TYPE_AXIS(0),
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.C_APPLICATION_TYPE_RACH(0),
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.C_APPLICATION_TYPE_RDCH(0),
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.C_APPLICATION_TYPE_WACH(0),
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.C_APPLICATION_TYPE_WDCH(0),
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.C_APPLICATION_TYPE_WRCH(0),
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| 75 |
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.C_AXI_ADDR_WIDTH(32),
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.C_AXI_ARUSER_WIDTH(1),
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.C_AXI_AWUSER_WIDTH(1),
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.C_AXI_BUSER_WIDTH(1),
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.C_AXI_DATA_WIDTH(64),
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.C_AXI_ID_WIDTH(4),
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.C_AXI_RUSER_WIDTH(1),
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.C_AXI_TYPE(0),
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.C_AXI_WUSER_WIDTH(1),
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.C_AXIS_TDATA_WIDTH(64),
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.C_AXIS_TDEST_WIDTH(4),
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.C_AXIS_TID_WIDTH(8),
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.C_AXIS_TKEEP_WIDTH(4),
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.C_AXIS_TSTRB_WIDTH(4),
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.C_AXIS_TUSER_WIDTH(4),
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.C_AXIS_TYPE(0),
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| 91 |
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.C_COMMON_CLOCK(0),
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| 92 |
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.C_COUNT_TYPE(0),
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.C_DATA_COUNT_WIDTH(4),
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.C_DEFAULT_VALUE("BlankString"),
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.C_DIN_WIDTH(128),
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.C_DIN_WIDTH_AXIS(1),
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.C_DIN_WIDTH_RACH(32),
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.C_DIN_WIDTH_RDCH(64),
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.C_DIN_WIDTH_WACH(32),
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.C_DIN_WIDTH_WDCH(64),
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.C_DIN_WIDTH_WRCH(2),
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.C_DOUT_RST_VAL("0"),
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.C_DOUT_WIDTH(128),
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.C_ENABLE_RLOCS(0),
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.C_ENABLE_RST_SYNC(1),
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.C_ERROR_INJECTION_TYPE(0),
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.C_ERROR_INJECTION_TYPE_AXIS(0),
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.C_ERROR_INJECTION_TYPE_RACH(0),
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.C_ERROR_INJECTION_TYPE_RDCH(0),
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.C_ERROR_INJECTION_TYPE_WACH(0),
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.C_ERROR_INJECTION_TYPE_WDCH(0),
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.C_ERROR_INJECTION_TYPE_WRCH(0),
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.C_FAMILY("virtex7"),
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.C_FULL_FLAGS_RST_VAL(0),
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.C_HAS_ALMOST_EMPTY(0),
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.C_HAS_ALMOST_FULL(0),
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.C_HAS_AXI_ARUSER(0),
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.C_HAS_AXI_AWUSER(0),
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| 119 |
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.C_HAS_AXI_BUSER(0),
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| 120 |
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.C_HAS_AXI_RD_CHANNEL(0),
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.C_HAS_AXI_RUSER(0),
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.C_HAS_AXI_WR_CHANNEL(0),
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| 123 |
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.C_HAS_AXI_WUSER(0),
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| 124 |
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.C_HAS_AXIS_TDATA(0),
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.C_HAS_AXIS_TDEST(0),
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| 126 |
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.C_HAS_AXIS_TID(0),
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| 127 |
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.C_HAS_AXIS_TKEEP(0),
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| 128 |
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.C_HAS_AXIS_TLAST(0),
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| 129 |
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.C_HAS_AXIS_TREADY(1),
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| 130 |
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.C_HAS_AXIS_TSTRB(0),
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| 131 |
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.C_HAS_AXIS_TUSER(0),
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.C_HAS_BACKUP(0),
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.C_HAS_DATA_COUNT(0),
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| 134 |
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.C_HAS_DATA_COUNTS_AXIS(0),
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.C_HAS_DATA_COUNTS_RACH(0),
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.C_HAS_DATA_COUNTS_RDCH(0),
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.C_HAS_DATA_COUNTS_WACH(0),
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| 138 |
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.C_HAS_DATA_COUNTS_WDCH(0),
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.C_HAS_DATA_COUNTS_WRCH(0),
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| 140 |
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.C_HAS_INT_CLK(0),
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| 141 |
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.C_HAS_MASTER_CE(0),
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| 142 |
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.C_HAS_MEMINIT_FILE(0),
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| 143 |
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.C_HAS_OVERFLOW(0),
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| 144 |
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.C_HAS_PROG_FLAGS_AXIS(0),
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| 145 |
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.C_HAS_PROG_FLAGS_RACH(0),
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| 146 |
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.C_HAS_PROG_FLAGS_RDCH(0),
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| 147 |
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.C_HAS_PROG_FLAGS_WACH(0),
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| 148 |
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.C_HAS_PROG_FLAGS_WDCH(0),
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| 149 |
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.C_HAS_PROG_FLAGS_WRCH(0),
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| 150 |
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.C_HAS_RD_DATA_COUNT(1),
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| 151 |
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.C_HAS_RD_RST(0),
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| 152 |
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.C_HAS_RST(1),
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| 153 |
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.C_HAS_SLAVE_CE(0),
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| 154 |
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.C_HAS_SRST(0),
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| 155 |
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.C_HAS_UNDERFLOW(0),
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| 156 |
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.C_HAS_VALID(0),
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| 157 |
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.C_HAS_WR_ACK(0),
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| 158 |
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.C_HAS_WR_DATA_COUNT(1),
|
| 159 |
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.C_HAS_WR_RST(0),
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| 160 |
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.C_IMPLEMENTATION_TYPE(2),
|
| 161 |
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.C_IMPLEMENTATION_TYPE_AXIS(1),
|
| 162 |
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.C_IMPLEMENTATION_TYPE_RACH(1),
|
| 163 |
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.C_IMPLEMENTATION_TYPE_RDCH(1),
|
| 164 |
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.C_IMPLEMENTATION_TYPE_WACH(1),
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| 165 |
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.C_IMPLEMENTATION_TYPE_WDCH(1),
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| 166 |
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.C_IMPLEMENTATION_TYPE_WRCH(1),
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| 167 |
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.C_INIT_WR_PNTR_VAL(0),
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| 168 |
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.C_INTERFACE_TYPE(0),
|
| 169 |
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.C_MEMORY_TYPE(1),
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| 170 |
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.C_MIF_FILE_NAME("BlankString"),
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| 171 |
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.C_MSGON_VAL(1),
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| 172 |
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.C_OPTIMIZATION_MODE(0),
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| 173 |
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.C_OVERFLOW_LOW(0),
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| 174 |
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.C_PRELOAD_LATENCY(2),
|
| 175 |
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.C_PRELOAD_REGS(1),
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| 176 |
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.C_PRIM_FIFO_TYPE("512x72"),
|
| 177 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
| 178 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
|
| 179 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
|
| 180 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
|
| 181 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
|
| 182 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
|
| 183 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
|
| 184 |
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.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
| 185 |
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.C_PROG_EMPTY_TYPE(0),
|
| 186 |
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.C_PROG_EMPTY_TYPE_AXIS(0),
|
| 187 |
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.C_PROG_EMPTY_TYPE_RACH(0),
|
| 188 |
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.C_PROG_EMPTY_TYPE_RDCH(0),
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| 189 |
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.C_PROG_EMPTY_TYPE_WACH(0),
|
| 190 |
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.C_PROG_EMPTY_TYPE_WDCH(0),
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| 191 |
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.C_PROG_EMPTY_TYPE_WRCH(0),
|
| 192 |
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.C_PROG_FULL_THRESH_ASSERT_VAL(13),
|
| 193 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
|
| 194 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
|
| 195 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
| 196 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
|
| 197 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
| 198 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
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| 199 |
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|
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
|
| 200 |
|
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.C_PROG_FULL_TYPE(0),
|
| 201 |
|
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.C_PROG_FULL_TYPE_AXIS(0),
|
| 202 |
|
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.C_PROG_FULL_TYPE_RACH(0),
|
| 203 |
|
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.C_PROG_FULL_TYPE_RDCH(0),
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| 204 |
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.C_PROG_FULL_TYPE_WACH(0),
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| 205 |
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.C_PROG_FULL_TYPE_WDCH(0),
|
| 206 |
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.C_PROG_FULL_TYPE_WRCH(0),
|
| 207 |
|
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.C_RACH_TYPE(0),
|
| 208 |
|
|
.C_RD_DATA_COUNT_WIDTH(4),
|
| 209 |
|
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.C_RD_DEPTH(16),
|
| 210 |
|
|
.C_RD_FREQ(1),
|
| 211 |
|
|
.C_RD_PNTR_WIDTH(4),
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| 212 |
|
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.C_RDCH_TYPE(0),
|
| 213 |
|
|
.C_REG_SLICE_MODE_AXIS(0),
|
| 214 |
|
|
.C_REG_SLICE_MODE_RACH(0),
|
| 215 |
|
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.C_REG_SLICE_MODE_RDCH(0),
|
| 216 |
|
|
.C_REG_SLICE_MODE_WACH(0),
|
| 217 |
|
|
.C_REG_SLICE_MODE_WDCH(0),
|
| 218 |
|
|
.C_REG_SLICE_MODE_WRCH(0),
|
| 219 |
|
|
.C_SYNCHRONIZER_STAGE(2),
|
| 220 |
|
|
.C_UNDERFLOW_LOW(0),
|
| 221 |
|
|
.C_USE_COMMON_OVERFLOW(0),
|
| 222 |
|
|
.C_USE_COMMON_UNDERFLOW(0),
|
| 223 |
|
|
.C_USE_DEFAULT_SETTINGS(0),
|
| 224 |
|
|
.C_USE_DOUT_RST(1),
|
| 225 |
|
|
.C_USE_ECC(0),
|
| 226 |
|
|
.C_USE_ECC_AXIS(0),
|
| 227 |
|
|
.C_USE_ECC_RACH(0),
|
| 228 |
|
|
.C_USE_ECC_RDCH(0),
|
| 229 |
|
|
.C_USE_ECC_WACH(0),
|
| 230 |
|
|
.C_USE_ECC_WDCH(0),
|
| 231 |
|
|
.C_USE_ECC_WRCH(0),
|
| 232 |
|
|
.C_USE_EMBEDDED_REG(1),
|
| 233 |
|
|
.C_USE_FIFO16_FLAGS(0),
|
| 234 |
|
|
.C_USE_FWFT_DATA_COUNT(0),
|
| 235 |
|
|
.C_VALID_LOW(0),
|
| 236 |
|
|
.C_WACH_TYPE(0),
|
| 237 |
|
|
.C_WDCH_TYPE(0),
|
| 238 |
|
|
.C_WR_ACK_LOW(0),
|
| 239 |
|
|
.C_WR_DATA_COUNT_WIDTH(4),
|
| 240 |
|
|
.C_WR_DEPTH(16),
|
| 241 |
|
|
.C_WR_DEPTH_AXIS(1024),
|
| 242 |
|
|
.C_WR_DEPTH_RACH(16),
|
| 243 |
|
|
.C_WR_DEPTH_RDCH(1024),
|
| 244 |
|
|
.C_WR_DEPTH_WACH(16),
|
| 245 |
|
|
.C_WR_DEPTH_WDCH(1024),
|
| 246 |
|
|
.C_WR_DEPTH_WRCH(16),
|
| 247 |
|
|
.C_WR_FREQ(1),
|
| 248 |
|
|
.C_WR_PNTR_WIDTH(4),
|
| 249 |
|
|
.C_WR_PNTR_WIDTH_AXIS(10),
|
| 250 |
|
|
.C_WR_PNTR_WIDTH_RACH(4),
|
| 251 |
|
|
.C_WR_PNTR_WIDTH_RDCH(10),
|
| 252 |
|
|
.C_WR_PNTR_WIDTH_WACH(4),
|
| 253 |
|
|
.C_WR_PNTR_WIDTH_WDCH(10),
|
| 254 |
|
|
.C_WR_PNTR_WIDTH_WRCH(4),
|
| 255 |
|
|
.C_WR_RESPONSE_LATENCY(1),
|
| 256 |
|
|
.C_WRCH_TYPE(0)
|
| 257 |
|
|
)
|
| 258 |
|
|
inst (
|
| 259 |
|
|
.RST(rst),
|
| 260 |
|
|
.WR_CLK(wr_clk),
|
| 261 |
|
|
.RD_CLK(rd_clk),
|
| 262 |
|
|
.DIN(din),
|
| 263 |
|
|
.WR_EN(wr_en),
|
| 264 |
|
|
.RD_EN(rd_en),
|
| 265 |
|
|
.DOUT(dout),
|
| 266 |
|
|
.FULL(full),
|
| 267 |
|
|
.EMPTY(empty),
|
| 268 |
|
|
.RD_DATA_COUNT(rd_data_count),
|
| 269 |
|
|
.WR_DATA_COUNT(wr_data_count),
|
| 270 |
|
|
.BACKUP(),
|
| 271 |
|
|
.BACKUP_MARKER(),
|
| 272 |
|
|
.CLK(),
|
| 273 |
|
|
.SRST(),
|
| 274 |
|
|
.WR_RST(),
|
| 275 |
|
|
.RD_RST(),
|
| 276 |
|
|
.PROG_EMPTY_THRESH(),
|
| 277 |
|
|
.PROG_EMPTY_THRESH_ASSERT(),
|
| 278 |
|
|
.PROG_EMPTY_THRESH_NEGATE(),
|
| 279 |
|
|
.PROG_FULL_THRESH(),
|
| 280 |
|
|
.PROG_FULL_THRESH_ASSERT(),
|
| 281 |
|
|
.PROG_FULL_THRESH_NEGATE(),
|
| 282 |
|
|
.INT_CLK(),
|
| 283 |
|
|
.INJECTDBITERR(),
|
| 284 |
|
|
.INJECTSBITERR(),
|
| 285 |
|
|
.ALMOST_FULL(),
|
| 286 |
|
|
.WR_ACK(),
|
| 287 |
|
|
.OVERFLOW(),
|
| 288 |
|
|
.ALMOST_EMPTY(),
|
| 289 |
|
|
.VALID(),
|
| 290 |
|
|
.UNDERFLOW(),
|
| 291 |
|
|
.DATA_COUNT(),
|
| 292 |
|
|
.PROG_FULL(),
|
| 293 |
|
|
.PROG_EMPTY(),
|
| 294 |
|
|
.SBITERR(),
|
| 295 |
|
|
.DBITERR(),
|
| 296 |
|
|
.M_ACLK(),
|
| 297 |
|
|
.S_ACLK(),
|
| 298 |
|
|
.S_ARESETN(),
|
| 299 |
|
|
.M_ACLK_EN(),
|
| 300 |
|
|
.S_ACLK_EN(),
|
| 301 |
|
|
.S_AXI_AWID(),
|
| 302 |
|
|
.S_AXI_AWADDR(),
|
| 303 |
|
|
.S_AXI_AWLEN(),
|
| 304 |
|
|
.S_AXI_AWSIZE(),
|
| 305 |
|
|
.S_AXI_AWBURST(),
|
| 306 |
|
|
.S_AXI_AWLOCK(),
|
| 307 |
|
|
.S_AXI_AWCACHE(),
|
| 308 |
|
|
.S_AXI_AWPROT(),
|
| 309 |
|
|
.S_AXI_AWQOS(),
|
| 310 |
|
|
.S_AXI_AWREGION(),
|
| 311 |
|
|
.S_AXI_AWUSER(),
|
| 312 |
|
|
.S_AXI_AWVALID(),
|
| 313 |
|
|
.S_AXI_AWREADY(),
|
| 314 |
|
|
.S_AXI_WID(),
|
| 315 |
|
|
.S_AXI_WDATA(),
|
| 316 |
|
|
.S_AXI_WSTRB(),
|
| 317 |
|
|
.S_AXI_WLAST(),
|
| 318 |
|
|
.S_AXI_WUSER(),
|
| 319 |
|
|
.S_AXI_WVALID(),
|
| 320 |
|
|
.S_AXI_WREADY(),
|
| 321 |
|
|
.S_AXI_BID(),
|
| 322 |
|
|
.S_AXI_BRESP(),
|
| 323 |
|
|
.S_AXI_BUSER(),
|
| 324 |
|
|
.S_AXI_BVALID(),
|
| 325 |
|
|
.S_AXI_BREADY(),
|
| 326 |
|
|
.M_AXI_AWID(),
|
| 327 |
|
|
.M_AXI_AWADDR(),
|
| 328 |
|
|
.M_AXI_AWLEN(),
|
| 329 |
|
|
.M_AXI_AWSIZE(),
|
| 330 |
|
|
.M_AXI_AWBURST(),
|
| 331 |
|
|
.M_AXI_AWLOCK(),
|
| 332 |
|
|
.M_AXI_AWCACHE(),
|
| 333 |
|
|
.M_AXI_AWPROT(),
|
| 334 |
|
|
.M_AXI_AWQOS(),
|
| 335 |
|
|
.M_AXI_AWREGION(),
|
| 336 |
|
|
.M_AXI_AWUSER(),
|
| 337 |
|
|
.M_AXI_AWVALID(),
|
| 338 |
|
|
.M_AXI_AWREADY(),
|
| 339 |
|
|
.M_AXI_WID(),
|
| 340 |
|
|
.M_AXI_WDATA(),
|
| 341 |
|
|
.M_AXI_WSTRB(),
|
| 342 |
|
|
.M_AXI_WLAST(),
|
| 343 |
|
|
.M_AXI_WUSER(),
|
| 344 |
|
|
.M_AXI_WVALID(),
|
| 345 |
|
|
.M_AXI_WREADY(),
|
| 346 |
|
|
.M_AXI_BID(),
|
| 347 |
|
|
.M_AXI_BRESP(),
|
| 348 |
|
|
.M_AXI_BUSER(),
|
| 349 |
|
|
.M_AXI_BVALID(),
|
| 350 |
|
|
.M_AXI_BREADY(),
|
| 351 |
|
|
.S_AXI_ARID(),
|
| 352 |
|
|
.S_AXI_ARADDR(),
|
| 353 |
|
|
.S_AXI_ARLEN(),
|
| 354 |
|
|
.S_AXI_ARSIZE(),
|
| 355 |
|
|
.S_AXI_ARBURST(),
|
| 356 |
|
|
.S_AXI_ARLOCK(),
|
| 357 |
|
|
.S_AXI_ARCACHE(),
|
| 358 |
|
|
.S_AXI_ARPROT(),
|
| 359 |
|
|
.S_AXI_ARQOS(),
|
| 360 |
|
|
.S_AXI_ARREGION(),
|
| 361 |
|
|
.S_AXI_ARUSER(),
|
| 362 |
|
|
.S_AXI_ARVALID(),
|
| 363 |
|
|
.S_AXI_ARREADY(),
|
| 364 |
|
|
.S_AXI_RID(),
|
| 365 |
|
|
.S_AXI_RDATA(),
|
| 366 |
|
|
.S_AXI_RRESP(),
|
| 367 |
|
|
.S_AXI_RLAST(),
|
| 368 |
|
|
.S_AXI_RUSER(),
|
| 369 |
|
|
.S_AXI_RVALID(),
|
| 370 |
|
|
.S_AXI_RREADY(),
|
| 371 |
|
|
.M_AXI_ARID(),
|
| 372 |
|
|
.M_AXI_ARADDR(),
|
| 373 |
|
|
.M_AXI_ARLEN(),
|
| 374 |
|
|
.M_AXI_ARSIZE(),
|
| 375 |
|
|
.M_AXI_ARBURST(),
|
| 376 |
|
|
.M_AXI_ARLOCK(),
|
| 377 |
|
|
.M_AXI_ARCACHE(),
|
| 378 |
|
|
.M_AXI_ARPROT(),
|
| 379 |
|
|
.M_AXI_ARQOS(),
|
| 380 |
|
|
.M_AXI_ARREGION(),
|
| 381 |
|
|
.M_AXI_ARUSER(),
|
| 382 |
|
|
.M_AXI_ARVALID(),
|
| 383 |
|
|
.M_AXI_ARREADY(),
|
| 384 |
|
|
.M_AXI_RID(),
|
| 385 |
|
|
.M_AXI_RDATA(),
|
| 386 |
|
|
.M_AXI_RRESP(),
|
| 387 |
|
|
.M_AXI_RLAST(),
|
| 388 |
|
|
.M_AXI_RUSER(),
|
| 389 |
|
|
.M_AXI_RVALID(),
|
| 390 |
|
|
.M_AXI_RREADY(),
|
| 391 |
|
|
.S_AXIS_TVALID(),
|
| 392 |
|
|
.S_AXIS_TREADY(),
|
| 393 |
|
|
.S_AXIS_TDATA(),
|
| 394 |
|
|
.S_AXIS_TSTRB(),
|
| 395 |
|
|
.S_AXIS_TKEEP(),
|
| 396 |
|
|
.S_AXIS_TLAST(),
|
| 397 |
|
|
.S_AXIS_TID(),
|
| 398 |
|
|
.S_AXIS_TDEST(),
|
| 399 |
|
|
.S_AXIS_TUSER(),
|
| 400 |
|
|
.M_AXIS_TVALID(),
|
| 401 |
|
|
.M_AXIS_TREADY(),
|
| 402 |
|
|
.M_AXIS_TDATA(),
|
| 403 |
|
|
.M_AXIS_TSTRB(),
|
| 404 |
|
|
.M_AXIS_TKEEP(),
|
| 405 |
|
|
.M_AXIS_TLAST(),
|
| 406 |
|
|
.M_AXIS_TID(),
|
| 407 |
|
|
.M_AXIS_TDEST(),
|
| 408 |
|
|
.M_AXIS_TUSER(),
|
| 409 |
|
|
.AXI_AW_INJECTSBITERR(),
|
| 410 |
|
|
.AXI_AW_INJECTDBITERR(),
|
| 411 |
|
|
.AXI_AW_PROG_FULL_THRESH(),
|
| 412 |
|
|
.AXI_AW_PROG_EMPTY_THRESH(),
|
| 413 |
|
|
.AXI_AW_DATA_COUNT(),
|
| 414 |
|
|
.AXI_AW_WR_DATA_COUNT(),
|
| 415 |
|
|
.AXI_AW_RD_DATA_COUNT(),
|
| 416 |
|
|
.AXI_AW_SBITERR(),
|
| 417 |
|
|
.AXI_AW_DBITERR(),
|
| 418 |
|
|
.AXI_AW_OVERFLOW(),
|
| 419 |
|
|
.AXI_AW_UNDERFLOW(),
|
| 420 |
|
|
.AXI_AW_PROG_FULL(),
|
| 421 |
|
|
.AXI_AW_PROG_EMPTY(),
|
| 422 |
|
|
.AXI_W_INJECTSBITERR(),
|
| 423 |
|
|
.AXI_W_INJECTDBITERR(),
|
| 424 |
|
|
.AXI_W_PROG_FULL_THRESH(),
|
| 425 |
|
|
.AXI_W_PROG_EMPTY_THRESH(),
|
| 426 |
|
|
.AXI_W_DATA_COUNT(),
|
| 427 |
|
|
.AXI_W_WR_DATA_COUNT(),
|
| 428 |
|
|
.AXI_W_RD_DATA_COUNT(),
|
| 429 |
|
|
.AXI_W_SBITERR(),
|
| 430 |
|
|
.AXI_W_DBITERR(),
|
| 431 |
|
|
.AXI_W_OVERFLOW(),
|
| 432 |
|
|
.AXI_W_UNDERFLOW(),
|
| 433 |
|
|
.AXI_B_INJECTSBITERR(),
|
| 434 |
|
|
.AXI_W_PROG_FULL(),
|
| 435 |
|
|
.AXI_W_PROG_EMPTY(),
|
| 436 |
|
|
.AXI_B_INJECTDBITERR(),
|
| 437 |
|
|
.AXI_B_PROG_FULL_THRESH(),
|
| 438 |
|
|
.AXI_B_PROG_EMPTY_THRESH(),
|
| 439 |
|
|
.AXI_B_DATA_COUNT(),
|
| 440 |
|
|
.AXI_B_WR_DATA_COUNT(),
|
| 441 |
|
|
.AXI_B_RD_DATA_COUNT(),
|
| 442 |
|
|
.AXI_B_SBITERR(),
|
| 443 |
|
|
.AXI_B_DBITERR(),
|
| 444 |
|
|
.AXI_B_OVERFLOW(),
|
| 445 |
|
|
.AXI_B_UNDERFLOW(),
|
| 446 |
|
|
.AXI_AR_INJECTSBITERR(),
|
| 447 |
|
|
.AXI_B_PROG_FULL(),
|
| 448 |
|
|
.AXI_B_PROG_EMPTY(),
|
| 449 |
|
|
.AXI_AR_INJECTDBITERR(),
|
| 450 |
|
|
.AXI_AR_PROG_FULL_THRESH(),
|
| 451 |
|
|
.AXI_AR_PROG_EMPTY_THRESH(),
|
| 452 |
|
|
.AXI_AR_DATA_COUNT(),
|
| 453 |
|
|
.AXI_AR_WR_DATA_COUNT(),
|
| 454 |
|
|
.AXI_AR_RD_DATA_COUNT(),
|
| 455 |
|
|
.AXI_AR_SBITERR(),
|
| 456 |
|
|
.AXI_AR_DBITERR(),
|
| 457 |
|
|
.AXI_AR_OVERFLOW(),
|
| 458 |
|
|
.AXI_AR_UNDERFLOW(),
|
| 459 |
|
|
.AXI_AR_PROG_FULL(),
|
| 460 |
|
|
.AXI_AR_PROG_EMPTY(),
|
| 461 |
|
|
.AXI_R_INJECTSBITERR(),
|
| 462 |
|
|
.AXI_R_INJECTDBITERR(),
|
| 463 |
|
|
.AXI_R_PROG_FULL_THRESH(),
|
| 464 |
|
|
.AXI_R_PROG_EMPTY_THRESH(),
|
| 465 |
|
|
.AXI_R_DATA_COUNT(),
|
| 466 |
|
|
.AXI_R_WR_DATA_COUNT(),
|
| 467 |
|
|
.AXI_R_RD_DATA_COUNT(),
|
| 468 |
|
|
.AXI_R_SBITERR(),
|
| 469 |
|
|
.AXI_R_DBITERR(),
|
| 470 |
|
|
.AXI_R_OVERFLOW(),
|
| 471 |
|
|
.AXI_R_UNDERFLOW(),
|
| 472 |
|
|
.AXIS_INJECTSBITERR(),
|
| 473 |
|
|
.AXI_R_PROG_FULL(),
|
| 474 |
|
|
.AXI_R_PROG_EMPTY(),
|
| 475 |
|
|
.AXIS_INJECTDBITERR(),
|
| 476 |
|
|
.AXIS_PROG_FULL_THRESH(),
|
| 477 |
|
|
.AXIS_PROG_EMPTY_THRESH(),
|
| 478 |
|
|
.AXIS_DATA_COUNT(),
|
| 479 |
|
|
.AXIS_WR_DATA_COUNT(),
|
| 480 |
|
|
.AXIS_RD_DATA_COUNT(),
|
| 481 |
|
|
.AXIS_SBITERR(),
|
| 482 |
|
|
.AXIS_DBITERR(),
|
| 483 |
|
|
.AXIS_OVERFLOW(),
|
| 484 |
|
|
.AXIS_UNDERFLOW(),
|
| 485 |
|
|
.AXIS_PROG_FULL(),
|
| 486 |
|
|
.AXIS_PROG_EMPTY()
|
| 487 |
|
|
);
|
| 488 |
|
|
|
| 489 |
|
|
// synthesis translate_on
|
| 490 |
|
|
|
| 491 |
|
|
endmodule
|
