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[/] [hdl-deflate/] [trunk/] [deflate.v] - Blame information for rev 2

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// File: deflate.v
2
// Generated by MyHDL 0.10
3
// Date: Thu Dec 20 18:23:02 2018
4
 
5
 
6
`timescale 1ns/10ps
7
 
8
module deflate (
9
    i_mode,
10
    o_done,
11
    i_data,
12
    o_iprogress,
13
    o_oprogress,
14
    o_byte,
15
    i_addr,
16
    clk,
17
    reset
18
);
19
// Deflate (de)compress
20
// 
21
// Ports:
22
 
23
input [2:0] i_mode;
24
output o_done;
25
reg o_done;
26
input [7:0] i_data;
27
output [12:0] o_iprogress;
28
reg [12:0] o_iprogress;
29
output [12:0] o_oprogress;
30
reg [12:0] o_oprogress;
31
output [7:0] o_byte;
32
reg [7:0] o_byte;
33
input [12:0] i_addr;
34
input clk;
35
input reset;
36
 
37
reg [18:0] wleaf;
38
reg [9:0] step;
39
reg static;
40
reg [4:0] state;
41
reg [8:0] spread_i;
42
reg [9:0] spread;
43
reg [9:0] reverse;
44
reg [7:0] orbyte;
45
reg [12:0] oraddr;
46
reg [12:0] offset;
47
reg [7:0] obyte;
48
reg [7:0] ob1;
49
reg [12:0] oaddr;
50
reg [8:0] numLiterals;
51
reg [5:0] numDistance;
52
reg [8:0] numCodeLength;
53
reg [2:0] nb;
54
reg [4:0] minBits;
55
reg [2:0] method;
56
reg [4:0] maxBits;
57
reg [8:0] lwaddr;
58
reg [12:0] length;
59
reg [18:0] leaf;
60
reg [14:0] lastToken;
61
reg [15:0] ladler1;
62
reg [12:0] isize;
63
reg [9:0] instantMaxBit;
64
reg [14:0] instantMask;
65
reg [8:0] howOften;
66
reg flush;
67
reg final;
68
reg filled;
69
reg [2:0] doo;
70
reg do_compress;
71
reg [12:0] do;
72
reg [2:0] dio;
73
reg [12:0] di;
74
reg [4:0] d_maxBits;
75
reg [9:0] d_instantMaxBit;
76
reg [14:0] d_instantMask;
77
reg [8:0] cur_static;
78
reg signed [7:0] cur_search;
79
reg cur_next;
80
reg [12:0] cur_i;
81
reg signed [7:0] cur_dist;
82
reg [12:0] cur_cstatic;
83
reg [9:0] cur_HF1;
84
reg [7:0] copy1;
85
reg [14:0] code;
86
reg [3:0] bits;
87
reg [8:0] b_numCodeLength;
88
wire [31:0] b41;
89
reg [7:0] b4;
90
reg [7:0] b3;
91
reg [7:0] b2;
92
reg [7:0] b1;
93
reg [15:0] adler2;
94
reg [15:0] adler1;
95
reg [7:0] oram [0:8192-1];
96
reg [9:0] nextCode [0:15-1];
97
reg [18:0] leaves [0:512-1];
98
reg [7:0] iram [0:128-1];
99
reg [3:0] distanceLength [0:32-1];
100
reg [18:0] d_leaves [0:128-1];
101
reg [8:0] code_bits [0:288-1];
102
reg [3:0] codeLength [0:290-1];
103
reg [8:0] bitLengthCount [0:16-1];
104
 
105
assign b41[32-1:24] = b4;
106
assign b41[24-1:16] = b3;
107
assign b41[16-1:8] = b2;
108
assign b41[8-1:0] = b1;
109
 
110
task MYHDL3_adv;
111
    input width;
112
    integer width;
113
    integer nshift;
114
begin: MYHDL77_RETURN
115
    nshift = ((dio + width) >>> 3);
116
    o_iprogress <= di;
117
    dio <= ((dio + width) & 7);
118
    di <= ($signed({1'b0, di}) + nshift);
119
    if ((nshift != 0)) begin
120
        filled <= 1'b0;
121
    end
122
end
123
endtask
124
 
125
function integer MYHDL4_get4;
126
    input boffset;
127
    input width;
128
begin: MYHDL78_RETURN
129
    if ((nb != 4)) begin
130
        $write("----NB----");
131
        $write("\n");
132
        $finish;
133
    end
134
    MYHDL4_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
135
    disable MYHDL78_RETURN;
136
end
137
endfunction
138
 
139
function integer MYHDL5_get4;
140
    input boffset;
141
    input width;
142
    integer width;
143
begin: MYHDL79_RETURN
144
    if ((nb != 4)) begin
145
        $write("----NB----");
146
        $write("\n");
147
        $finish;
148
    end
149
    MYHDL5_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
150
    disable MYHDL79_RETURN;
151
end
152
endfunction
153
 
154
task MYHDL6_adv;
155
    input width;
156
    integer width;
157
    integer nshift;
158
begin: MYHDL80_RETURN
159
    nshift = ((dio + width) >>> 3);
160
    o_iprogress <= di;
161
    dio <= ((dio + width) & 7);
162
    di <= ($signed({1'b0, di}) + nshift);
163
    if ((nshift != 0)) begin
164
        filled <= 1'b0;
165
    end
166
end
167
endtask
168
 
169
task MYHDL7_adv;
170
    input width;
171
    integer width;
172
    integer nshift;
173
begin: MYHDL81_RETURN
174
    nshift = ((dio + width) >>> 3);
175
    o_iprogress <= di;
176
    dio <= ((dio + width) & 7);
177
    di <= ($signed({1'b0, di}) + nshift);
178
    if ((nshift != 0)) begin
179
        filled <= 1'b0;
180
    end
181
end
182
endtask
183
 
184
function integer MYHDL8_get4;
185
    input boffset;
186
    integer boffset;
187
    input width;
188
    integer width;
189
begin: MYHDL82_RETURN
190
    if ((nb != 4)) begin
191
        $write("----NB----");
192
        $write("\n");
193
        $finish;
194
    end
195
    MYHDL8_get4 = ($signed($signed({1'b0, b41}) >>> ($signed({1'b0, dio}) + boffset)) & ((1 << width) - 1));
196
    disable MYHDL82_RETURN;
197
end
198
endfunction
199
 
200
task MYHDL9_adv;
201
    input width;
202
    integer width;
203
    integer nshift;
204
begin: MYHDL83_RETURN
205
    nshift = $signed(($signed({1'b0, dio}) + width) >>> 3);
206
    o_iprogress <= di;
207
    dio <= (($signed({1'b0, dio}) + width) & 7);
208
    di <= ($signed({1'b0, di}) + nshift);
209
    if ((nshift != 0)) begin
210
        filled <= 1'b0;
211
    end
212
end
213
endtask
214
 
215
function integer MYHDL10_put;
216
    input d;
217
    integer d;
218
    input width;
219
    integer width;
220
begin: MYHDL84_RETURN
221
    if ((width > 9)) begin
222
        $finish;
223
    end
224
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
225
        $finish;
226
    end
227
    MYHDL10_put = ((ob1 | (d << doo)) & 255);
228
    disable MYHDL84_RETURN;
229
end
230
endfunction
231
 
232
task MYHDL11_put_adv;
233
    input d;
234
    integer d;
235
    input width;
236
    integer width;
237
    reg pshift;
238
    integer carry;
239
    integer doo_next;
240
begin: MYHDL85_RETURN
241
    if ((width > 9)) begin
242
        $finish;
243
    end
244
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
245
        $finish;
246
    end
247
    pshift = ((doo + width) > 8);
248
    if (pshift) begin
249
        carry = ($signed({1'b0, width}) - (8 - $signed({1'b0, doo})));
250
        ob1 <= $signed($signed({1'b0, d}) >>> ($signed({1'b0, width}) - carry));
251
    end
252
    else begin
253
        ob1 <= (ob1 | (d << doo));
254
    end
255
    do <= (do + pshift);
256
    o_oprogress <= (do + pshift);
257
    doo_next = ((doo + width) & 7);
258
    if ((doo_next == 0)) begin
259
        flush <= 1'b1;
260
    end
261
    doo <= doo_next;
262
end
263
endtask
264
 
265
task MYHDL12_do_flush;
266
begin: MYHDL86_RETURN
267
    flush <= 1'b0;
268
    ob1 <= 0;
269
    o_oprogress <= (do + 1);
270
    do <= (do + 1);
271
end
272
endtask
273
 
274
function integer MYHDL13_put;
275
    input [9-1:0] d;
276
    input [4-1:0] width;
277
begin: MYHDL87_RETURN
278
    if ((width > 9)) begin
279
        $finish;
280
    end
281
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
282
        $finish;
283
    end
284
    MYHDL13_put = ((ob1 | (d << doo)) & 255);
285
    disable MYHDL87_RETURN;
286
end
287
endfunction
288
 
289
task MYHDL14_put_adv;
290
    input [9-1:0] d;
291
    input [4-1:0] width;
292
    reg pshift;
293
    integer carry;
294
    integer doo_next;
295
begin: MYHDL88_RETURN
296
    if ((width > 9)) begin
297
        $finish;
298
    end
299
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
300
        $finish;
301
    end
302
    pshift = ((doo + width) > 8);
303
    if (pshift) begin
304
        carry = ($signed({1'b0, width}) - (8 - $signed({1'b0, doo})));
305
        ob1 <= $signed($signed({1'b0, d}) >>> ($signed({1'b0, width}) - carry));
306
    end
307
    else begin
308
        ob1 <= (ob1 | (d << doo));
309
    end
310
    do <= (do + pshift);
311
    o_oprogress <= (do + pshift);
312
    doo_next = ((doo + width) & 7);
313
    if ((doo_next == 0)) begin
314
        flush <= 1'b1;
315
    end
316
    doo <= doo_next;
317
end
318
endtask
319
 
320
task MYHDL15_do_flush;
321
begin: MYHDL89_RETURN
322
    flush <= 1'b0;
323
    ob1 <= 0;
324
    o_oprogress <= (do + 1);
325
    do <= (do + 1);
326
end
327
endtask
328
 
329
function integer MYHDL16_rev_bits;
330
    input [13-1:0] b;
331
    input nb;
332
    integer nb;
333
    integer r;
334
begin: MYHDL90_RETURN
335
    if ((b >= (1 << nb))) begin
336
        $finish;
337
        $write("too few bits");
338
        $write("\n");
339
    end
340
    r = (((((((((((((((((b >>> 14) & 1) << 0) | (((b >>> 13) & 1) << 1)) | (((b >>> 12) & 1) << 2)) | (((b >>> 11) & 1) << 3)) | (((b >>> 10) & 1) << 4)) | (((b >>> 9) & 1) << 5)) | (((b >>> 8) & 1) << 6)) | (((b >>> 7) & 1) << 7)) | (((b >>> 6) & 1) << 8)) | (((b >>> 5) & 1) << 9)) | (((b >>> 4) & 1) << 10)) | (((b >>> 3) & 1) << 11)) | (((b >>> 2) & 1) << 12)) | (((b >>> 1) & 1) << 13)) | (((b >>> 0) & 1) << 14));
341
    r = r >>> (15 - $signed({1'b0, nb}));
342
    MYHDL16_rev_bits = r;
343
    disable MYHDL90_RETURN;
344
end
345
endfunction
346
 
347
function integer MYHDL17_put;
348
    input d;
349
    integer d;
350
    input width;
351
    integer width;
352
begin: MYHDL91_RETURN
353
    if ((width > 9)) begin
354
        $finish;
355
    end
356
    if ((d > ((1 << width) - 1))) begin
357
        $finish;
358
    end
359
    MYHDL17_put = (($signed({1'b0, ob1}) | (d << $signed({1'b0, doo}))) & 255);
360
    disable MYHDL91_RETURN;
361
end
362
endfunction
363
 
364
task MYHDL18_put_adv;
365
    input d;
366
    integer d;
367
    input width;
368
    integer width;
369
    reg pshift;
370
    integer carry;
371
    integer doo_next;
372
begin: MYHDL92_RETURN
373
    if ((width > 9)) begin
374
        $finish;
375
    end
376
    if ((d > ((1 << width) - 1))) begin
377
        $finish;
378
    end
379
    pshift = (($signed({1'b0, doo}) + width) > 8);
380
    if (pshift) begin
381
        carry = (width - (8 - $signed({1'b0, doo})));
382
        ob1 <= $signed(d >>> (width - carry));
383
    end
384
    else begin
385
        ob1 <= ($signed({1'b0, ob1}) | (d << $signed({1'b0, doo})));
386
    end
387
    do <= (do + pshift);
388
    o_oprogress <= (do + pshift);
389
    doo_next = (($signed({1'b0, doo}) + width) & 7);
390
    if ((doo_next == 0)) begin
391
        flush <= 1'b1;
392
    end
393
    doo <= doo_next;
394
end
395
endtask
396
 
397
function integer MYHDL19_put;
398
    input [9-1:0] d;
399
    input [4-1:0] width;
400
begin: MYHDL93_RETURN
401
    if ((width > 9)) begin
402
        $finish;
403
    end
404
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
405
        $finish;
406
    end
407
    MYHDL19_put = ((ob1 | (d << doo)) & 255);
408
    disable MYHDL93_RETURN;
409
end
410
endfunction
411
 
412
task MYHDL20_put_adv;
413
    input [9-1:0] d;
414
    input [4-1:0] width;
415
    reg pshift;
416
    integer carry;
417
    integer doo_next;
418
begin: MYHDL94_RETURN
419
    if ((width > 9)) begin
420
        $finish;
421
    end
422
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
423
        $finish;
424
    end
425
    pshift = ((doo + width) > 8);
426
    if (pshift) begin
427
        carry = ($signed({1'b0, width}) - (8 - $signed({1'b0, doo})));
428
        ob1 <= $signed($signed({1'b0, d}) >>> ($signed({1'b0, width}) - carry));
429
    end
430
    else begin
431
        ob1 <= (ob1 | (d << doo));
432
    end
433
    do <= (do + pshift);
434
    o_oprogress <= (do + pshift);
435
    doo_next = ((doo + width) & 7);
436
    if ((doo_next == 0)) begin
437
        flush <= 1'b1;
438
    end
439
    doo <= doo_next;
440
end
441
endtask
442
 
443
function integer MYHDL21_put;
444
    input [9-1:0] d;
445
    input [4-1:0] width;
446
begin: MYHDL95_RETURN
447
    if ((width > 9)) begin
448
        $finish;
449
    end
450
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
451
        $finish;
452
    end
453
    MYHDL21_put = ((ob1 | (d << doo)) & 255);
454
    disable MYHDL95_RETURN;
455
end
456
endfunction
457
 
458
task MYHDL22_put_adv;
459
    input [9-1:0] d;
460
    input [4-1:0] width;
461
    reg pshift;
462
    integer carry;
463
    integer doo_next;
464
begin: MYHDL96_RETURN
465
    if ((width > 9)) begin
466
        $finish;
467
    end
468
    if (($signed({1'b0, d}) > ((1 << width) - 1))) begin
469
        $finish;
470
    end
471
    pshift = ((doo + width) > 8);
472
    if (pshift) begin
473
        carry = ($signed({1'b0, width}) - (8 - $signed({1'b0, doo})));
474
        ob1 <= $signed($signed({1'b0, d}) >>> ($signed({1'b0, width}) - carry));
475
    end
476
    else begin
477
        ob1 <= (ob1 | (d << doo));
478
    end
479
    do <= (do + pshift);
480
    o_oprogress <= (do + pshift);
481
    doo_next = ((doo + width) & 7);
482
    if ((doo_next == 0)) begin
483
        flush <= 1'b1;
484
    end
485
    doo <= doo_next;
486
end
487
endtask
488
 
489
function integer MYHDL31_get4;
490
    input boffset;
491
    input width;
492
    integer width;
493
begin: MYHDL97_RETURN
494
    if ((nb != 4)) begin
495
        $write("----NB----");
496
        $write("\n");
497
        $finish;
498
    end
499
    MYHDL31_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
500
    disable MYHDL97_RETURN;
501
end
502
endfunction
503
 
504
function integer MYHDL32_get4;
505
    input boffset;
506
    input width;
507
    integer width;
508
begin: MYHDL98_RETURN
509
    if ((nb != 4)) begin
510
        $write("----NB----");
511
        $write("\n");
512
        $finish;
513
    end
514
    MYHDL32_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
515
    disable MYHDL98_RETURN;
516
end
517
endfunction
518
 
519
function integer MYHDL33_get4;
520
    input boffset;
521
    integer boffset;
522
    input width;
523
    integer width;
524
begin: MYHDL99_RETURN
525
    if ((nb != 4)) begin
526
        $write("----NB----");
527
        $write("\n");
528
        $finish;
529
    end
530
    MYHDL33_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
531
    disable MYHDL99_RETURN;
532
end
533
endfunction
534
 
535
function integer MYHDL34_get4;
536
    input boffset;
537
    integer boffset;
538
    input width;
539
    integer width;
540
begin: MYHDL100_RETURN
541
    if ((nb != 4)) begin
542
        $write("----NB----");
543
        $write("\n");
544
        $finish;
545
    end
546
    MYHDL34_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
547
    disable MYHDL100_RETURN;
548
end
549
endfunction
550
 
551
function integer MYHDL35_get4;
552
    input boffset;
553
    integer boffset;
554
    input width;
555
    integer width;
556
begin: MYHDL101_RETURN
557
    if ((nb != 4)) begin
558
        $write("----NB----");
559
        $write("\n");
560
        $finish;
561
    end
562
    MYHDL35_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
563
    disable MYHDL101_RETURN;
564
end
565
endfunction
566
 
567
function integer MYHDL36_get4;
568
    input boffset;
569
    integer boffset;
570
    input width;
571
    integer width;
572
begin: MYHDL102_RETURN
573
    if ((nb != 4)) begin
574
        $write("----NB----");
575
        $write("\n");
576
        $finish;
577
    end
578
    MYHDL36_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
579
    disable MYHDL102_RETURN;
580
end
581
endfunction
582
 
583
task MYHDL37_adv;
584
    input width;
585
    integer width;
586
    integer nshift;
587
begin: MYHDL103_RETURN
588
    nshift = ((dio + width) >>> 3);
589
    o_iprogress <= di;
590
    dio <= ((dio + width) & 7);
591
    di <= ($signed({1'b0, di}) + nshift);
592
    if ((nshift != 0)) begin
593
        filled <= 1'b0;
594
    end
595
end
596
endtask
597
 
598
function integer MYHDL38_get4;
599
    input boffset;
600
    input width;
601
    integer width;
602
begin: MYHDL104_RETURN
603
    if ((nb != 4)) begin
604
        $write("----NB----");
605
        $write("\n");
606
        $finish;
607
    end
608
    MYHDL38_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
609
    disable MYHDL104_RETURN;
610
end
611
endfunction
612
 
613
task MYHDL39_adv;
614
    input width;
615
    integer width;
616
    integer nshift;
617
begin: MYHDL105_RETURN
618
    nshift = ((dio + width) >>> 3);
619
    o_iprogress <= di;
620
    dio <= ((dio + width) & 7);
621
    di <= ($signed({1'b0, di}) + nshift);
622
    if ((nshift != 0)) begin
623
        filled <= 1'b0;
624
    end
625
end
626
endtask
627
 
628
function integer MYHDL40_get4;
629
    input boffset;
630
    input width;
631
    integer width;
632
begin: MYHDL106_RETURN
633
    if ((nb != 4)) begin
634
        $write("----NB----");
635
        $write("\n");
636
        $finish;
637
    end
638
    MYHDL40_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
639
    disable MYHDL106_RETURN;
640
end
641
endfunction
642
 
643
function integer MYHDL41_get4;
644
    input boffset;
645
    input width;
646
    integer width;
647
begin: MYHDL107_RETURN
648
    if ((nb != 4)) begin
649
        $write("----NB----");
650
        $write("\n");
651
        $finish;
652
    end
653
    MYHDL41_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
654
    disable MYHDL107_RETURN;
655
end
656
endfunction
657
 
658
function integer MYHDL42_get4;
659
    input boffset;
660
    input width;
661
    integer width;
662
begin: MYHDL108_RETURN
663
    if ((nb != 4)) begin
664
        $write("----NB----");
665
        $write("\n");
666
        $finish;
667
    end
668
    MYHDL42_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
669
    disable MYHDL108_RETURN;
670
end
671
endfunction
672
 
673
task MYHDL43_adv;
674
    input width;
675
    integer width;
676
    integer nshift;
677
begin: MYHDL109_RETURN
678
    nshift = ((dio + width) >>> 3);
679
    o_iprogress <= di;
680
    dio <= ((dio + width) & 7);
681
    di <= ($signed({1'b0, di}) + nshift);
682
    if ((nshift != 0)) begin
683
        filled <= 1'b0;
684
    end
685
end
686
endtask
687
 
688
function integer MYHDL50_rev_bits;
689
    input [10-1:0] b;
690
    input [4-1:0] nb;
691
    integer r;
692
begin: MYHDL110_RETURN
693
    if ((b >= (1 << nb))) begin
694
        $finish;
695
        $write("too few bits");
696
        $write("\n");
697
    end
698
    r = (((((((((((((((((b >>> 14) & 1) << 0) | (((b >>> 13) & 1) << 1)) | (((b >>> 12) & 1) << 2)) | (((b >>> 11) & 1) << 3)) | (((b >>> 10) & 1) << 4)) | (((b >>> 9) & 1) << 5)) | (((b >>> 8) & 1) << 6)) | (((b >>> 7) & 1) << 7)) | (((b >>> 6) & 1) << 8)) | (((b >>> 5) & 1) << 9)) | (((b >>> 4) & 1) << 10)) | (((b >>> 3) & 1) << 11)) | (((b >>> 2) & 1) << 12)) | (((b >>> 1) & 1) << 13)) | (((b >>> 0) & 1) << 14));
699
    r = r >>> (15 - $signed({1'b0, nb}));
700
    MYHDL50_rev_bits = r;
701
    disable MYHDL110_RETURN;
702
end
703
endfunction
704
 
705
function integer MYHDL51_makeLeaf;
706
    input [9-1:0] lcode;
707
    input [4-1:0] lbits;
708
begin: MYHDL111_RETURN
709
    if ((lcode >= (1 << 10))) begin
710
        $finish;
711
    end
712
    if ((lbits >= (1 << 9))) begin
713
        $finish;
714
    end
715
    MYHDL51_makeLeaf = ((lcode << 9) | lbits);
716
    disable MYHDL111_RETURN;
717
end
718
endfunction
719
 
720
function integer MYHDL52_makeLeaf;
721
    input [9-1:0] lcode;
722
    input [4-1:0] lbits;
723
begin: MYHDL112_RETURN
724
    if ((lcode >= (1 << 10))) begin
725
        $finish;
726
    end
727
    if ((lbits >= (1 << 9))) begin
728
        $finish;
729
    end
730
    MYHDL52_makeLeaf = ((lcode << 9) | lbits);
731
    disable MYHDL112_RETURN;
732
end
733
endfunction
734
 
735
function integer MYHDL53_makeLeaf;
736
    input [9-1:0] lcode;
737
    input [4-1:0] lbits;
738
begin: MYHDL113_RETURN
739
    if ((lcode >= (1 << 10))) begin
740
        $finish;
741
    end
742
    if ((lbits >= (1 << 9))) begin
743
        $finish;
744
    end
745
    MYHDL53_makeLeaf = ((lcode << 9) | lbits);
746
    disable MYHDL113_RETURN;
747
end
748
endfunction
749
 
750
function integer MYHDL54_get4;
751
    input boffset;
752
    input [5-1:0] width;
753
begin: MYHDL114_RETURN
754
    if ((nb != 4)) begin
755
        $write("----NB----");
756
        $write("\n");
757
        $finish;
758
    end
759
    MYHDL54_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
760
    disable MYHDL114_RETURN;
761
end
762
endfunction
763
 
764
function integer MYHDL55_get_bits;
765
    input [19-1:0] aleaf;
766
begin: MYHDL115_RETURN
767
    MYHDL55_get_bits = ($signed({1'b0, aleaf}) & ((1 << 9) - 1));
768
    disable MYHDL115_RETURN;
769
end
770
endfunction
771
 
772
function integer MYHDL56_get_bits;
773
    input [19-1:0] aleaf;
774
begin: MYHDL116_RETURN
775
    MYHDL56_get_bits = ($signed({1'b0, aleaf}) & ((1 << 9) - 1));
776
    disable MYHDL116_RETURN;
777
end
778
endfunction
779
 
780
task MYHDL57_adv;
781
    input width;
782
    integer width;
783
    integer nshift;
784
begin: MYHDL117_RETURN
785
    nshift = $signed(($signed({1'b0, dio}) + width) >>> 3);
786
    o_iprogress <= di;
787
    dio <= (($signed({1'b0, dio}) + width) & 7);
788
    di <= ($signed({1'b0, di}) + nshift);
789
    if ((nshift != 0)) begin
790
        filled <= 1'b0;
791
    end
792
end
793
endtask
794
 
795
function integer MYHDL58_get_code;
796
    input [19-1:0] aleaf;
797
begin: MYHDL118_RETURN
798
    MYHDL58_get_code = (aleaf >>> 9);
799
    disable MYHDL118_RETURN;
800
end
801
endfunction
802
 
803
function integer MYHDL59_get_code;
804
    input [19-1:0] aleaf;
805
begin: MYHDL119_RETURN
806
    MYHDL59_get_code = (aleaf >>> 9);
807
    disable MYHDL119_RETURN;
808
end
809
endfunction
810
 
811
function integer MYHDL60_get4;
812
    input boffset;
813
    integer boffset;
814
    input [5-1:0] width;
815
begin: MYHDL120_RETURN
816
    if ((nb != 4)) begin
817
        $write("----NB----");
818
        $write("\n");
819
        $finish;
820
    end
821
    MYHDL60_get4 = ($signed($signed({1'b0, b41}) >>> ($signed({1'b0, dio}) + boffset)) & ((1 << width) - 1));
822
    disable MYHDL120_RETURN;
823
end
824
endfunction
825
 
826
function integer MYHDL61_get_bits;
827
    input [19-1:0] aleaf;
828
begin: MYHDL121_RETURN
829
    MYHDL61_get_bits = ($signed({1'b0, aleaf}) & ((1 << 9) - 1));
830
    disable MYHDL121_RETURN;
831
end
832
endfunction
833
 
834
function integer MYHDL62_get4;
835
    input boffset;
836
    input width;
837
    integer width;
838
begin: MYHDL122_RETURN
839
    if ((nb != 4)) begin
840
        $write("----NB----");
841
        $write("\n");
842
        $finish;
843
    end
844
    MYHDL62_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
845
    disable MYHDL122_RETURN;
846
end
847
endfunction
848
 
849
function integer MYHDL63_get_code;
850
    input [19-1:0] aleaf;
851
begin: MYHDL123_RETURN
852
    MYHDL63_get_code = (aleaf >>> 9);
853
    disable MYHDL123_RETURN;
854
end
855
endfunction
856
 
857
function integer MYHDL64_get_bits;
858
    input [19-1:0] aleaf;
859
begin: MYHDL124_RETURN
860
    MYHDL64_get_bits = ($signed({1'b0, aleaf}) & ((1 << 9) - 1));
861
    disable MYHDL124_RETURN;
862
end
863
endfunction
864
 
865
function integer MYHDL65_get4;
866
    input boffset;
867
    integer boffset;
868
    input width;
869
    integer width;
870
begin: MYHDL125_RETURN
871
    if ((nb != 4)) begin
872
        $write("----NB----");
873
        $write("\n");
874
        $finish;
875
    end
876
    MYHDL65_get4 = ($signed($signed({1'b0, b41}) >>> ($signed({1'b0, dio}) + boffset)) & ((1 << width) - 1));
877
    disable MYHDL125_RETURN;
878
end
879
endfunction
880
 
881
function integer MYHDL66_get_bits;
882
    input [19-1:0] aleaf;
883
begin: MYHDL126_RETURN
884
    MYHDL66_get_bits = ($signed({1'b0, aleaf}) & ((1 << 9) - 1));
885
    disable MYHDL126_RETURN;
886
end
887
endfunction
888
 
889
task MYHDL67_adv;
890
    input width;
891
    integer width;
892
    integer nshift;
893
begin: MYHDL127_RETURN
894
    nshift = $signed(($signed({1'b0, dio}) + width) >>> 3);
895
    o_iprogress <= di;
896
    dio <= (($signed({1'b0, dio}) + width) & 7);
897
    di <= ($signed({1'b0, di}) + nshift);
898
    if ((nshift != 0)) begin
899
        filled <= 1'b0;
900
    end
901
end
902
endtask
903
 
904
function integer MYHDL68_get4;
905
    input boffset;
906
    input width;
907
    integer width;
908
begin: MYHDL128_RETURN
909
    if ((nb != 4)) begin
910
        $write("----NB----");
911
        $write("\n");
912
        $finish;
913
    end
914
    MYHDL68_get4 = ((b41 >>> (dio + boffset)) & ((1 << width) - 1));
915
    disable MYHDL128_RETURN;
916
end
917
endfunction
918
 
919
function integer MYHDL69_get4;
920
    input boffset;
921
    integer boffset;
922
    input width;
923
    integer width;
924
begin: MYHDL129_RETURN
925
    if ((nb != 4)) begin
926
        $write("----NB----");
927
        $write("\n");
928
        $finish;
929
    end
930
    MYHDL69_get4 = ($signed($signed({1'b0, b41}) >>> ($signed({1'b0, dio}) + boffset)) & ((1 << width) - 1));
931
    disable MYHDL129_RETURN;
932
end
933
endfunction
934
 
935
function integer MYHDL70_rev_bits;
936
    input b;
937
    integer b;
938
    input nb;
939
    integer nb;
940
    integer r;
941
begin: MYHDL130_RETURN
942
    if ((b >= (1 << nb))) begin
943
        $finish;
944
        $write("too few bits");
945
        $write("\n");
946
    end
947
    r = (((((((((((((((((b >>> 14) & 1) << 0) | (((b >>> 13) & 1) << 1)) | (((b >>> 12) & 1) << 2)) | (((b >>> 11) & 1) << 3)) | (((b >>> 10) & 1) << 4)) | (((b >>> 9) & 1) << 5)) | (((b >>> 8) & 1) << 6)) | (((b >>> 7) & 1) << 7)) | (((b >>> 6) & 1) << 8)) | (((b >>> 5) & 1) << 9)) | (((b >>> 4) & 1) << 10)) | (((b >>> 3) & 1) << 11)) | (((b >>> 2) & 1) << 12)) | (((b >>> 1) & 1) << 13)) | (((b >>> 0) & 1) << 14));
948
    r = r >>> (15 - $signed({1'b0, nb}));
949
    MYHDL70_rev_bits = r;
950
    disable MYHDL130_RETURN;
951
end
952
endfunction
953
 
954
function integer MYHDL71_get4;
955
    input boffset;
956
    integer boffset;
957
    input width;
958
    integer width;
959
begin: MYHDL131_RETURN
960
    if ((nb != 4)) begin
961
        $write("----NB----");
962
        $write("\n");
963
        $finish;
964
    end
965
    MYHDL71_get4 = ($signed($signed({1'b0, b41}) >>> ($signed({1'b0, dio}) + boffset)) & ((1 << width) - 1));
966
    disable MYHDL131_RETURN;
967
end
968
endfunction
969
 
970
task MYHDL72_adv;
971
    input width;
972
    integer width;
973
    integer nshift;
974
begin: MYHDL132_RETURN
975
    nshift = $signed(($signed({1'b0, dio}) + width) >>> 3);
976
    o_iprogress <= di;
977
    dio <= (($signed({1'b0, dio}) + width) & 7);
978
    di <= ($signed({1'b0, di}) + nshift);
979
    if ((nshift != 0)) begin
980
        filled <= 1'b0;
981
    end
982
end
983
endtask
984
 
985
task MYHDL73_adv;
986
    input width;
987
    integer width;
988
    integer nshift;
989
begin: MYHDL133_RETURN
990
    nshift = ((dio + width) >>> 3);
991
    o_iprogress <= di;
992
    dio <= ((dio + width) & 7);
993
    di <= ($signed({1'b0, di}) + nshift);
994
    if ((nshift != 0)) begin
995
        filled <= 1'b0;
996
    end
997
end
998
endtask
999
 
1000
 
1001
always @(posedge clk) begin: DEFLATE_IO_LOGIC
1002
    case (i_mode)
1003
        'h2: begin
1004
            iram[(i_addr & 127)] <= i_data;
1005
            isize <= i_addr;
1006
        end
1007
        'h3: begin
1008
            o_byte <= oram[i_addr];
1009
        end
1010
        default: begin
1011
            // pass
1012
        end
1013
    endcase
1014
end
1015
 
1016
 
1017
always @(posedge clk) begin: DEFLATE_LOGIC
1018
    integer hm;
1019
    integer skip;
1020
    reg no_adv;
1021
    integer cs_i;
1022
    reg [4-1:0] outlen;
1023
    reg [9-1:0] outbits;
1024
    reg [8-1:0] bdata;
1025
    integer adler1_next;
1026
    integer nextdist;
1027
    integer copydist;
1028
    integer extra_dist;
1029
    integer extra_bits;
1030
    integer outcode;
1031
    integer lencode;
1032
    integer match;
1033
    integer distance;
1034
    integer stat_i;
1035
    integer clo_i;
1036
    integer n_adv;
1037
    integer dbl_i;
1038
    integer dbl;
1039
    integer dist_i;
1040
    integer limit;
1041
    reg [4-1:0] j;
1042
    integer t;
1043
    integer hf2_i;
1044
    reg [5-1:0] amb;
1045
    integer ncode;
1046
    reg [10-1:0] canonical;
1047
    reg [4-1:0] bits_next;
1048
    reg [15-1:0] aim;
1049
    integer cto;
1050
    integer mask;
1051
    integer token;
1052
    integer extraLength;
1053
    integer tlength;
1054
    integer distanceCode;
1055
    integer moreBits;
1056
    integer mored;
1057
    if ((!reset)) begin
1058
        $write("DEFLATE RESET");
1059
        $write("\n");
1060
        state <= 5'b00000;
1061
        o_done <= 1'b0;
1062
    end
1063
    else begin
1064
        case (state)
1065
            5'b00000: begin
1066
                case (i_mode)
1067
                    'h4: begin
1068
                        $write("STARTC");
1069
                        $write("\n");
1070
                        do_compress <= 1'b1;
1071
                        method <= 1;
1072
                        o_done <= 1'b0;
1073
                        o_iprogress <= 0;
1074
                        o_oprogress <= 0;
1075
                        di <= 0;
1076
                        dio <= 0;
1077
                        do <= 0;
1078
                        doo <= 0;
1079
                        filled <= 1'b1;
1080
                        cur_static <= 0;
1081
                        state <= 5'b01110;
1082
                    end
1083
                    'h5: begin
1084
                        do_compress <= 1'b0;
1085
                        o_done <= 1'b0;
1086
                        o_iprogress <= 0;
1087
                        o_oprogress <= 0;
1088
                        di <= 0;
1089
                        dio <= 0;
1090
                        do <= 0;
1091
                        doo <= 0;
1092
                        filled <= 1'b1;
1093
                        state <= 5'b00001;
1094
                    end
1095
                    default: begin
1096
                        // pass
1097
                    end
1098
                endcase
1099
            end
1100
            5'b00001: begin
1101
                if ((!filled)) begin
1102
                    filled <= 1'b1;
1103
                end
1104
                else if ((nb < 4)) begin
1105
                    // pass
1106
                end
1107
                else if ((di == 0)) begin
1108
                    if ((b1 == 120)) begin
1109
                        $write("deflate mode");
1110
                        $write("\n");
1111
                    end
1112
                    else begin
1113
                        $write("%h", di);
1114
                        $write(" ");
1115
                        $write("%h", dio);
1116
                        $write(" ");
1117
                        $write("%h", nb);
1118
                        $write(" ");
1119
                        $write("%h", b1);
1120
                        $write(" ");
1121
                        $write("%h", b2);
1122
                        $write(" ");
1123
                        $write("%h", b3);
1124
                        $write(" ");
1125
                        $write("%h", b4);
1126
                        $write(" ");
1127
                        $write("%h", isize);
1128
                        $write("\n");
1129
                        $finish;
1130
                        o_done <= 1'b1;
1131
                        state <= 5'b00000;
1132
                    end
1133
                    MYHDL3_adv(16);
1134
                end
1135
                else begin
1136
                    if (MYHDL4_get4(0, 1)) begin
1137
                        $write("final");
1138
                        $write("\n");
1139
                        final <= 1'b1;
1140
                    end
1141
                    hm = MYHDL5_get4(1, 2);
1142
                    method <= hm;
1143
                    $write("method");
1144
                    $write(" ");
1145
                    $write("%0d", hm);
1146
                    $write("\n");
1147
                    case (hm)
1148
                        'h2: begin
1149
                            state <= 5'b00010;
1150
                            numCodeLength <= 0;
1151
                            numLiterals <= 0;
1152
                            static <= 1'b0;
1153
                            MYHDL6_adv(3);
1154
                        end
1155
                        'h1: begin
1156
                            static <= 1'b1;
1157
                            cur_static <= 0;
1158
                            state <= 5'b01110;
1159
                            MYHDL7_adv(3);
1160
                        end
1161
                        'h0: begin
1162
                            state <= 5'b10101;
1163
                            skip = (8 - dio);
1164
                            if ((skip <= 2)) begin
1165
                                skip = (16 - dio);
1166
                            end
1167
                            length <= MYHDL8_get4(skip, 16);
1168
                            MYHDL9_adv((skip + 16));
1169
                            cur_i <= 0;
1170
                            offset <= 7;
1171
                        end
1172
                        default: begin
1173
                            state <= 5'b00000;
1174
                            $write("Bad method");
1175
                            $write("\n");
1176
                            $finish;
1177
                        end
1178
                    endcase
1179
                end
1180
            end
1181
            5'b10110: begin
1182
                no_adv = 0;
1183
                if ((!filled)) begin
1184
                    no_adv = 1;
1185
                    filled <= 1'b1;
1186
                end
1187
                else if ((nb < 4)) begin
1188
                    no_adv = 1;
1189
                    // pass
1190
                end
1191
                else if ((cur_cstatic == 0)) begin
1192
                    flush <= 1'b0;
1193
                    ob1 <= 0;
1194
                    adler1 <= 1;
1195
                    adler2 <= 0;
1196
                    ladler1 <= 0;
1197
                    oaddr <= 0;
1198
                    obyte <= 120;
1199
                end
1200
                else if ((cur_cstatic == 1)) begin
1201
                    oaddr <= 1;
1202
                    obyte <= 156;
1203
                    do <= 2;
1204
                end
1205
                else if ((cur_cstatic == 2)) begin
1206
                    oaddr <= do;
1207
                    obyte <= MYHDL10_put(3, 3);
1208
                    MYHDL11_put_adv(3, 3);
1209
                end
1210
                else if (flush) begin
1211
                    $write("flush");
1212
                    $write(" ");
1213
                    $write("%h", do);
1214
                    $write(" ");
1215
                    $write("%h", ob1);
1216
                    $write("\n");
1217
                    no_adv = 1;
1218
                    oaddr <= do;
1219
                    obyte <= ob1;
1220
                    MYHDL12_do_flush;
1221
                end
1222
                else if ((($signed({1'b0, cur_cstatic}) - 3) > isize)) begin
1223
                    if ((($signed({1'b0, cur_cstatic}) - 3) == (isize + 1))) begin
1224
                        $write("Put EOF");
1225
                        $write(" ");
1226
                        $write("%h", do);
1227
                        $write("\n");
1228
                        cs_i = 256;
1229
                        outlen = codeLength[cs_i];
1230
                        outbits = code_bits[cs_i];
1231
                        $write("EOF BITS:");
1232
                        $write(" ");
1233
                        $write("%0d", cs_i);
1234
                        $write(" ");
1235
                        $write("%h", outlen);
1236
                        $write(" ");
1237
                        $write("%h", outbits);
1238
                        $write("\n");
1239
                        oaddr <= do;
1240
                        obyte <= MYHDL13_put(outbits, outlen);
1241
                        MYHDL14_put_adv(outbits, outlen);
1242
                    end
1243
                    else if ((($signed({1'b0, cur_cstatic}) - 3) == (isize + 2))) begin
1244
                        $write("calc end adler");
1245
                        $write("\n");
1246
                        adler2 <= ((adler2 + ladler1) % 65521);
1247
                        if ((doo != 0)) begin
1248
                            oaddr <= do;
1249
                            obyte <= ob1;
1250
                            do <= (do + 1);
1251
                        end
1252
                    end
1253
                    else if ((($signed({1'b0, cur_cstatic}) - 3) == (isize + 3))) begin
1254
                        $write("c1");
1255
                        $write("\n");
1256
                        oaddr <= do;
1257
                        obyte <= (adler2 >>> 8);
1258
                        do <= (do + 1);
1259
                    end
1260
                    else if ((($signed({1'b0, cur_cstatic}) - 3) == (isize + 4))) begin
1261
                        $write("c2");
1262
                        $write("\n");
1263
                        oaddr <= do;
1264
                        obyte <= (adler2 & 255);
1265
                        do <= (do + 1);
1266
                    end
1267
                    else if ((($signed({1'b0, cur_cstatic}) - 3) == (isize + 5))) begin
1268
                        $write("c3");
1269
                        $write("\n");
1270
                        oaddr <= do;
1271
                        obyte <= (adler1 >>> 8);
1272
                        do <= (do + 1);
1273
                    end
1274
                    else if ((($signed({1'b0, cur_cstatic}) - 3) == (isize + 6))) begin
1275
                        $write("c4");
1276
                        $write("\n");
1277
                        oaddr <= do;
1278
                        obyte <= (adler1 & 255);
1279
                    end
1280
                    else if ((($signed({1'b0, cur_cstatic}) - 3) == (isize + 7))) begin
1281
                        $write("EOF finish");
1282
                        $write(" ");
1283
                        $write("%h", do);
1284
                        $write("\n");
1285
                        o_done <= 1'b1;
1286
                        o_oprogress <= (do + 1);
1287
                        state <= 5'b00000;
1288
                    end
1289
                    else begin
1290
                        $write("%h", cur_cstatic);
1291
                        $write(" ");
1292
                        $write("%h", isize);
1293
                        $write("\n");
1294
                        $finish;
1295
                    end
1296
                end
1297
                else begin
1298
                    bdata = iram[di];
1299
                    adler1_next = ((adler1 + bdata) % 65521);
1300
                    adler1 <= adler1_next;
1301
                    adler2 <= ((adler2 + ladler1) % 65521);
1302
                    ladler1 <= adler1_next;
1303
                    state <= 5'b10111;
1304
                    cur_search <= (di - 1);
1305
                end
1306
                if ((!no_adv)) begin
1307
                    cur_cstatic <= (cur_cstatic + 1);
1308
                end
1309
            end
1310
            5'b11000: begin
1311
                if (flush) begin
1312
                    MYHDL15_do_flush;
1313
                end
1314
                else begin
1315
                    case ((cur_i + 1))
1316
                        0: nextdist = 1;
1317
                        1: nextdist = 2;
1318
                        2: nextdist = 3;
1319
                        3: nextdist = 4;
1320
                        4: nextdist = 5;
1321
                        5: nextdist = 7;
1322
                        6: nextdist = 9;
1323
                        7: nextdist = 13;
1324
                        8: nextdist = 17;
1325
                        9: nextdist = 25;
1326
                        10: nextdist = 33;
1327
                        11: nextdist = 49;
1328
                        12: nextdist = 65;
1329
                        13: nextdist = 97;
1330
                        14: nextdist = 129;
1331
                        15: nextdist = 193;
1332
                        16: nextdist = 257;
1333
                        17: nextdist = 385;
1334
                        18: nextdist = 513;
1335
                        19: nextdist = 769;
1336
                        20: nextdist = 1025;
1337
                        21: nextdist = 1537;
1338
                        22: nextdist = 2049;
1339
                        23: nextdist = 3073;
1340
                        24: nextdist = 4097;
1341
                        25: nextdist = 6145;
1342
                        26: nextdist = 8193;
1343
                        27: nextdist = 12289;
1344
                        28: nextdist = 16385;
1345
                        default: nextdist = 24577;
1346
                    endcase
1347
                    if ((nextdist > cur_dist)) begin
1348
                        case (cur_i)
1349
                            0: copydist = 1;
1350
                            1: copydist = 2;
1351
                            2: copydist = 3;
1352
                            3: copydist = 4;
1353
                            4: copydist = 5;
1354
                            5: copydist = 7;
1355
                            6: copydist = 9;
1356
                            7: copydist = 13;
1357
                            8: copydist = 17;
1358
                            9: copydist = 25;
1359
                            10: copydist = 33;
1360
                            11: copydist = 49;
1361
                            12: copydist = 65;
1362
                            13: copydist = 97;
1363
                            14: copydist = 129;
1364
                            15: copydist = 193;
1365
                            16: copydist = 257;
1366
                            17: copydist = 385;
1367
                            18: copydist = 513;
1368
                            19: copydist = 769;
1369
                            20: copydist = 1025;
1370
                            21: copydist = 1537;
1371
                            22: copydist = 2049;
1372
                            23: copydist = 3073;
1373
                            24: copydist = 4097;
1374
                            25: copydist = 6145;
1375
                            26: copydist = 8193;
1376
                            27: copydist = 12289;
1377
                            28: copydist = 16385;
1378
                            default: copydist = 24577;
1379
                        endcase
1380
                        extra_dist = (cur_dist - copydist);
1381
                        case ((cur_i / 2))
1382
                            0: extra_bits = 0;
1383
                            1: extra_bits = 0;
1384
                            2: extra_bits = 1;
1385
                            3: extra_bits = 2;
1386
                            4: extra_bits = 3;
1387
                            5: extra_bits = 4;
1388
                            6: extra_bits = 5;
1389
                            7: extra_bits = 6;
1390
                            8: extra_bits = 7;
1391
                            9: extra_bits = 8;
1392
                            10: extra_bits = 9;
1393
                            11: extra_bits = 10;
1394
                            12: extra_bits = 11;
1395
                            13: extra_bits = 12;
1396
                            default: extra_bits = 13;
1397
                        endcase
1398
                        if ((extra_dist > ((1 << extra_bits) - 1))) begin
1399
                            $finish;
1400
                        end
1401
                        outcode = (MYHDL16_rev_bits(cur_i, 5) | (extra_dist << 5));
1402
                        oaddr <= do;
1403
                        obyte <= MYHDL17_put(outcode, (5 + extra_bits));
1404
                        MYHDL18_put_adv(outcode, (5 + extra_bits));
1405
                        cur_i <= (($signed({1'b0, di}) - $signed({1'b0, length})) + 1);
1406
                        state <= 5'b11001;
1407
                    end
1408
                    else begin
1409
                        cur_i <= (cur_i + 1);
1410
                    end
1411
                end
1412
            end
1413
            5'b11001: begin
1414
                if ((cur_i < di)) begin
1415
                    bdata = iram[(cur_i & 127)];
1416
                    adler1_next = ((adler1 + bdata) % 65521);
1417
                    adler1 <= adler1_next;
1418
                    adler2 <= ((adler2 + ladler1) % 65521);
1419
                    ladler1 <= adler1_next;
1420
                    cur_i <= (cur_i + 1);
1421
                end
1422
                else begin
1423
                    state <= 5'b10110;
1424
                end
1425
            end
1426
            5'b10111: begin
1427
                if ((!filled)) begin
1428
                    filled <= 1'b1;
1429
                end
1430
                else if ((nb < 4)) begin
1431
                    // pass
1432
                end
1433
                else begin
1434
                    if (((cur_search >= 0) && (cur_search >= ($signed({1'b0, di}) - 32)) && ($signed({1'b0, di}) < ($signed({1'b0, isize}) - 3)))) begin
1435
                        if (((iram[(cur_search & 127)] == b1) && (iram[((cur_search + 1) & 127)] == b2) && (iram[((cur_search + 2) & 127)] == b3))) begin
1436
                            lencode = 257;
1437
                            match = 3;
1438
                            if ((($signed({1'b0, di}) < ($signed({1'b0, isize}) - 4)) && (iram[((cur_search + 3) & 127)] == b4))) begin
1439
                                lencode = 258;
1440
                                match = 4;
1441
                                if ((($signed({1'b0, di}) < ($signed({1'b0, isize}) - 5)) && (iram[((cur_search + 4) & 127)] == iram[((di + 4) & 127)]))) begin
1442
                                    lencode = 259;
1443
                                    match = 5;
1444
                                end
1445
                            end
1446
                            // if di < isize - 6 and                                             iram[cur_search+5 & IBS] == iram[di + 5 & IBS]:
1447
                            //     lencode = 260
1448
                            //     match = 6
1449
                            //     if di < isize - 7 and                                                 iram[cur_search+6 & IBS] == iram[di + 6 & IBS]:
1450
                            //         lencode = 261
1451
                            //         match = 7
1452
                            //         if di < isize - 8 and                                                     iram[cur_search+7 & IBS] == iram[di + 7 & IBS]:
1453
                            //             lencode = 262
1454
                            //             match = 8
1455
                            //             if di < isize - 9 and                                                         iram[cur_search+8 & IBS] == iram[di + 8 & IBS]:
1456
                            //                 lencode = 263
1457
                            //                 match = 9
1458
                            //                 if di < isize - 10 and                                                             iram[cur_search+9 & IBS] == iram[di + 9 & IBS]:
1459
                            //                     lencode = 264
1460
                            //                     match = 10
1461
                            $write("found:");
1462
                            $write(" ");
1463
                            $write("%h", cur_search);
1464
                            $write(" ");
1465
                            $write("%h", di);
1466
                            $write(" ");
1467
                            $write("%h", isize);
1468
                            $write(" ");
1469
                            $write("%0d", match);
1470
                            $write("\n");
1471
                            outlen = codeLength[lencode];
1472
                            outbits = code_bits[lencode];
1473
                            oaddr <= do;
1474
                            obyte <= MYHDL19_put(outbits, outlen);
1475
                            MYHDL20_put_adv(outbits, outlen);
1476
                            distance = ($signed({1'b0, di}) - cur_search);
1477
                            cur_dist <= distance;
1478
                            cur_i <= 0;
1479
                            di <= (di + match);
1480
                            cur_cstatic <= ((cur_cstatic + match) - 1);
1481
                            length <= match;
1482
                            state <= 5'b11000;
1483
                        end
1484
                        else begin
1485
                            cur_search <= (cur_search - 1);
1486
                        end
1487
                    end
1488
                    else begin
1489
                        bdata = iram[di];
1490
                        di <= (di + 1);
1491
                        outlen = codeLength[bdata];
1492
                        outbits = code_bits[bdata];
1493
                        oaddr <= do;
1494
                        obyte <= MYHDL21_put(outbits, outlen);
1495
                        MYHDL22_put_adv(outbits, outlen);
1496
                        state <= 5'b10110;
1497
                    end
1498
                end
1499
            end
1500
            5'b01110: begin
1501
                for (stat_i=0; stat_i<144; stat_i=stat_i+1) begin
1502
                    codeLength[stat_i] <= 8;
1503
                end
1504
                for (stat_i=144; stat_i<256; stat_i=stat_i+1) begin
1505
                    codeLength[stat_i] <= 9;
1506
                end
1507
                for (stat_i=256; stat_i<280; stat_i=stat_i+1) begin
1508
                    codeLength[stat_i] <= 7;
1509
                end
1510
                for (stat_i=280; stat_i<288; stat_i=stat_i+1) begin
1511
                    codeLength[stat_i] <= 8;
1512
                end
1513
                numCodeLength <= 288;
1514
                cur_HF1 <= 0;
1515
                state <= 5'b00111;
1516
                // if cur_static < 288:
1517
                //     if cur_static < 144:
1518
                //         codeLength[cur_static].next = 8
1519
                //     elif cur_static < 256:
1520
                //         codeLength[cur_static].next = 9
1521
                //     elif cur_static < 280:
1522
                //         codeLength[cur_static].next = 7
1523
                //     else:
1524
                //         codeLength[cur_static].next = 8
1525
                //     cur_static.next = cur_static + 1
1526
                // else:
1527
                //     numCodeLength.next = 288
1528
                //     cur_HF1.next = 0
1529
                //     state.next = d_state.HF1
1530
            end
1531
            5'b00010: begin
1532
                if ((!filled)) begin
1533
                    filled <= 1'b1;
1534
                end
1535
                else if ((nb < 4)) begin
1536
                    // pass
1537
                end
1538
                else if ((numLiterals == 0)) begin
1539
                    numLiterals <= (257 + MYHDL31_get4(0, 5));
1540
                    $write("NL:");
1541
                    $write(" ");
1542
                    $write("%0d", (257 + MYHDL32_get4(0, 5)));
1543
                    $write("\n");
1544
                    numDistance <= (1 + MYHDL33_get4(5, 5));
1545
                    $write("ND:");
1546
                    $write(" ");
1547
                    $write("%0d", (1 + MYHDL34_get4(5, 5)));
1548
                    $write("\n");
1549
                    b_numCodeLength <= (4 + MYHDL35_get4(10, 4));
1550
                    $write("NCL:");
1551
                    $write(" ");
1552
                    $write("%0d", (4 + MYHDL36_get4(10, 4)));
1553
                    $write("\n");
1554
                    numCodeLength <= 0;
1555
                    MYHDL37_adv(14);
1556
                end
1557
                else begin
1558
                    if ((numCodeLength < 19)) begin
1559
                        case (numCodeLength)
1560
                            0: clo_i = 16;
1561
                            1: clo_i = 17;
1562
                            2: clo_i = 18;
1563
                            3: clo_i = 0;
1564
                            4: clo_i = 8;
1565
                            5: clo_i = 7;
1566
                            6: clo_i = 9;
1567
                            7: clo_i = 6;
1568
                            8: clo_i = 10;
1569
                            9: clo_i = 5;
1570
                            10: clo_i = 11;
1571
                            11: clo_i = 4;
1572
                            12: clo_i = 12;
1573
                            13: clo_i = 3;
1574
                            14: clo_i = 13;
1575
                            15: clo_i = 2;
1576
                            16: clo_i = 14;
1577
                            17: clo_i = 1;
1578
                            default: clo_i = 15;
1579
                        endcase
1580
                        if ((numCodeLength < b_numCodeLength)) begin
1581
                            codeLength[clo_i] <= MYHDL38_get4(0, 3);
1582
                            MYHDL39_adv(3);
1583
                        end
1584
                        else begin
1585
                            codeLength[clo_i] <= 0;
1586
                        end
1587
                        numCodeLength <= (numCodeLength + 1);
1588
                    end
1589
                    else begin
1590
                        numCodeLength <= 19;
1591
                        cur_HF1 <= 0;
1592
                        state <= 5'b00111;
1593
                    end
1594
                end
1595
            end
1596
            5'b00011: begin
1597
                if ((!filled)) begin
1598
                    filled <= 1'b1;
1599
                end
1600
                else if ((nb < 4)) begin
1601
                    // pass
1602
                end
1603
                else if ((numCodeLength < (numLiterals + numDistance))) begin
1604
                    n_adv = 0;
1605
                    if ((code < 16)) begin
1606
                        howOften <= 1;
1607
                        lastToken <= code;
1608
                    end
1609
                    else if ((code == 16)) begin
1610
                        howOften <= (3 + MYHDL40_get4(0, 2));
1611
                        n_adv = 2;
1612
                    end
1613
                    else if ((code == 17)) begin
1614
                        howOften <= (3 + MYHDL41_get4(0, 3));
1615
                        lastToken <= 0;
1616
                        n_adv = 3;
1617
                    end
1618
                    else if ((code == 18)) begin
1619
                        howOften <= (11 + MYHDL42_get4(0, 7));
1620
                        lastToken <= 0;
1621
                        n_adv = 7;
1622
                    end
1623
                    else begin
1624
                        $finish;
1625
                    end
1626
                    if ((n_adv != 0)) begin
1627
                        MYHDL43_adv(n_adv);
1628
                    end
1629
                    state <= 5'b00100;
1630
                end
1631
                else begin
1632
                    $write("FILL UP");
1633
                    $write("\n");
1634
                    for (dbl_i=0; dbl_i<32; dbl_i=dbl_i+1) begin
1635
                        dbl = 0;
1636
                        if (((dbl_i + $signed({1'b0, numLiterals})) < numCodeLength)) begin
1637
                            dbl = codeLength[(dbl_i + $signed({1'b0, numLiterals}))];
1638
                        end
1639
                        distanceLength[dbl_i] <= dbl;
1640
                    end
1641
                    cur_i <= numLiterals;
1642
                    state <= 5'b00110;
1643
                end
1644
            end
1645
            default: begin
1646
                if ((state == 5'b00110)) begin
1647
                    if ((cur_i < 288)) begin
1648
                        codeLength[cur_i] <= 0;
1649
                        cur_i <= (cur_i + 1);
1650
                    end
1651
                    else begin
1652
                        numCodeLength <= 288;
1653
                        method <= 3;
1654
                        cur_HF1 <= 0;
1655
                        state <= 5'b00111;
1656
                    end
1657
                end
1658
                else begin
1659
                    case (state)
1660
                        5'b00101: begin
1661
                            $write("DISTTREE");
1662
                            $write("\n");
1663
                            for (dist_i=0; dist_i<32; dist_i=dist_i+1) begin
1664
                                codeLength[dist_i] <= distanceLength[dist_i];
1665
                            end
1666
                            numCodeLength <= 32;
1667
                            method <= 4;
1668
                            cur_HF1 <= 0;
1669
                            state <= 5'b00111;
1670
                        end
1671
                        5'b00100: begin
1672
                            if ((howOften != 0)) begin
1673
                                codeLength[numCodeLength] <= lastToken;
1674
                                howOften <= (howOften - 1);
1675
                                numCodeLength <= (numCodeLength + 1);
1676
                            end
1677
                            else if ((numCodeLength < (numLiterals + numDistance))) begin
1678
                                cur_next <= 0;
1679
                                state <= 5'b10011;
1680
                            end
1681
                            else begin
1682
                                state <= 5'b00011;
1683
                            end
1684
                        end
1685
                        5'b00111: begin
1686
                            if ((cur_HF1 < 16)) begin
1687
                                bitLengthCount[cur_HF1] <= 0;
1688
                            end
1689
                            if ((cur_HF1 < 128)) begin
1690
                                d_leaves[cur_HF1] <= 0;
1691
                            end
1692
                            if (((method != 4) && (cur_HF1 < 512))) begin
1693
                                lwaddr <= cur_HF1;
1694
                                wleaf <= 0;
1695
                            end
1696
                            limit = 512;
1697
                            if ((method == 4)) begin
1698
                                limit = 128;
1699
                            end
1700
                            if ((cur_HF1 < limit)) begin
1701
                                cur_HF1 <= (cur_HF1 + 1);
1702
                            end
1703
                            else begin
1704
                                $write("DID HF1 INIT");
1705
                                $write("\n");
1706
                                cur_i <= 0;
1707
                                state <= 5'b01000;
1708
                            end
1709
                        end
1710
                        5'b01000: begin
1711
                            if ((cur_i < numCodeLength)) begin
1712
                                j = codeLength[cur_i];
1713
                                bitLengthCount[j] <= (bitLengthCount[j] + 1);
1714
                                cur_i <= (cur_i + 1);
1715
                            end
1716
                            else begin
1717
                                bitLengthCount[0] <= 0;
1718
                                state <= 5'b01001;
1719
                                cur_i <= 1;
1720
                                if ((method == 4)) begin
1721
                                    d_maxBits <= 0;
1722
                                end
1723
                                else begin
1724
                                    maxBits <= 0;
1725
                                end
1726
                                minBits <= 15;
1727
                            end
1728
                        end
1729
                        5'b01001: begin
1730
                            if ((cur_i <= 15)) begin
1731
                                if ((bitLengthCount[cur_i] != 0)) begin
1732
                                    if ((cur_i < minBits)) begin
1733
                                        minBits <= cur_i;
1734
                                    end
1735
                                    if ((method == 4)) begin
1736
                                        if ((cur_i > d_maxBits)) begin
1737
                                            d_maxBits <= cur_i;
1738
                                        end
1739
                                    end
1740
                                    else begin
1741
                                        if ((cur_i > maxBits)) begin
1742
                                            maxBits <= cur_i;
1743
                                        end
1744
                                    end
1745
                                end
1746
                                cur_i <= (cur_i + 1);
1747
                            end
1748
                            else begin
1749
                                $write("%h", minBits);
1750
                                $write(" ");
1751
                                $write("%h", maxBits);
1752
                                $write("\n");
1753
                                t = 10;
1754
                                if ((method == 4)) begin
1755
                                    if ((t > d_maxBits)) begin
1756
                                        t = d_maxBits;
1757
                                    end
1758
                                    d_instantMaxBit <= t;
1759
                                    d_instantMask <= ((1 << t) - 1);
1760
                                end
1761
                                else begin
1762
                                    if ((t > maxBits)) begin
1763
                                        t = maxBits;
1764
                                    end
1765
                                    instantMaxBit <= t;
1766
                                    instantMask <= ((1 << t) - 1);
1767
                                end
1768
                                $write("%0d", ((1 << t) - 1));
1769
                                $write("\n");
1770
                                state <= 5'b01010;
1771
                                cur_i <= minBits;
1772
                                code <= 0;
1773
                                for (hf2_i=0; hf2_i<15; hf2_i=hf2_i+1) begin
1774
                                    nextCode[hf2_i] <= 0;
1775
                                end
1776
                                $write("to HF3");
1777
                                $write("\n");
1778
                            end
1779
                        end
1780
                        5'b01010: begin
1781
                            amb = maxBits;
1782
                            if ((method == 4)) begin
1783
                                amb = d_maxBits;
1784
                            end
1785
                            if ((cur_i <= amb)) begin
1786
                                ncode = ((code + bitLengthCount[($signed({1'b0, cur_i}) - 1)]) << 1);
1787
                                code <= ncode;
1788
                                nextCode[cur_i] <= ncode;
1789
                                cur_i <= (cur_i + 1);
1790
                            end
1791
                            else begin
1792
                                state <= 5'b01011;
1793
                                cur_i <= 0;
1794
                                spread_i <= 0;
1795
                                $write("to HF4");
1796
                                $write("\n");
1797
                            end
1798
                        end
1799
                        5'b01100: begin
1800
                            canonical = nextCode[bits];
1801
                            nextCode[bits] <= (nextCode[bits] + 1);
1802
                            if ((bits > 15)) begin
1803
                                $finish;
1804
                            end
1805
                            reverse <= MYHDL50_rev_bits(canonical, bits);
1806
                            leaf <= MYHDL51_makeLeaf(spread_i, bits);
1807
                            state <= 5'b01101;
1808
                        end
1809
                        5'b01101: begin
1810
                            if ((method == 4)) begin
1811
                                d_leaves[reverse] <= leaf;
1812
                                if ((bits <= d_instantMaxBit)) begin
1813
                                    if (((reverse + (1 << bits)) <= d_instantMask)) begin
1814
                                        step <= (1 << bits);
1815
                                        spread <= (reverse + (1 << bits));
1816
                                        state <= 5'b10010;
1817
                                    end
1818
                                    else begin
1819
                                        spread_i <= (spread_i + 1);
1820
                                        state <= 5'b01011;
1821
                                    end
1822
                                end
1823
                                else begin
1824
                                    state <= 5'b01011;
1825
                                    spread_i <= (spread_i + 1);
1826
                                end
1827
                            end
1828
                            else begin
1829
                                wleaf <= leaf;
1830
                                lwaddr <= reverse;
1831
                                code_bits[spread_i] <= reverse;
1832
                                if ((bits <= instantMaxBit)) begin
1833
                                    if (((reverse + (1 << bits)) <= instantMask)) begin
1834
                                        step <= (1 << bits);
1835
                                        spread <= (reverse + (1 << bits));
1836
                                        state <= 5'b10010;
1837
                                    end
1838
                                    else begin
1839
                                        spread_i <= (spread_i + 1);
1840
                                        state <= 5'b01011;
1841
                                    end
1842
                                end
1843
                                else begin
1844
                                    spread_i <= (spread_i + 1);
1845
                                    state <= 5'b01011;
1846
                                end
1847
                            end
1848
                        end
1849
                        5'b01011: begin
1850
                            if ((spread_i < numCodeLength)) begin
1851
                                bits_next = codeLength[spread_i];
1852
                                if ((bits_next != 0)) begin
1853
                                    bits <= bits_next;
1854
                                    state <= 5'b01100;
1855
                                end
1856
                                else begin
1857
                                    spread_i <= (spread_i + 1);
1858
                                end
1859
                            end
1860
                            else begin
1861
                                if (do_compress) begin
1862
                                    state <= 5'b10110;
1863
                                    cur_cstatic <= 0;
1864
                                end
1865
                                else if ((method == 3)) begin
1866
                                    state <= 5'b00101;
1867
                                end
1868
                                else if ((method == 4)) begin
1869
                                    $write("DEFLATE m2!");
1870
                                    $write("\n");
1871
                                    state <= 5'b10011;
1872
                                end
1873
                                else if ((method == 2)) begin
1874
                                    numCodeLength <= 0;
1875
                                    state <= 5'b10011;
1876
                                end
1877
                                else begin
1878
                                    state <= 5'b10011;
1879
                                end
1880
                                cur_next <= 0;
1881
                                cur_i <= 0;
1882
                            end
1883
                        end
1884
                        5'b10010: begin
1885
                            if ((method == 4)) begin
1886
                                d_leaves[spread] <= MYHDL52_makeLeaf(spread_i, codeLength[spread_i]);
1887
                            end
1888
                            else begin
1889
                                lwaddr <= spread;
1890
                                wleaf <= MYHDL53_makeLeaf(spread_i, codeLength[spread_i]);
1891
                            end
1892
                            aim = instantMask;
1893
                            if ((method == 4)) begin
1894
                                aim = d_instantMask;
1895
                            end
1896
                            if (($signed({1'b0, spread}) > ($signed({1'b0, aim}) - $signed({1'b0, step})))) begin
1897
                                spread_i <= (spread_i + 1);
1898
                                state <= 5'b01011;
1899
                            end
1900
                            else begin
1901
                                spread <= (spread + step);
1902
                            end
1903
                        end
1904
                        5'b10011: begin
1905
                            if ((!filled)) begin
1906
                                filled <= 1'b1;
1907
                            end
1908
                            else if ((nb < 4)) begin
1909
                                // pass
1910
                            end
1911
                            else if ((cur_next == 0)) begin
1912
                                cto = MYHDL54_get4(0, maxBits);
1913
                                cur_next <= 1;
1914
                                mask = ((1 << instantMaxBit) - 1);
1915
                                leaf <= leaves[(cto & mask)];
1916
                            end
1917
                            else begin
1918
                                if ((MYHDL55_get_bits(leaf) < 1)) begin
1919
                                    $write("< 1 bits: ");
1920
                                    $write("\n");
1921
                                    $finish;
1922
                                end
1923
                                MYHDL57_adv(MYHDL56_get_bits(leaf));
1924
                                if ((MYHDL58_get_code(leaf) == 0)) begin
1925
                                    $write("leaf 0");
1926
                                    $write("\n");
1927
                                end
1928
                                code <= MYHDL59_get_code(leaf);
1929
                                if ((method == 2)) begin
1930
                                    state <= 5'b00011;
1931
                                end
1932
                                else begin
1933
                                    state <= 5'b10100;
1934
                                end
1935
                            end
1936
                        end
1937
                        5'b01111: begin
1938
                            if ((!filled)) begin
1939
                                filled <= 1'b1;
1940
                            end
1941
                            else if ((nb < 4)) begin
1942
                                // pass
1943
                            end
1944
                            else begin
1945
                                token = (code - 257);
1946
                                case (token)
1947
                                    0: extraLength = 0;
1948
                                    1: extraLength = 0;
1949
                                    2: extraLength = 0;
1950
                                    3: extraLength = 0;
1951
                                    4: extraLength = 0;
1952
                                    5: extraLength = 0;
1953
                                    6: extraLength = 0;
1954
                                    7: extraLength = 0;
1955
                                    8: extraLength = 1;
1956
                                    9: extraLength = 1;
1957
                                    10: extraLength = 1;
1958
                                    11: extraLength = 1;
1959
                                    12: extraLength = 2;
1960
                                    13: extraLength = 2;
1961
                                    14: extraLength = 2;
1962
                                    15: extraLength = 2;
1963
                                    16: extraLength = 3;
1964
                                    17: extraLength = 3;
1965
                                    18: extraLength = 3;
1966
                                    19: extraLength = 3;
1967
                                    20: extraLength = 4;
1968
                                    21: extraLength = 4;
1969
                                    22: extraLength = 4;
1970
                                    23: extraLength = 4;
1971
                                    24: extraLength = 5;
1972
                                    25: extraLength = 5;
1973
                                    26: extraLength = 5;
1974
                                    27: extraLength = 5;
1975
                                    default: extraLength = 0;
1976
                                endcase
1977
                                cto = MYHDL60_get4(extraLength, d_maxBits);
1978
                                mask = ((1 << d_instantMaxBit) - 1);
1979
                                leaf <= d_leaves[(cto & mask)];
1980
                                state <= 5'b10000;
1981
                            end
1982
                        end
1983
                        5'b10000: begin
1984
                            if ((MYHDL61_get_bits(leaf) == 0)) begin
1985
                                $finish;
1986
                            end
1987
                            token = (code - 257);
1988
                            case (token)
1989
                                0: tlength = 3;
1990
                                1: tlength = 4;
1991
                                2: tlength = 5;
1992
                                3: tlength = 6;
1993
                                4: tlength = 7;
1994
                                5: tlength = 8;
1995
                                6: tlength = 9;
1996
                                7: tlength = 10;
1997
                                8: tlength = 11;
1998
                                9: tlength = 13;
1999
                                10: tlength = 15;
2000
                                11: tlength = 17;
2001
                                12: tlength = 19;
2002
                                13: tlength = 23;
2003
                                14: tlength = 27;
2004
                                15: tlength = 31;
2005
                                16: tlength = 35;
2006
                                17: tlength = 43;
2007
                                18: tlength = 51;
2008
                                19: tlength = 59;
2009
                                20: tlength = 67;
2010
                                21: tlength = 83;
2011
                                22: tlength = 99;
2012
                                23: tlength = 115;
2013
                                24: tlength = 131;
2014
                                25: tlength = 163;
2015
                                26: tlength = 195;
2016
                                27: tlength = 227;
2017
                                default: tlength = 258;
2018
                            endcase
2019
                            case (token)
2020
                                0: extraLength = 0;
2021
                                1: extraLength = 0;
2022
                                2: extraLength = 0;
2023
                                3: extraLength = 0;
2024
                                4: extraLength = 0;
2025
                                5: extraLength = 0;
2026
                                6: extraLength = 0;
2027
                                7: extraLength = 0;
2028
                                8: extraLength = 1;
2029
                                9: extraLength = 1;
2030
                                10: extraLength = 1;
2031
                                11: extraLength = 1;
2032
                                12: extraLength = 2;
2033
                                13: extraLength = 2;
2034
                                14: extraLength = 2;
2035
                                15: extraLength = 2;
2036
                                16: extraLength = 3;
2037
                                17: extraLength = 3;
2038
                                18: extraLength = 3;
2039
                                19: extraLength = 3;
2040
                                20: extraLength = 4;
2041
                                21: extraLength = 4;
2042
                                22: extraLength = 4;
2043
                                23: extraLength = 4;
2044
                                24: extraLength = 5;
2045
                                25: extraLength = 5;
2046
                                26: extraLength = 5;
2047
                                27: extraLength = 5;
2048
                                default: extraLength = 0;
2049
                            endcase
2050
                            tlength = tlength + MYHDL62_get4(0, extraLength);
2051
                            distanceCode = MYHDL63_get_code(leaf);
2052
                            case (distanceCode)
2053
                                0: distance = 1;
2054
                                1: distance = 2;
2055
                                2: distance = 3;
2056
                                3: distance = 4;
2057
                                4: distance = 5;
2058
                                5: distance = 7;
2059
                                6: distance = 9;
2060
                                7: distance = 13;
2061
                                8: distance = 17;
2062
                                9: distance = 25;
2063
                                10: distance = 33;
2064
                                11: distance = 49;
2065
                                12: distance = 65;
2066
                                13: distance = 97;
2067
                                14: distance = 129;
2068
                                15: distance = 193;
2069
                                16: distance = 257;
2070
                                17: distance = 385;
2071
                                18: distance = 513;
2072
                                19: distance = 769;
2073
                                20: distance = 1025;
2074
                                21: distance = 1537;
2075
                                22: distance = 2049;
2076
                                23: distance = 3073;
2077
                                24: distance = 4097;
2078
                                25: distance = 6145;
2079
                                26: distance = 8193;
2080
                                27: distance = 12289;
2081
                                28: distance = 16385;
2082
                                default: distance = 24577;
2083
                            endcase
2084
                            case ($signed(distanceCode >>> 1))
2085
                                0: moreBits = 0;
2086
                                1: moreBits = 0;
2087
                                2: moreBits = 1;
2088
                                3: moreBits = 2;
2089
                                4: moreBits = 3;
2090
                                5: moreBits = 4;
2091
                                6: moreBits = 5;
2092
                                7: moreBits = 6;
2093
                                8: moreBits = 7;
2094
                                9: moreBits = 8;
2095
                                10: moreBits = 9;
2096
                                11: moreBits = 10;
2097
                                12: moreBits = 11;
2098
                                13: moreBits = 12;
2099
                                default: moreBits = 13;
2100
                            endcase
2101
                            mored = MYHDL65_get4((extraLength + MYHDL64_get_bits(leaf)), moreBits);
2102
                            distance = distance + mored;
2103
                            MYHDL67_adv(((moreBits + extraLength) + MYHDL66_get_bits(leaf)));
2104
                            offset <= ($signed({1'b0, do}) - distance);
2105
                            length <= tlength;
2106
                            cur_i <= 0;
2107
                            oraddr <= offset;
2108
                            state <= 5'b10101;
2109
                        end
2110
                        default: begin
2111
                            if ((state == 5'b10100)) begin
2112
                                if ((!filled)) begin
2113
                                    filled <= 1'b1;
2114
                                end
2115
                                else if ((nb < 4)) begin
2116
                                    // pass
2117
                                end
2118
                                else if (($signed({1'b0, di}) > ($signed({1'b0, isize}) - 3))) begin
2119
                                    state <= 5'b00000;
2120
                                    o_done <= 1'b1;
2121
                                    $write("NO EOF ");
2122
                                    $write(" ");
2123
                                    $write("%h", di);
2124
                                    $write("\n");
2125
                                    $finish;
2126
                                end
2127
                                else if ((code == 256)) begin
2128
                                    $write("EOF:");
2129
                                    $write(" ");
2130
                                    $write("%h", di);
2131
                                    $write(" ");
2132
                                    $write("%h", do);
2133
                                    $write("\n");
2134
                                    if ((!final)) begin
2135
                                        state <= 5'b00001;
2136
                                    end
2137
                                    else begin
2138
                                        o_done <= 1'b1;
2139
                                        o_oprogress <= do;
2140
                                        state <= 5'b00000;
2141
                                    end
2142
                                end
2143
                                else begin
2144
                                    if ((code < 256)) begin
2145
                                        oaddr <= do;
2146
                                        obyte <= code;
2147
                                        o_oprogress <= (do + 1);
2148
                                        do <= (do + 1);
2149
                                        cur_next <= 0;
2150
                                        state <= 5'b10011;
2151
                                    end
2152
                                    else if ((code == 300)) begin
2153
                                        $finish;
2154
                                    end
2155
                                    else begin
2156
                                        if (static) begin
2157
                                            token = (code - 257);
2158
                                            case (token)
2159
                                                0: tlength = 3;
2160
                                                1: tlength = 4;
2161
                                                2: tlength = 5;
2162
                                                3: tlength = 6;
2163
                                                4: tlength = 7;
2164
                                                5: tlength = 8;
2165
                                                6: tlength = 9;
2166
                                                7: tlength = 10;
2167
                                                8: tlength = 11;
2168
                                                9: tlength = 13;
2169
                                                10: tlength = 15;
2170
                                                11: tlength = 17;
2171
                                                12: tlength = 19;
2172
                                                13: tlength = 23;
2173
                                                14: tlength = 27;
2174
                                                15: tlength = 31;
2175
                                                16: tlength = 35;
2176
                                                17: tlength = 43;
2177
                                                18: tlength = 51;
2178
                                                19: tlength = 59;
2179
                                                20: tlength = 67;
2180
                                                21: tlength = 83;
2181
                                                22: tlength = 99;
2182
                                                23: tlength = 115;
2183
                                                24: tlength = 131;
2184
                                                25: tlength = 163;
2185
                                                26: tlength = 195;
2186
                                                27: tlength = 227;
2187
                                                default: tlength = 258;
2188
                                            endcase
2189
                                            case (token)
2190
                                                0: extraLength = 0;
2191
                                                1: extraLength = 0;
2192
                                                2: extraLength = 0;
2193
                                                3: extraLength = 0;
2194
                                                4: extraLength = 0;
2195
                                                5: extraLength = 0;
2196
                                                6: extraLength = 0;
2197
                                                7: extraLength = 0;
2198
                                                8: extraLength = 1;
2199
                                                9: extraLength = 1;
2200
                                                10: extraLength = 1;
2201
                                                11: extraLength = 1;
2202
                                                12: extraLength = 2;
2203
                                                13: extraLength = 2;
2204
                                                14: extraLength = 2;
2205
                                                15: extraLength = 2;
2206
                                                16: extraLength = 3;
2207
                                                17: extraLength = 3;
2208
                                                18: extraLength = 3;
2209
                                                19: extraLength = 3;
2210
                                                20: extraLength = 4;
2211
                                                21: extraLength = 4;
2212
                                                22: extraLength = 4;
2213
                                                23: extraLength = 4;
2214
                                                24: extraLength = 5;
2215
                                                25: extraLength = 5;
2216
                                                26: extraLength = 5;
2217
                                                27: extraLength = 5;
2218
                                                default: extraLength = 0;
2219
                                            endcase
2220
                                            tlength = tlength + MYHDL68_get4(0, extraLength);
2221
                                            t = MYHDL69_get4(extraLength, 5);
2222
                                            distanceCode = MYHDL70_rev_bits(t, 5);
2223
                                            case (distanceCode)
2224
                                                0: distance = 1;
2225
                                                1: distance = 2;
2226
                                                2: distance = 3;
2227
                                                3: distance = 4;
2228
                                                4: distance = 5;
2229
                                                5: distance = 7;
2230
                                                6: distance = 9;
2231
                                                7: distance = 13;
2232
                                                8: distance = 17;
2233
                                                9: distance = 25;
2234
                                                10: distance = 33;
2235
                                                11: distance = 49;
2236
                                                12: distance = 65;
2237
                                                13: distance = 97;
2238
                                                14: distance = 129;
2239
                                                15: distance = 193;
2240
                                                16: distance = 257;
2241
                                                17: distance = 385;
2242
                                                18: distance = 513;
2243
                                                19: distance = 769;
2244
                                                20: distance = 1025;
2245
                                                21: distance = 1537;
2246
                                                22: distance = 2049;
2247
                                                23: distance = 3073;
2248
                                                24: distance = 4097;
2249
                                                25: distance = 6145;
2250
                                                26: distance = 8193;
2251
                                                27: distance = 12289;
2252
                                                28: distance = 16385;
2253
                                                default: distance = 24577;
2254
                                            endcase
2255
                                            case ($signed(distanceCode >>> 1))
2256
                                                0: moreBits = 0;
2257
                                                1: moreBits = 0;
2258
                                                2: moreBits = 1;
2259
                                                3: moreBits = 2;
2260
                                                4: moreBits = 3;
2261
                                                5: moreBits = 4;
2262
                                                6: moreBits = 5;
2263
                                                7: moreBits = 6;
2264
                                                8: moreBits = 7;
2265
                                                9: moreBits = 8;
2266
                                                10: moreBits = 9;
2267
                                                11: moreBits = 10;
2268
                                                12: moreBits = 11;
2269
                                                13: moreBits = 12;
2270
                                                default: moreBits = 13;
2271
                                            endcase
2272
                                            distance = distance + MYHDL71_get4((extraLength + 5), moreBits);
2273
                                            MYHDL72_adv(((extraLength + 5) + moreBits));
2274
                                            offset <= ($signed({1'b0, do}) - distance);
2275
                                            length <= tlength;
2276
                                            cur_i <= 0;
2277
                                            oraddr <= offset;
2278
                                            state <= 5'b10101;
2279
                                        end
2280
                                        else begin
2281
                                            state <= 5'b01111;
2282
                                        end
2283
                                    end
2284
                                    cur_next <= 0;
2285
                                end
2286
                            end
2287
                            else begin
2288
                                if ((state == 5'b10101)) begin
2289
                                    if ((!filled)) begin
2290
                                        filled <= 1'b1;
2291
                                    end
2292
                                    else if ((nb < 4)) begin
2293
                                        // pass
2294
                                    end
2295
                                    else if ((method == 0)) begin
2296
                                        if ((cur_i < length)) begin
2297
                                            oaddr <= do;
2298
                                            obyte <= b3;
2299
                                            MYHDL73_adv(8);
2300
                                            cur_i <= (cur_i + 1);
2301
                                            do <= (do + 1);
2302
                                            o_oprogress <= (do + 1);
2303
                                        end
2304
                                        else if ((!final)) begin
2305
                                            state <= 5'b00001;
2306
                                        end
2307
                                        else begin
2308
                                            o_oprogress <= do;
2309
                                            o_done <= 1'b1;
2310
                                            state <= 5'b00000;
2311
                                        end
2312
                                    end
2313
                                    else if ((cur_i < (length + 1))) begin
2314
                                        oraddr <= (offset + cur_i);
2315
                                        if ((cur_i == 1)) begin
2316
                                            copy1 <= orbyte;
2317
                                        end
2318
                                        if ((cur_i > 1)) begin
2319
                                            if (((offset + cur_i) == (do + 1))) begin
2320
                                                obyte <= copy1;
2321
                                            end
2322
                                            else begin
2323
                                                obyte <= orbyte;
2324
                                            end
2325
                                            oaddr <= do;
2326
                                            o_oprogress <= (do + 1);
2327
                                            do <= (do + 1);
2328
                                        end
2329
                                        cur_i <= (cur_i + 1);
2330
                                    end
2331
                                    else begin
2332
                                        oaddr <= do;
2333
                                        if (((offset + cur_i) == (do + 1))) begin
2334
                                            obyte <= copy1;
2335
                                        end
2336
                                        else begin
2337
                                            obyte <= orbyte;
2338
                                        end
2339
                                        do <= (do + 1);
2340
                                        o_oprogress <= (do + 1);
2341
                                        cur_next <= 0;
2342
                                        state <= 5'b10011;
2343
                                    end
2344
                                end
2345
                                else begin
2346
                                    $write("unknown state?!");
2347
                                    $write("\n");
2348
                                    state <= 5'b00000;
2349
                                end
2350
                            end
2351
                        end
2352
                    endcase
2353
                end
2354
            end
2355
        endcase
2356
    end
2357
end
2358
 
2359
 
2360
always @(posedge clk) begin: DEFLATE_FILL_BUF
2361
    if ((!reset)) begin
2362
        $write("FILL RESET");
2363
        $write("\n");
2364
        nb <= 0;
2365
        b1 <= 0;
2366
        b2 <= 0;
2367
        b3 <= 0;
2368
        b4 <= 0;
2369
    end
2370
    else begin
2371
        if ((isize < 4)) begin
2372
            // pass
2373
        end
2374
        else if (((i_mode == 4) || (i_mode == 5))) begin
2375
            nb <= 0;
2376
        end
2377
        else begin
2378
            nb <= 4;
2379
            b1 <= iram[(di & 127)];
2380
            b2 <= iram[((di + 1) & 127)];
2381
            b3 <= iram[((di + 2) & 127)];
2382
            b4 <= iram[((di + 3) & 127)];
2383
        end
2384
    end
2385
end
2386
 
2387
 
2388
always @(posedge clk) begin: DEFLATE_ORAMWRITE
2389
    oram[oaddr] <= obyte;
2390
    leaves[lwaddr] <= wleaf;
2391
end
2392
 
2393
 
2394
always @(posedge clk) begin: DEFLATE_ORAMREAD
2395
    orbyte <= oram[oraddr];
2396
end
2397
 
2398
endmodule

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