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[/] [hf-risc/] [trunk/] [hf-risc/] [peripherals/] [xtea/] [xtea.vhd] - Blame information for rev 13

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1 13 serginhofr
--XTEA encryption algorithm v0.3
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--Sergio Johann Filho, 2016
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--
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--based on reference code (below) released into the public domain by David Wheeler and Roger Needham
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--the code takes 64 bits of data in v[0] and v[1] and 128 bits of key in key[0] - key[3]
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--recommended number of rounds is 32 (2 Feistel-network rounds are performed on each iteration).
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--
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--
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--void encipher(uint32_t num_rounds, uint32_t v[2], uint32_t const key[4]){
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--      uint32_t i;
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--      uint32_t v0 = v[0], v1 = v[1], sum = 0, delta = 0x9E3779B9;
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--
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--      for (i = 0; i < num_rounds; i++){
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--              v0 += (((v1 << 4) ^ (v1 >> 5)) + v1) ^ (sum + key[sum & 3]);
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--              sum += delta;
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--              v1 += (((v0 << 4) ^ (v0 >> 5)) + v0) ^ (sum + key[(sum>>11) & 3]);
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--      }
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--      v[0] = v0; v[1] = v1;
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--}
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--
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--void decipher(uint32_t num_rounds, uint32_t v[2], uint32_t const key[4]){
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--      uint32_t i;
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--      uint32_t v0 = v[0], v1 = v[1], delta = 0x9E3779B9, sum = delta * num_rounds;
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--
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--      for (i = 0; i < num_rounds; i++){
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--              v1 -= (((v0 << 4) ^ (v0 >> 5)) + v0) ^ (sum + key[(sum>>11) & 3]);
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--              sum -= delta;
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--              v0 -= (((v1 << 4) ^ (v1 >> 5)) + v1) ^ (sum + key[sum & 3]);
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--      }
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--      v[0] = v0; v[1] = v1;
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--}
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity xtea is
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        generic (
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                ROUNDS: integer := 32
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        );
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        port (  clock: in std_logic;
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                reset: in std_logic;
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                start: in std_logic;
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                encrypt: in std_logic;
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                key: in std_logic_vector(127 downto 0);
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                input: in std_logic_vector(63 downto 0);
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                output: out std_logic_vector(63 downto 0);
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                ready: out std_logic
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        );
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end xtea;
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architecture xtea_arch of xtea is
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        type states is (idle, enc_step1, enc_step2, enc_step3, dec_step1, dec_step2, dec_step3, key_sel1, key_sel2, done);
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        signal state: states;
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        signal v0, v1, sum, delta, key_sel: std_logic_vector(31 downto 0);
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        signal counter: std_logic_vector(7 downto 0);
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begin
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        delta <= x"9e3779b9";
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        process(clock, reset)
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        begin
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                if reset = '1' then
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                        v0 <= (others => '0');
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                        v1 <= (others => '0');
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                        sum <= (others => '0');
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                        key_sel <= (others => '0');
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                        counter <= (others => '0');
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                        output <= (others => '0');
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                        ready <= '0';
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                elsif clock'event and clock = '1' then
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                        case state is
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                                when idle =>
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                                        ready <= '0';
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                                        counter <= (others => '0');
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                                when key_sel1 =>
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                                        case sum(1 downto 0) is
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                                                when "00" =>
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                                                        key_sel <= key(127 downto 96);
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                                                when "01" =>
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                                                        key_sel <= key(95 downto 64);
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                                                when "10" =>
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                                                        key_sel <= key(63 downto 32);
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                                                when "11" =>
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                                                        key_sel <= key(31 downto 0);
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                                                when others => null;
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                                        end case;
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                                when key_sel2 =>
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                                        case sum(12 downto 11) is
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                                                when "00" =>
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                                                        key_sel <= key(127 downto 96);
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                                                when "01" =>
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                                                        key_sel <= key(95 downto 64);
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                                                when "10" =>
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                                                        key_sel <= key(63 downto 32);
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                                                when "11" =>
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                                                        key_sel <= key(31 downto 0);
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                                                when others => null;
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                                        end case;
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                                when enc_step1 =>
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                                        v1 <= input(31 downto 0);
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                                        v0 <= input(63 downto 32);
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                                        sum <= (others => '0');
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                                when enc_step2 =>
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                                        v0 <= v0 + ((((v1(27 downto 0) & "0000") xor ("00000" & v1(31 downto 5))) + v1) xor (sum + key_sel));
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                                        sum <= sum + delta;
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                                when enc_step3 =>
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                                        v1 <= v1 + ((((v0(27 downto 0) & "0000") xor ("00000" & v0(31 downto 5))) + v0) xor (sum + key_sel));
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                                        counter <= counter + 1;
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                                when dec_step1 =>
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                                        v1 <= input(31 downto 0);
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                                        v0 <= input(63 downto 32);
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                                        sum <= x"c6ef3720";
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                                when dec_step2 =>
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                                        v1 <= v1 - ((((v0(27 downto 0) & "0000") xor ("00000" & v0(31 downto 5))) + v0) xor (sum + key_sel));
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                                        sum <= sum - delta;
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                                when dec_step3 =>
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                                        v0 <= v0 - ((((v1(27 downto 0) & "0000") xor ("00000" & v1(31 downto 5))) + v1) xor (sum + key_sel));
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                                        counter <= counter + 1;
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                                when done =>
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                                        output(63 downto 32) <= v0;
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                                        output(31 downto 0) <= v1;
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                                        ready <= '1';
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                                when others => null;
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                        end case;
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                end if;
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        end process;
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        process(clock, reset, state, counter, start, encrypt)
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        begin
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                if reset = '1' then
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                        state <= idle;
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                elsif clock'event and clock = '1' then
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                        case state is
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                                when idle =>
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                                        if (start = '1') then
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                                                if (encrypt = '1') then
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                                                        state <= enc_step1;
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                                                else
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                                                        state <= dec_step1;
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                                                end if;
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                                        else
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                                                state <= idle;
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                                        end if;
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                                when key_sel1 =>
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                                        if (encrypt = '1') then
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                                                state <= enc_step2;
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                                        else
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                                                state <= dec_step3;
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                                        end if;
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                                when key_sel2 =>
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                                        if (encrypt = '1') then
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                                                state <= enc_step3;
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                                        else
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                                                state <= dec_step2;
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                                        end if;
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                                when enc_step1 => state <= key_sel1;
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                                when enc_step2 => state <= key_sel2;
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                                when enc_step3 =>
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                                        if (counter < ROUNDS-1) then
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                                                state <= key_sel1;
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                                        else
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                                                state <= done;
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                                        end if;
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                                when dec_step1 => state <= key_sel2;
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                                when dec_step2 => state <= key_sel1;
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                                when dec_step3 =>
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                                        if (counter < ROUNDS-1) then
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                                                state <= key_sel2;
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                                        else
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                                                state <= done;
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                                        end if;
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                                when done =>
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                                        if (start = '1') then
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                                                state <= done;
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                                        else
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                                                state <= idle;
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                                        end if;
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                                when others => null;
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                        end case;
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                end if;
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        end process;
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end xtea_arch;
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