URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

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[/] [hf-risc/] [trunk/] [hf-risc/] [platform/] [virtex4_ml403/] [virtex4ml403.vhd] - Blame information for rev 18

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hfrisc_soc is
        generic(
                address_width: integer := 16;
                memory_file : string := "code.txt";
                uart_support : string := "yes"
        );
        port (  clk_in:         in std_logic;
                reset_in:       in std_logic;
                uart_read:      in std_logic;
                uart_write:     out std_logic
        );
end hfrisc_soc;
 
architecture top_level of hfrisc_soc is
        signal clock, reset, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, rff1, ram_dly: std_logic;
        signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
        signal ext_irq: std_logic_vector(7 downto 0);
        signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
begin
        -- clock divider (50MHz clock from 100MHz main clock for ML403 kit)
        process (reset, clk_in, clock)
        begin
                if reset = '1' then
                        clock <= '0';
                else
                        if clk_in'event and clk_in='1' then
                                clock <= not clock;
                        end if;
                end if;
        end process;
 
        -- reset synchronizer
        process (clock, reset_in)
        begin
                if (reset_in = '0') then
                        rff1 <= '1';
                        reset <= '1';
                elsif (clock'event and clock = '1') then
                        rff1 <= '0';
                        reset <= rff1;
                end if;
        end process;
 
        process(clk_in, reset, ram_enable_n)
        begin
                if reset = '1' then
                        ram_dly <= '0';
                elsif clk_in'event and clk_in = '1' then
                        ram_dly <= not ram_enable_n;
                end if;
        end process;
 
        ext_irq <= "00000000";
 
        stall <= '0';
        boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
        ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
        data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
        data_w_n_ram <= not data_we;
 
        -- HF-RISC core
        core: entity work.datapath
        port map(       clock => clock,
                        reset => reset,
                        stall => stall_cpu,
                        irq_vector => irq_vector_cpu,
                        irq => irq_cpu,
                        irq_ack => irq_ack_cpu,
                        address => address_cpu,
                        data_in => data_in_cpu,
                        data_out => data_out_cpu,
                        data_w => data_w_cpu,
                        data_access => data_access_cpu
        );
 
        -- peripherals / busmux logic
        peripherals_busmux: entity work.busmux
        generic map(
                uart_support => uart_support
        )
        port map(
                clock => clock,
                reset => reset,
 
                stall => stall,
 
                stall_cpu => stall_cpu,
                irq_vector_cpu => irq_vector_cpu,
                irq_cpu => irq_cpu,
                irq_ack_cpu => irq_ack_cpu,
                address_cpu => address_cpu,
                data_in_cpu => data_in_cpu,
                data_out_cpu => data_out_cpu,
                data_w_cpu => data_w_cpu,
                data_access_cpu => data_access_cpu,
 
                addr_mem => address,
                data_read_mem => data_read,
                data_write_mem => data_write,
                data_we_mem => data_we,
                extio_in => ext_irq,
                extio_out => open,
                uart_read => uart_read,
                uart_write => uart_write
        );
 
        -- instruction and data memory (boot RAM)
        boot_ram: entity work.ram
        generic map (memory_type => "DEFAULT")
        port map (
                clk                     => clock,
                enable                  => boot_enable,
                write_byte_enable       => "0000",
                address                 => address(31 downto 2),
                data_write              => (others => '0'),
                data_read               => data_read_boot
        );
 
        -- instruction and data memory (external RAM)
        memory0lb: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 0)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(0),
                data_i  => data_write(7 downto 0),
                data_o  => data_read_ram(7 downto 0)
        );
 
        memory0ub: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 1)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(1),
                data_i  => data_write(15 downto 8),
                data_o  => data_read_ram(15 downto 8)
        );
 
        memory1lb: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 2)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(2),
                data_i  => data_write(23 downto 16),
                data_o  => data_read_ram(23 downto 16)
        );
 
        memory1ub: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 3)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(3),
                data_i  => data_write(31 downto 24),
                data_o  => data_read_ram(31 downto 24)
        );
 
end top_level;
 

Line No.	Rev	Author	Line
1	13	serginhofr	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_unsigned.all;`
4
5	18	serginhofr	`entity hfrisc_soc is`
6	13	serginhofr	`generic(`
7			`address_width: integer := 16;`
8			`memory_file : string := "code.txt";`
9			`uart_support : string := "yes"`
10			`);`
11			`port ( clk_in: in std_logic;`
12			`reset_in: in std_logic;`
13			`uart_read: in std_logic;`
14			`uart_write: out std_logic`
15			`);`
16	18	serginhofr	`end hfrisc_soc;`
17	13	serginhofr
18	18	serginhofr	`architecture top_level of hfrisc_soc is`
19			`signal clock, reset, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, rff1, ram_dly: std_logic;`
20			`signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);`
21	13	serginhofr	`signal ext_irq: std_logic_vector(7 downto 0);`
22			`signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);`
23			`begin`
24			`-- clock divider (50MHz clock from 100MHz main clock for ML403 kit)`
25			`process (reset, clk_in, clock)`
26			`begin`
27			`if reset = '1' then`
28			`clock <= '0';`
29			`else`
30			`if clk_in'event and clk_in='1' then`
31			`clock <= not clock;`
32			`end if;`
33			`end if;`
34			`end process;`
35
36			`-- reset synchronizer`
37			`process (clock, reset_in)`
38			`begin`
39			`if (reset_in = '0') then`
40			`rff1 <= '1';`
41			`reset <= '1';`
42			`elsif (clock'event and clock = '1') then`
43			`rff1 <= '0';`
44			`reset <= rff1;`
45			`end if;`
46			`end process;`
47
48			`process(clk_in, reset, ram_enable_n)`
49			`begin`
50			`if reset = '1' then`
51			`ram_dly <= '0';`
52			`elsif clk_in'event and clk_in = '1' then`
53			`ram_dly <= not ram_enable_n;`
54			`end if;`
55			`end process;`
56
57			`ext_irq <= "00000000";`
58
59			`stall <= '0';`
60			`boot_enable <= '1' when address(31 downto 28) = "0000" else '0';`
61			`ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';`
62			`data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;`
63			`data_w_n_ram <= not data_we;`
64
65			`-- HF-RISC core`
66			`core: entity work.datapath`
67			`port map( clock => clock,`
68			`reset => reset,`
69			`stall => stall_cpu,`
70			`irq_vector => irq_vector_cpu,`
71			`irq => irq_cpu,`
72			`irq_ack => irq_ack_cpu,`
73	18	serginhofr	`address => address_cpu,`
74	13	serginhofr	`data_in => data_in_cpu,`
75			`data_out => data_out_cpu,`
76			`data_w => data_w_cpu,`
77			`data_access => data_access_cpu`
78			`);`
79
80			`-- peripherals / busmux logic`
81			`peripherals_busmux: entity work.busmux`
82			`generic map(`
83			`uart_support => uart_support`
84			`)`
85			`port map(`
86			`clock => clock,`
87			`reset => reset,`
88
89			`stall => stall,`
90
91			`stall_cpu => stall_cpu,`
92			`irq_vector_cpu => irq_vector_cpu,`
93			`irq_cpu => irq_cpu,`
94			`irq_ack_cpu => irq_ack_cpu,`
95	18	serginhofr	`address_cpu => address_cpu,`
96	13	serginhofr	`data_in_cpu => data_in_cpu,`
97			`data_out_cpu => data_out_cpu,`
98			`data_w_cpu => data_w_cpu,`
99			`data_access_cpu => data_access_cpu,`
100
101			`addr_mem => address,`
102			`data_read_mem => data_read,`
103			`data_write_mem => data_write,`
104			`data_we_mem => data_we,`
105			`extio_in => ext_irq,`
106			`extio_out => open,`
107			`uart_read => uart_read,`
108			`uart_write => uart_write`
109			`);`
110
111			`-- instruction and data memory (boot RAM)`
112			`boot_ram: entity work.ram`
113			`generic map (memory_type => "DEFAULT")`
114			`port map (`
115			`clk => clock,`
116			`enable => boot_enable,`
117			`write_byte_enable => "0000",`
118			`address => address(31 downto 2),`
119			`data_write => (others => '0'),`
120			`data_read => data_read_boot`
121			`);`
122
123			`-- instruction and data memory (external RAM)`
124			`memory0lb: entity work.bram`
125			`generic map ( memory_file => memory_file,`
126			`data_width => 8,`
127			`address_width => address_width,`
128			`bank => 0)`
129			`port map(`
130			`clk => clock,`
131			`addr => address(address_width -1 downto 2),`
132			`cs_n => ram_enable_n,`
133			`we_n => data_w_n_ram(0),`
134			`data_i => data_write(7 downto 0),`
135			`data_o => data_read_ram(7 downto 0)`
136			`);`
137
138			`memory0ub: entity work.bram`
139			`generic map ( memory_file => memory_file,`
140			`data_width => 8,`
141			`address_width => address_width,`
142			`bank => 1)`
143			`port map(`
144			`clk => clock,`
145			`addr => address(address_width -1 downto 2),`
146			`cs_n => ram_enable_n,`
147			`we_n => data_w_n_ram(1),`
148			`data_i => data_write(15 downto 8),`
149			`data_o => data_read_ram(15 downto 8)`
150			`);`
151
152			`memory1lb: entity work.bram`
153			`generic map ( memory_file => memory_file,`
154			`data_width => 8,`
155			`address_width => address_width,`
156			`bank => 2)`
157			`port map(`
158			`clk => clock,`
159			`addr => address(address_width -1 downto 2),`
160			`cs_n => ram_enable_n,`
161			`we_n => data_w_n_ram(2),`
162			`data_i => data_write(23 downto 16),`
163			`data_o => data_read_ram(23 downto 16)`
164			`);`
165
166			`memory1ub: entity work.bram`
167			`generic map ( memory_file => memory_file,`
168			`data_width => 8,`
169			`address_width => address_width,`
170			`bank => 3)`
171			`port map(`
172			`clk => clock,`
173			`addr => address(address_width -1 downto 2),`
174			`cs_n => ram_enable_n,`
175			`we_n => data_w_n_ram(3),`
176			`data_i => data_write(31 downto 24),`
177			`data_o => data_read_ram(31 downto 24)`
178			`);`
179
180	18	serginhofr	`end top_level;`
181	13	serginhofr

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Subversion Repositories hf-risc

[/] [hf-risc/] [trunk/] [hf-risc/] [platform/] [virtex4_ml403/] [virtex4ml403.vhd] - Blame information for rev 18