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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
entity datapath is
        port (  clock:          in std_logic;
                reset:          in std_logic;
 
                stall:          in std_logic;
 
                irq_vector:     in std_logic_vector(31 downto 0);
                irq:            in std_logic;
                irq_ack:        out std_logic;
 
                address:        out std_logic_vector(31 downto 0);
                data_in:        in std_logic_vector(31 downto 0);
                data_out:       out std_logic_vector(31 downto 0);
                data_w:         out std_logic_vector(3 downto 0);
                data_access:    out std_logic
        );
end datapath;
 
architecture arch_datapath of datapath is
-- datapath signals
        signal data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);
        signal opcode, funct: std_logic_vector(5 downto 0);
        signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0);
        signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
        signal imm: std_logic_vector(15 downto 0);
        signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, mwait, stall_reg: std_logic;
        signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
 
-- control signals
        signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
        signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
        signal branch_ctl: std_logic_vector(2 downto 0);
        signal alu_op_ctl: std_logic_vector(3 downto 0);
 
 
        signal reg_dst_ctl_r, reg_write_ctl_r, alu_src_ctl_r, reg_to_mem_ctl_r, mem_to_reg_ctl_r, signed_imm_ctl_r, signed_rd_ctl_r, shift_ctl_r, br_link_ctl_r: std_logic;
        signal jump_ctl_r, mem_read_ctl_r, mem_write_ctl_r: std_logic_vector(1 downto 0);
        signal branch_ctl_r: std_logic_vector(2 downto 0);
        signal alu_op_ctl_r: std_logic_vector(3 downto 0);
        signal rs_r, rt_r, rd_r: std_logic_vector(4 downto 0);
        signal imm_r: std_logic_vector(15 downto 0);
begin
 
--
-- FETCH STAGE
--
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
 
        -- program counter logic
        process(clock, reset, reg_to_mem_ctl_r, mem_to_reg_ctl_r, mwait, stall)
        begin
                if reset = '1' then
                        pc <= (others => '0');
                        pc_last <= (others => '0');
                elsif clock'event and clock = '1' then
                        if stall = '0' then
                                if mwait = '0' then
                                        pc <= pc_next;
                                        pc_last <= pc;
                                else
                                        if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and bds = '0' then
                                                pc <= pc_last;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        pc_plus4 <=     pc + 4;
 
        pc_next <=      irq_vector when irq = '1' and irq_ack_s = '1' else
                        branch when branch_taken = '1' else
                        jump when jump_taken = '1' else
                        pc_plus4;
 
        -- interrupt acknowledge logic
        irq_ack_s <= '1' when irq = '1' and
                bds = '0' and branch_taken = '0' and jump_taken = '0' and
                reg_to_mem_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';
 
        irq_ack <= irq_ack_s_dly;
 
        process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, mwait, stall)
        begin
                if reset = '1' then
                        irq_ack_s_dly <= '0';
                        bds <= '0';
                        mem_to_reg_ctl_dly <= '0';
                        stall_reg <= '0';
                        data_access_s_dly <= '0';
                elsif clock'event and clock = '1' then
                        stall_reg <= stall;
                        if stall = '0' then
                                mem_to_reg_ctl_dly <= mem_to_reg_ctl_r;
                                data_access_s_dly <= data_access_s;
                                if mwait = '0' then
                                        irq_ack_s_dly <= irq_ack_s;
                                        if branch_taken = '1' or jump_taken = '1' then
                                                bds <= '1';
                                        else
                                                bds <= '0';
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
--
-- DECODE STAGE
--
-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and 2nd branch delay slot
 
        -- instruction decode
        opcode <= data_in(31 downto 26);
        rs <= data_in(25 downto 21);
        rt <= data_in(20 downto 16);
        rd <= "11111" when br_link_ctl = '1' else data_in(15 downto 11);                                        -- FIXME: this will not work for the 'jalr rd, rs' format
        funct <= data_in(5 downto 0);
        imm <= data_in(15 downto 0);
 
        -- control unit
        control_unit: entity work.control
        port map(       opcode => opcode,
                        funct => funct,
                        rtx => rt,
                        reg_dst => reg_dst_ctl,
                        reg_write => reg_write_ctl,
                        alu_src => alu_src_ctl,
                        alu_op => alu_op_ctl,
                        jump => jump_ctl,
                        branch => branch_ctl,
                        br_link => br_link_ctl,
                        reg_to_mem => reg_to_mem_ctl,
                        mem_to_reg => mem_to_reg_ctl,
                        signed_imm => signed_imm_ctl,
                        mem_write => mem_write_ctl,
                        mem_read => mem_read_ctl,
                        signed_rd => signed_rd_ctl,
                        shift => shift_ctl
        );
 
        process(clock, reset, mwait, stall)
        begin
                if reset = '1' then
                        rs_r <= (others => '0');
                        rt_r <= (others => '0');
                        rd_r <= (others => '0');
                        imm_r <= (others => '0');
                        reg_dst_ctl_r <= '0';
                        reg_write_ctl_r <= '0';
                        alu_src_ctl_r <= '0';
                        alu_op_ctl_r <= (others => '0');
                        jump_ctl_r <= (others => '0');
                        branch_ctl_r <= (others => '0');
                        br_link_ctl_r <= '0';
                        reg_to_mem_ctl_r <= '0';
                        mem_to_reg_ctl_r <= '0';
                        signed_imm_ctl_r <= '0';
                        mem_write_ctl_r <= "00";
                        mem_read_ctl_r <= "00";
                        signed_rd_ctl_r <= '0';
                        shift_ctl_r <= '0';
                elsif clock'event and clock = '1' then
                        if stall = '0' then
                                if irq_ack_s = '1' then
                                        rs_r <= (others => '0');
                                        rt_r <= (others => '0');
                                        rd_r <= (others => '0');
                                        imm_r <= (others => '0');
                                        reg_dst_ctl_r <= '0';
                                        reg_write_ctl_r <= '0';
                                        alu_src_ctl_r <= '0';
                                        alu_op_ctl_r <= (others => '0');
                                        jump_ctl_r <= (others => '0');
                                        branch_ctl_r <= (others => '0');
                                        br_link_ctl_r <= '0';
                                        reg_to_mem_ctl_r <= '0';
                                        mem_to_reg_ctl_r <= '0';
                                        signed_imm_ctl_r <= '0';
                                        mem_write_ctl_r <= "00";
                                        mem_read_ctl_r <= "00";
                                        signed_rd_ctl_r <= '0';
                                        shift_ctl_r <= '0';
                                else
                                        if mwait = '0' then
                                                if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or bds = '1' then
                                                        rs_r <= (others => '0');
                                                        rt_r <= (others => '0');
                                                        rd_r <= (others => '0');
                                                        imm_r <= (others => '0');
                                                        reg_dst_ctl_r <= '0';
                                                        reg_write_ctl_r <= '0';
                                                        alu_src_ctl_r <= '0';
                                                        alu_op_ctl_r <= (others => '0');
                                                        jump_ctl_r <= (others => '0');
                                                        branch_ctl_r <= (others => '0');
                                                        br_link_ctl_r <= '0';
                                                        reg_to_mem_ctl_r <= '0';
                                                        mem_to_reg_ctl_r <= '0';
                                                        signed_imm_ctl_r <= '0';
                                                        mem_write_ctl_r <= "00";
                                                        mem_read_ctl_r <= "00";
                                                        signed_rd_ctl_r <= '0';
                                                        shift_ctl_r <= '0';
                                                else
                                                        rs_r <= rs;
                                                        rt_r <= rt;
                                                        rd_r <= rd;
                                                        imm_r <= imm;
                                                        reg_dst_ctl_r <= reg_dst_ctl;
                                                        reg_write_ctl_r <= reg_write_ctl;
                                                        alu_src_ctl_r <= alu_src_ctl;
                                                        alu_op_ctl_r <= alu_op_ctl;
                                                        jump_ctl_r <= jump_ctl;
                                                        branch_ctl_r <= branch_ctl;
                                                        br_link_ctl_r <= br_link_ctl;
                                                        reg_to_mem_ctl_r <= reg_to_mem_ctl;
                                                        mem_to_reg_ctl_r <= mem_to_reg_ctl;
                                                        signed_imm_ctl_r <= signed_imm_ctl;
                                                        mem_write_ctl_r <= mem_write_ctl;
                                                        mem_read_ctl_r <= mem_read_ctl;
                                                        signed_rd_ctl_r <= signed_rd_ctl;
                                                        shift_ctl_r <= shift_ctl;
                                                end if;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
--
-- EXECUTE STAGE
--
 
-- 3rd stage (a) register file access (read)
        -- the register file
        register_bank: entity work.reg_bank
        port map(       clock => clock,
                        read_reg1 => read_reg1,
                        read_reg2 => read_reg2,
                        write_reg => write_reg,
                        wreg => wreg,
                        write_data => write_data,
                        read_data1 => read_data1,
                        read_data2 => read_data2
        );
 
        -- register file read/write selection and write enable
        read_reg1 <= rs_r when shift_ctl_r = '0' else rt_r;                                              -- source for shifts or normal operations
        read_reg2 <= "00000" when branch_ctl_r > "010" else                                             -- source for branch and link (for zero operations)
                        rs_r when shift_ctl_r = '1' else rt_r;                                          -- source for register based shifts or normal operations
        write_reg <= target when mem_to_reg_ctl_r = '0' else rt_r;
        ext32 <= x"0000" & imm_r when (imm_r(15) = '0' or signed_imm_ctl_r = '0') else x"ffff" & imm_r;
        target <= rt_r when reg_dst_ctl_r = '0' else rd_r;                                               -- target register selection
        wreg <= (reg_write_ctl_r or mem_to_reg_ctl_dly) and not mwait and not stall_reg;                        -- enable the register bank for write back also
 
-- 3rd stage (b) ALU operation
        alu: entity work.alu
        port map(       op1 => read_data1,
                        op2 => alu_src,
                        alu_op => alu_op_ctl_r,
                        result => result,
                        zero => zero,
                        less_than => less_than
        );
 
        alu_src <= read_data2 when alu_src_ctl_r = '0' else ext32;
 
        branch <= (ext32(29 downto 0) & "00") + pc_last;
        jump <= read_data1 when jump_ctl_r = "10" else pc_last(31 downto 28) & rs_r & rt_r & imm_r & "00";
 
        branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or                                               -- BEQ
                                (zero = '0' and branch_ctl_r = "010") or                                         -- BNE
                                ((zero = '1' or less_than = '1') and branch_ctl_r = "011") or                           -- BLEZ
                                ((zero = '0' and less_than = '0') and branch_ctl_r = "100") or                            -- BGTZ
                                ((zero = '0' and less_than = '1') and branch_ctl_r = "101") or                           -- BLTZ, BLTZAL
                                ((zero = '1' or less_than = '0') and branch_ctl_r = "110")                               -- BGEZ, BGEZAL
                                else '0';
        jump_taken <= '1' when jump_ctl_r /= "00" else '0';                                                              -- J, JAL, JR, JALR
 
        address <= result when data_access_s = '1' and mwait = '1' else pc;
        data_access_s <= '1' when reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';
        mwait <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
        data_access <= mwait;
 
 
-- 3rd stage (c) data memory / write back operation, register file access (write)
        -- memory access, store operations
        process(mem_write_ctl_r, result, read_data2)
        begin
                case mem_write_ctl_r is
                        when "11" =>                    -- store word
                                data_out <= read_data2;
                                data_w <= "1111";
                        when "01" =>                    -- store byte
                                data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
                                case result(1 downto 0) is
                                        when "11" => data_w <= "0001";
                                        when "10" => data_w <= "0010";
                                        when "01" => data_w <= "0100";
                                        when others => data_w <= "1000";
                                end case;
                        when "10" =>                    -- store half word
                                data_out <= read_data2(15 downto 0) & read_data2(15 downto 0);
                                case result(1) is
                                        when '1' => data_w <= "0011";
                                        when others => data_w <= "1100";
                                end case;
                        when others =>                  -- WTF??
                                data_out <= read_data2;
                                data_w <= "0000";
                end case;
        end process;
 
        -- memory access, load operations
        process(mem_read_ctl_r, result, data_in)
        begin
                case mem_read_ctl_r is
                        when "01" =>                    -- load byte
                                case result(1 downto 0) is
                                        when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
                                        when "10" => data_in_s <= x"000000" & data_in(15 downto 8);
                                        when "01" => data_in_s <= x"000000" & data_in(23 downto 16);
                                        when others => data_in_s <= x"000000" & data_in(31 downto 24);
 
                                end case;
                        when "10" =>                    -- load half word
                                case result(1) is
                                        when '1' => data_in_s <= x"0000" & data_in(15 downto 0);
                                        when others => data_in_s <= x"0000" & data_in(31 downto 16);
                                end case;
                        when others =>                  -- load word
                                data_in_s <= data_in;
                end case;
        end process;
 
        -- write back
        ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or signed_rd_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
        ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or signed_rd_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
 
        write_data <= data_in_s when mem_read_ctl_r = "11" else
                        ext32b when mem_read_ctl_r = "01" else
                        ext32h when mem_read_ctl_r = "10" else
                        pc when br_link_ctl_r = '1' else result;
 
end arch_datapath;
 

Line No.	Rev	Author	Line
1	13	serginhofr	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_unsigned.all;`
4			`use ieee.std_logic_arith.all;`
5
6			`entity datapath is`
7			`port ( clock: in std_logic;`
8			`reset: in std_logic;`
9
10			`stall: in std_logic;`
11
12			`irq_vector: in std_logic_vector(31 downto 0);`
13			`irq: in std_logic;`
14			`irq_ack: out std_logic;`
15
16	18	serginhofr	`address: out std_logic_vector(31 downto 0);`
17	13	serginhofr	`data_in: in std_logic_vector(31 downto 0);`
18			`data_out: out std_logic_vector(31 downto 0);`
19			`data_w: out std_logic_vector(3 downto 0);`
20			`data_access: out std_logic`
21			`);`
22			`end datapath;`
23
24			`architecture arch_datapath of datapath is`
25			`-- datapath signals`
26			`signal data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);`
27			`signal opcode, funct: std_logic_vector(5 downto 0);`
28			`signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0);`
29			`signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);`
30			`signal imm: std_logic_vector(15 downto 0);`
31	18	serginhofr	`signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, mwait, stall_reg: std_logic;`
32			`signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;`
33	13	serginhofr
34			`-- control signals`
35			`signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;`
36			`signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);`
37			`signal branch_ctl: std_logic_vector(2 downto 0);`
38			`signal alu_op_ctl: std_logic_vector(3 downto 0);`
39
40
41			`signal reg_dst_ctl_r, reg_write_ctl_r, alu_src_ctl_r, reg_to_mem_ctl_r, mem_to_reg_ctl_r, signed_imm_ctl_r, signed_rd_ctl_r, shift_ctl_r, br_link_ctl_r: std_logic;`
42			`signal jump_ctl_r, mem_read_ctl_r, mem_write_ctl_r: std_logic_vector(1 downto 0);`
43			`signal branch_ctl_r: std_logic_vector(2 downto 0);`
44			`signal alu_op_ctl_r: std_logic_vector(3 downto 0);`
45			`signal rs_r, rt_r, rd_r: std_logic_vector(4 downto 0);`
46			`signal imm_r: std_logic_vector(15 downto 0);`
47			`begin`
48
49			`--`
50			`-- FETCH STAGE`
51			`--`
52			`-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic`
53
54			`-- program counter logic`
55	18	serginhofr	`process(clock, reset, reg_to_mem_ctl_r, mem_to_reg_ctl_r, mwait, stall)`
56	13	serginhofr	`begin`
57			`if reset = '1' then`
58			`pc <= (others => '0');`
59			`pc_last <= (others => '0');`
60			`elsif clock'event and clock = '1' then`
61			`if stall = '0' then`
62	18	serginhofr	`if mwait = '0' then`
63	13	serginhofr	`pc <= pc_next;`
64			`pc_last <= pc;`
65			`else`
66	17	serginhofr	`if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and bds = '0' then`
67	13	serginhofr	`pc <= pc_last;`
68			`end if;`
69			`end if;`
70			`end if;`
71			`end if;`
72			`end process;`
73
74			`pc_plus4 <= pc + 4;`
75
76			`pc_next <= irq_vector when irq = '1' and irq_ack_s = '1' else`
77			`branch when branch_taken = '1' else`
78			`jump when jump_taken = '1' else`
79			`pc_plus4;`
80
81			`-- interrupt acknowledge logic`
82			`irq_ack_s <= '1' when irq = '1' and`
83			`bds = '0' and branch_taken = '0' and jump_taken = '0' and`
84			`reg_to_mem_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';`
85
86			`irq_ack <= irq_ack_s_dly;`
87
88	18	serginhofr	`process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, mwait, stall)`
89	13	serginhofr	`begin`
90			`if reset = '1' then`
91			`irq_ack_s_dly <= '0';`
92			`bds <= '0';`
93			`mem_to_reg_ctl_dly <= '0';`
94			`stall_reg <= '0';`
95	18	serginhofr	`data_access_s_dly <= '0';`
96	13	serginhofr	`elsif clock'event and clock = '1' then`
97			`stall_reg <= stall;`
98			`if stall = '0' then`
99			`mem_to_reg_ctl_dly <= mem_to_reg_ctl_r;`
100	18	serginhofr	`data_access_s_dly <= data_access_s;`
101			`if mwait = '0' then`
102	13	serginhofr	`irq_ack_s_dly <= irq_ack_s;`
103			`if branch_taken = '1' or jump_taken = '1' then`
104			`bds <= '1';`
105			`else`
106			`bds <= '0';`
107			`end if;`
108			`end if;`
109			`end if;`
110			`end if;`
111			`end process;`
112
113			`--`
114			`-- DECODE STAGE`
115			`--`
116			`-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and 2nd branch delay slot`
117
118			`-- instruction decode`
119	18	serginhofr	`opcode <= data_in(31 downto 26);`
120			`rs <= data_in(25 downto 21);`
121			`rt <= data_in(20 downto 16);`
122			`rd <= "11111" when br_link_ctl = '1' else data_in(15 downto 11); -- FIXME: this will not work for the 'jalr rd, rs' format`
123			`funct <= data_in(5 downto 0);`
124			`imm <= data_in(15 downto 0);`
125	13	serginhofr
126			`-- control unit`
127	18	serginhofr	`control_unit: entity work.control`
128	13	serginhofr	`port map( opcode => opcode,`
129			`funct => funct,`
130			`rtx => rt,`
131			`reg_dst => reg_dst_ctl,`
132			`reg_write => reg_write_ctl,`
133			`alu_src => alu_src_ctl,`
134			`alu_op => alu_op_ctl,`
135			`jump => jump_ctl,`
136			`branch => branch_ctl,`
137			`br_link => br_link_ctl,`
138			`reg_to_mem => reg_to_mem_ctl,`
139			`mem_to_reg => mem_to_reg_ctl,`
140			`signed_imm => signed_imm_ctl,`
141			`mem_write => mem_write_ctl,`
142			`mem_read => mem_read_ctl,`
143			`signed_rd => signed_rd_ctl,`
144			`shift => shift_ctl`
145			`);`
146
147	18	serginhofr	`process(clock, reset, mwait, stall)`
148	13	serginhofr	`begin`
149			`if reset = '1' then`
150			`rs_r <= (others => '0');`
151			`rt_r <= (others => '0');`
152			`rd_r <= (others => '0');`
153			`imm_r <= (others => '0');`
154			`reg_dst_ctl_r <= '0';`
155			`reg_write_ctl_r <= '0';`
156			`alu_src_ctl_r <= '0';`
157			`alu_op_ctl_r <= (others => '0');`
158			`jump_ctl_r <= (others => '0');`
159			`branch_ctl_r <= (others => '0');`
160			`br_link_ctl_r <= '0';`
161			`reg_to_mem_ctl_r <= '0';`
162			`mem_to_reg_ctl_r <= '0';`
163			`signed_imm_ctl_r <= '0';`
164			`mem_write_ctl_r <= "00";`
165			`mem_read_ctl_r <= "00";`
166			`signed_rd_ctl_r <= '0';`
167			`shift_ctl_r <= '0';`
168			`elsif clock'event and clock = '1' then`
169			`if stall = '0' then`
170			`if irq_ack_s = '1' then`
171			`rs_r <= (others => '0');`
172			`rt_r <= (others => '0');`
173			`rd_r <= (others => '0');`
174			`imm_r <= (others => '0');`
175			`reg_dst_ctl_r <= '0';`
176			`reg_write_ctl_r <= '0';`
177			`alu_src_ctl_r <= '0';`
178			`alu_op_ctl_r <= (others => '0');`
179			`jump_ctl_r <= (others => '0');`
180			`branch_ctl_r <= (others => '0');`
181			`br_link_ctl_r <= '0';`
182			`reg_to_mem_ctl_r <= '0';`
183			`mem_to_reg_ctl_r <= '0';`
184			`signed_imm_ctl_r <= '0';`
185			`mem_write_ctl_r <= "00";`
186			`mem_read_ctl_r <= "00";`
187			`signed_rd_ctl_r <= '0';`
188			`shift_ctl_r <= '0';`
189			`else`
190	18	serginhofr	`if mwait = '0' then`
191	17	serginhofr	`if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or bds = '1' then`
192	13	serginhofr	`rs_r <= (others => '0');`
193			`rt_r <= (others => '0');`
194			`rd_r <= (others => '0');`
195			`imm_r <= (others => '0');`
196			`reg_dst_ctl_r <= '0';`
197			`reg_write_ctl_r <= '0';`
198			`alu_src_ctl_r <= '0';`
199			`alu_op_ctl_r <= (others => '0');`
200			`jump_ctl_r <= (others => '0');`
201			`branch_ctl_r <= (others => '0');`
202			`br_link_ctl_r <= '0';`
203			`reg_to_mem_ctl_r <= '0';`
204			`mem_to_reg_ctl_r <= '0';`
205			`signed_imm_ctl_r <= '0';`
206			`mem_write_ctl_r <= "00";`
207			`mem_read_ctl_r <= "00";`
208			`signed_rd_ctl_r <= '0';`
209			`shift_ctl_r <= '0';`
210			`else`
211			`rs_r <= rs;`
212			`rt_r <= rt;`
213			`rd_r <= rd;`
214			`imm_r <= imm;`
215			`reg_dst_ctl_r <= reg_dst_ctl;`
216			`reg_write_ctl_r <= reg_write_ctl;`
217			`alu_src_ctl_r <= alu_src_ctl;`
218			`alu_op_ctl_r <= alu_op_ctl;`
219			`jump_ctl_r <= jump_ctl;`
220			`branch_ctl_r <= branch_ctl;`
221			`br_link_ctl_r <= br_link_ctl;`
222			`reg_to_mem_ctl_r <= reg_to_mem_ctl;`
223			`mem_to_reg_ctl_r <= mem_to_reg_ctl;`
224			`signed_imm_ctl_r <= signed_imm_ctl;`
225			`mem_write_ctl_r <= mem_write_ctl;`
226			`mem_read_ctl_r <= mem_read_ctl;`
227			`signed_rd_ctl_r <= signed_rd_ctl;`
228			`shift_ctl_r <= shift_ctl;`
229			`end if;`
230			`end if;`
231			`end if;`
232			`end if;`
233			`end if;`
234			`end process;`
235
236			`--`
237			`-- EXECUTE STAGE`
238			`--`
239
240			`-- 3rd stage (a) register file access (read)`
241			`-- the register file`
242			`register_bank: entity work.reg_bank`
243			`port map( clock => clock,`
244			`read_reg1 => read_reg1,`
245			`read_reg2 => read_reg2,`
246			`write_reg => write_reg,`
247			`wreg => wreg,`
248			`write_data => write_data,`
249			`read_data1 => read_data1,`
250			`read_data2 => read_data2`
251			`);`
252
253			`-- register file read/write selection and write enable`
254			`read_reg1 <= rs_r when shift_ctl_r = '0' else rt_r; -- source for shifts or normal operations`
255			`read_reg2 <= "00000" when branch_ctl_r > "010" else -- source for branch and link (for zero operations)`
256			`rs_r when shift_ctl_r = '1' else rt_r; -- source for register based shifts or normal operations`
257			`write_reg <= target when mem_to_reg_ctl_r = '0' else rt_r;`
258			`ext32 <= x"0000" & imm_r when (imm_r(15) = '0' or signed_imm_ctl_r = '0') else x"ffff" & imm_r;`
259			`target <= rt_r when reg_dst_ctl_r = '0' else rd_r; -- target register selection`
260	18	serginhofr	`wreg <= (reg_write_ctl_r or mem_to_reg_ctl_dly) and not mwait and not stall_reg; -- enable the register bank for write back also`
261	13	serginhofr
262			`-- 3rd stage (b) ALU operation`
263			`alu: entity work.alu`
264			`port map( op1 => read_data1,`
265			`op2 => alu_src,`
266			`alu_op => alu_op_ctl_r,`
267			`result => result,`
268			`zero => zero,`
269			`less_than => less_than`
270			`);`
271
272			`alu_src <= read_data2 when alu_src_ctl_r = '0' else ext32;`
273
274			`branch <= (ext32(29 downto 0) & "00") + pc_last;`
275			`jump <= read_data1 when jump_ctl_r = "10" else pc_last(31 downto 28) & rs_r & rt_r & imm_r & "00";`
276
277			`branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ`
278			`(zero = '0' and branch_ctl_r = "010") or -- BNE`
279			`((zero = '1' or less_than = '1') and branch_ctl_r = "011") or -- BLEZ`
280			`((zero = '0' and less_than = '0') and branch_ctl_r = "100") or -- BGTZ`
281			`((zero = '0' and less_than = '1') and branch_ctl_r = "101") or -- BLTZ, BLTZAL`
282			`((zero = '1' or less_than = '0') and branch_ctl_r = "110") -- BGEZ, BGEZAL`
283			`else '0';`
284			`jump_taken <= '1' when jump_ctl_r /= "00" else '0'; -- J, JAL, JR, JALR`
285
286	18	serginhofr	`address <= result when data_access_s = '1' and mwait = '1' else pc;`
287			`data_access_s <= '1' when reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';`
288			`mwait <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';`
289			`data_access <= mwait;`
290	13	serginhofr
291
292			`-- 3rd stage (c) data memory / write back operation, register file access (write)`
293			`-- memory access, store operations`
294			`process(mem_write_ctl_r, result, read_data2)`
295			`begin`
296			`case mem_write_ctl_r is`
297			`when "11" => -- store word`
298			`data_out <= read_data2;`
299			`data_w <= "1111";`
300			`when "01" => -- store byte`
301			`data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);`
302			`case result(1 downto 0) is`
303			`when "11" => data_w <= "0001";`
304			`when "10" => data_w <= "0010";`
305			`when "01" => data_w <= "0100";`
306			`when others => data_w <= "1000";`
307			`end case;`
308			`when "10" => -- store half word`
309			`data_out <= read_data2(15 downto 0) & read_data2(15 downto 0);`
310			`case result(1) is`
311			`when '1' => data_w <= "0011";`
312			`when others => data_w <= "1100";`
313			`end case;`
314			`when others => -- WTF??`
315			`data_out <= read_data2;`
316			`data_w <= "0000";`
317			`end case;`
318			`end process;`
319
320			`-- memory access, load operations`
321			`process(mem_read_ctl_r, result, data_in)`
322			`begin`
323			`case mem_read_ctl_r is`
324			`when "01" => -- load byte`
325			`case result(1 downto 0) is`
326			`when "11" => data_in_s <= x"000000" & data_in(7 downto 0);`
327			`when "10" => data_in_s <= x"000000" & data_in(15 downto 8);`
328			`when "01" => data_in_s <= x"000000" & data_in(23 downto 16);`
329			`when others => data_in_s <= x"000000" & data_in(31 downto 24);`
330
331			`end case;`
332			`when "10" => -- load half word`
333			`case result(1) is`
334			`when '1' => data_in_s <= x"0000" & data_in(15 downto 0);`
335			`when others => data_in_s <= x"0000" & data_in(31 downto 16);`
336			`end case;`
337			`when others => -- load word`
338			`data_in_s <= data_in;`
339			`end case;`
340			`end process;`
341
342			`-- write back`
343			`ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or signed_rd_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);`
344			`ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or signed_rd_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);`
345
346			`write_data <= data_in_s when mem_read_ctl_r = "11" else`
347			`ext32b when mem_read_ctl_r = "01" else`
348			`ext32h when mem_read_ctl_r = "10" else`
349			`pc when br_link_ctl_r = '1' else result;`
350
351			`end arch_datapath;`
352

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