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[/] [hf-risc/] [trunk/] [hf-riscv/] [platform/] [virtex4_ml403/] [virtex4ml403.ucf] - Blame information for rev 18

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# Virtex4 ML403
 
# Clock and Reset
NET "clk_in" LOC="AE14";
NET "clk_in" IOSTANDARD = LVCMOS33;
NET "reset_in" LOC="D6";
NET "reset_in" PULLUP;
 
# System level constraints
NET "clk_in" TNM_NET = "clk_in";
TIMESPEC TS_clk_in = PERIOD "clk_in" 10000 ps;
NET "reset_in" TIG;
 
# UART
NET "uart_read" LOC=W2;
NET "uart_read" IOSTANDARD = LVCMOS33;
NET "uart_write" LOC=W1;
NET "uart_write" IOSTANDARD = LVCMOS33;
 

Line No.	Rev	Author	Line
1	18	serginhofr	`# Virtex4 ML403`
2
3			`# Clock and Reset`
4			`NET "clk_in" LOC="AE14";`
5			`NET "clk_in" IOSTANDARD = LVCMOS33;`
6			`NET "reset_in" LOC="D6";`
7			`NET "reset_in" PULLUP;`
8
9			`# System level constraints`
10			`NET "clk_in" TNM_NET = "clk_in";`
11			`TIMESPEC TS_clk_in = PERIOD "clk_in" 10000 ps;`
12			`NET "reset_in" TIG;`
13
14			`# UART`
15			`NET "uart_read" LOC=W2;`
16			`NET "uart_read" IOSTANDARD = LVCMOS33;`
17			`NET "uart_write" LOC=W1;`
18			`NET "uart_write" IOSTANDARD = LVCMOS33;`
19

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[/] [hf-risc/] [trunk/] [hf-riscv/] [platform/] [virtex4_ml403/] [virtex4ml403.ucf] - Blame information for rev 18