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[/] [hight/] [trunk/] [rtl/] [CONTROL.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Control module for HIGHT Crypto Core                        ////
////                                                              ////
////  This file is part of the HIGHT Crypto Core project          ////
////  http://github.com/OpenSoCPlus/hight_crypto_core             ////
////  http://www.opencores.org/project,hight                      ////
////                                                              ////
////  Description                                                 ////
////  __description__                                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - JoonSoo Ha, json.ha@gmail.com                         ////
////      - Younjoo Kim, younjookim.kr@gmail.com                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG    ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module CONTROL(
        rstn           ,
        clk            ,
 
        i_mk_rdy       ,
        i_post_rdy     ,
        i_text_val     ,
 
        o_rdy          ,
        o_text_done    ,
 
        o_xf_sel       ,
        o_rf_final     ,
 
        o_key_sel      ,
        o_rnd_idx      ,
        o_wf_post_pre
);
 
 
//=====================================
//
//          PARAMETERS 
//
//=====================================
localparam  S_IDLE       = 6'b1_10000;
localparam  S_KEY_CONFIG = 6'b1_00000;
localparam  S_RDY        = 6'b0_00000;
localparam  S_WF1        = 6'b0_00001;
localparam  S_RF1        = 6'b0_00010;
localparam  S_RF2        = 6'b0_00011;
localparam  S_RF3        = 6'b0_00100;
localparam  S_RF4        = 6'b0_00101;
localparam  S_RF5        = 6'b0_00110;
localparam  S_RF6        = 6'b0_00111;
localparam  S_RF7        = 6'b0_01000;
localparam  S_RF8        = 6'b0_01001;
localparam  S_RF9        = 6'b0_01010;
localparam  S_RF10       = 6'b0_01011;
localparam  S_RF11       = 6'b0_01100;
localparam  S_RF12       = 6'b0_01101;
localparam  S_RF13       = 6'b0_01110;
localparam  S_RF14       = 6'b0_01111;
localparam  S_RF15       = 6'b0_10000;
localparam  S_RF16       = 6'b0_10001;
localparam  S_RF17       = 6'b0_10010;
localparam  S_RF18       = 6'b0_10011;
localparam  S_RF19       = 6'b0_10100;
localparam  S_RF20       = 6'b0_10101;
localparam  S_RF21       = 6'b0_10110;
localparam  S_RF22       = 6'b0_10111;
localparam  S_RF23       = 6'b0_11000;
localparam  S_RF24       = 6'b0_11001;
localparam  S_RF25       = 6'b0_11010;
localparam  S_RF26       = 6'b0_11011;
localparam  S_RF27       = 6'b0_11100;
localparam  S_RF28       = 6'b0_11101;
localparam  S_RF29       = 6'b0_11110;
localparam  S_RF30       = 6'b0_11111;
localparam  S_RF31       = 6'b1_11111;
localparam  S_RF32       = 6'b1_11110;
localparam  S_DONE       = 6'b1_11100;
localparam  S_ERROR      = 6'b1_01010;
 
 
//=====================================
//
//          I/O PORTS 
//
//=====================================
input        rstn           ;
input        clk            ;
 
input        i_mk_rdy       ;
input        i_post_rdy     ;
input        i_text_val     ;
 
output       o_rdy          ;
output       o_text_done    ;
 
output[2:0]  o_xf_sel       ;
output       o_rf_final     ;
 
output       o_key_sel      ;
output[4:0]  o_rnd_idx      ;
output       o_wf_post_pre  ;
 
 
//=====================================
//
//          REGISTERS
//
//=====================================
// state register
reg[5:0]    r_pstate        ;
 
 
//=====================================
//
//          WIRES
//
//=====================================
// nstate
reg[5:0]    w_nstate        ;
 
 
//=====================================
//
//          MAIN
//
//=====================================
// state register
always @(negedge rstn or posedge clk)
        if(~rstn)
                r_pstate <= #1 S_IDLE  ;
        else
                r_pstate <= #1 w_nstate;
 
 
// nstate
always @(i_mk_rdy or i_text_val or i_post_rdy or r_pstate)
        case(r_pstate)
        S_IDLE       :
                       begin
                           if(i_mk_rdy)
                               w_nstate <= S_RDY;
                           else
                               w_nstate <= S_KEY_CONFIG;
                       end
        S_KEY_CONFIG :
                       begin
                           if(i_mk_rdy)
                               w_nstate <= S_RDY;
                           else
                               w_nstate <= r_pstate;
                       end
        S_RDY        :
                       begin
                           if(i_text_val)
                               if(i_mk_rdy)
                                   w_nstate <= S_WF1;
                               else // ~i_mk_rdy
                                   w_nstate <= S_ERROR;
                           else // ~i_text_val
                               if(i_mk_rdy)
                                   w_nstate <= r_pstate;
                               else // ~i_mk_rdy
                                   w_nstate <= S_KEY_CONFIG;
                       end
        S_WF1        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF1;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF1        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF2;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF2        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF3;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF3        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF4;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF4        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF5;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF5        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF6;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF6        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF7;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF7        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF8;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF8        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF9;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF9        :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF10;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF10       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF11;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF11       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF12;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF12       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF13;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF13       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF14;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF14       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF15;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF15       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF16;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF16       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF17;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF17       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF18;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF18       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF19;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF19       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF20;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF20       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF21;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF21       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF22;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF22       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF23;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF23       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF24;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF24       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF25;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF25       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF26;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF26       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF27;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF27       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF28;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF28       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF29;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF29       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF30;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF30       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF31;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF31       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_RF32;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_RF32       :
                       begin
                           if(i_mk_rdy)
                               w_nstate     <= S_DONE;
                           else
                               w_nstate     <= S_ERROR;
                       end
        S_DONE       :
                       begin
                           if(i_post_rdy)
                               if(i_mk_rdy)
                                   w_nstate <= S_RDY;
                               else
                                   w_nstate <= S_KEY_CONFIG;
                           else
                               w_nstate <= r_pstate;
                       end
        S_ERROR      :
                       begin
                           w_nstate <= S_IDLE;
                       end
        default      :
                       begin
                           w_nstate <= S_ERROR;
                       end
        endcase
 
 
// o_rdy
assign      o_rdy         = i_mk_rdy & (r_pstate == S_RDY);
 
// o_text_done
assign      o_text_done   = (r_pstate == S_DONE) & i_post_rdy;
 
// o_xf_sel
assign      o_xf_sel[2]   = (r_pstate == S_RDY) & i_text_val;
assign      o_xf_sel[1:0] = ((r_pstate == S_RDY) & i_text_val)                            ? 2'b01 :
                            (((r_pstate != S_RDY) & ~r_pstate[5]) | (r_pstate == S_RF31)) ? 2'b10 :
                                                                    (r_pstate == S_RF32)  ? 2'b01 :
                                                                                            2'b00 ;
// o_rf_final
assign      o_rf_final    = (r_pstate == S_RF31);
 
// o_key_sel
assign      o_key_sel     = ((r_pstate == S_RDY) & i_text_val) | ((r_pstate != S_RDY) & (~r_pstate[5]));
 
// o_rnd_idx
assign      o_rnd_idx     = r_pstate[4:0];
 
// o_wf_post_pre
assign      o_wf_post_pre = (r_pstate == S_RF31);
 
endmodule
 
 
 
 

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[/] [hight/] [trunk/] [rtl/] [CONTROL.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	truemind	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Control module for HIGHT Crypto Core ////`
4			`//// ////`
5			`//// This file is part of the HIGHT Crypto Core project ////`
6			`//// http://github.com/OpenSoCPlus/hight_crypto_core ////`
7			`//// http://www.opencores.org/project,hight ////`
8			`//// ////`
9			`//// Description ////`
10			`//// __description__ ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - JoonSoo Ha, json.ha@gmail.com ////`
14			`//// - Younjoo Kim, younjookim.kr@gmail.com ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43			`module CONTROL(`
44			`rstn ,`
45			`clk ,`
46
47			`i_mk_rdy ,`
48			`i_post_rdy ,`
49			`i_text_val ,`
50
51			`o_rdy ,`
52			`o_text_done ,`
53
54			`o_xf_sel ,`
55			`o_rf_final ,`
56
57			`o_key_sel ,`
58			`o_rnd_idx ,`
59			`o_wf_post_pre`
60			`);`
61
62
63			`//=====================================`
64			`//`
65			`// PARAMETERS`
66			`//`
67			`//=====================================`
68			`localparam S_IDLE = 6'b1_10000;`
69			`localparam S_KEY_CONFIG = 6'b1_00000;`
70			`localparam S_RDY = 6'b0_00000;`
71			`localparam S_WF1 = 6'b0_00001;`
72			`localparam S_RF1 = 6'b0_00010;`
73			`localparam S_RF2 = 6'b0_00011;`
74			`localparam S_RF3 = 6'b0_00100;`
75			`localparam S_RF4 = 6'b0_00101;`
76			`localparam S_RF5 = 6'b0_00110;`
77			`localparam S_RF6 = 6'b0_00111;`
78			`localparam S_RF7 = 6'b0_01000;`
79			`localparam S_RF8 = 6'b0_01001;`
80			`localparam S_RF9 = 6'b0_01010;`
81			`localparam S_RF10 = 6'b0_01011;`
82			`localparam S_RF11 = 6'b0_01100;`
83			`localparam S_RF12 = 6'b0_01101;`
84			`localparam S_RF13 = 6'b0_01110;`
85			`localparam S_RF14 = 6'b0_01111;`
86			`localparam S_RF15 = 6'b0_10000;`
87			`localparam S_RF16 = 6'b0_10001;`
88			`localparam S_RF17 = 6'b0_10010;`
89			`localparam S_RF18 = 6'b0_10011;`
90			`localparam S_RF19 = 6'b0_10100;`
91			`localparam S_RF20 = 6'b0_10101;`
92			`localparam S_RF21 = 6'b0_10110;`
93			`localparam S_RF22 = 6'b0_10111;`
94			`localparam S_RF23 = 6'b0_11000;`
95			`localparam S_RF24 = 6'b0_11001;`
96			`localparam S_RF25 = 6'b0_11010;`
97			`localparam S_RF26 = 6'b0_11011;`
98			`localparam S_RF27 = 6'b0_11100;`
99			`localparam S_RF28 = 6'b0_11101;`
100			`localparam S_RF29 = 6'b0_11110;`
101			`localparam S_RF30 = 6'b0_11111;`
102			`localparam S_RF31 = 6'b1_11111;`
103			`localparam S_RF32 = 6'b1_11110;`
104			`localparam S_DONE = 6'b1_11100;`
105			`localparam S_ERROR = 6'b1_01010;`
106
107
108			`//=====================================`
109			`//`
110			`// I/O PORTS`
111			`//`
112			`//=====================================`
113			`input rstn ;`
114			`input clk ;`
115
116			`input i_mk_rdy ;`
117			`input i_post_rdy ;`
118			`input i_text_val ;`
119
120			`output o_rdy ;`
121			`output o_text_done ;`
122
123			`output[2:0] o_xf_sel ;`
124			`output o_rf_final ;`
125
126			`output o_key_sel ;`
127			`output[4:0] o_rnd_idx ;`
128			`output o_wf_post_pre ;`
129
130
131			`//=====================================`
132			`//`
133			`// REGISTERS`
134			`//`
135			`//=====================================`
136			`// state register`
137			`reg[5:0] r_pstate ;`
138
139
140			`//=====================================`
141			`//`
142			`// WIRES`
143			`//`
144			`//=====================================`
145			`// nstate`
146			`reg[5:0] w_nstate ;`
147
148
149			`//=====================================`
150			`//`
151			`// MAIN`
152			`//`
153			`//=====================================`
154			`// state register`
155			`always @(negedge rstn or posedge clk)`
156			`if(~rstn)`
157			`r_pstate <= #1 S_IDLE ;`
158			`else`
159			`r_pstate <= #1 w_nstate;`
160
161
162			`// nstate`
163			`always @(i_mk_rdy or i_text_val or i_post_rdy or r_pstate)`
164			`case(r_pstate)`
165			`S_IDLE :`
166			`begin`
167			`if(i_mk_rdy)`
168			`w_nstate <= S_RDY;`
169			`else`
170			`w_nstate <= S_KEY_CONFIG;`
171			`end`
172			`S_KEY_CONFIG :`
173			`begin`
174			`if(i_mk_rdy)`
175			`w_nstate <= S_RDY;`
176			`else`
177			`w_nstate <= r_pstate;`
178			`end`
179			`S_RDY :`
180			`begin`
181			`if(i_text_val)`
182			`if(i_mk_rdy)`
183			`w_nstate <= S_WF1;`
184			`else // ~i_mk_rdy`
185			`w_nstate <= S_ERROR;`
186			`else // ~i_text_val`
187			`if(i_mk_rdy)`
188			`w_nstate <= r_pstate;`
189			`else // ~i_mk_rdy`
190			`w_nstate <= S_KEY_CONFIG;`
191			`end`
192			`S_WF1 :`
193			`begin`
194			`if(i_mk_rdy)`
195			`w_nstate <= S_RF1;`
196			`else`
197			`w_nstate <= S_ERROR;`
198			`end`
199			`S_RF1 :`
200			`begin`
201			`if(i_mk_rdy)`
202			`w_nstate <= S_RF2;`
203			`else`
204			`w_nstate <= S_ERROR;`
205			`end`
206			`S_RF2 :`
207			`begin`
208			`if(i_mk_rdy)`
209			`w_nstate <= S_RF3;`
210			`else`
211			`w_nstate <= S_ERROR;`
212			`end`
213			`S_RF3 :`
214			`begin`
215			`if(i_mk_rdy)`
216			`w_nstate <= S_RF4;`
217			`else`
218			`w_nstate <= S_ERROR;`
219			`end`
220			`S_RF4 :`
221			`begin`
222			`if(i_mk_rdy)`
223			`w_nstate <= S_RF5;`
224			`else`
225			`w_nstate <= S_ERROR;`
226			`end`
227			`S_RF5 :`
228			`begin`
229			`if(i_mk_rdy)`
230			`w_nstate <= S_RF6;`
231			`else`
232			`w_nstate <= S_ERROR;`
233			`end`
234			`S_RF6 :`
235			`begin`
236			`if(i_mk_rdy)`
237			`w_nstate <= S_RF7;`
238			`else`
239			`w_nstate <= S_ERROR;`
240			`end`
241			`S_RF7 :`
242			`begin`
243			`if(i_mk_rdy)`
244			`w_nstate <= S_RF8;`
245			`else`
246			`w_nstate <= S_ERROR;`
247			`end`
248			`S_RF8 :`
249			`begin`
250			`if(i_mk_rdy)`
251			`w_nstate <= S_RF9;`
252			`else`
253			`w_nstate <= S_ERROR;`
254			`end`
255			`S_RF9 :`
256			`begin`
257			`if(i_mk_rdy)`
258			`w_nstate <= S_RF10;`
259			`else`
260			`w_nstate <= S_ERROR;`
261			`end`
262			`S_RF10 :`
263			`begin`
264			`if(i_mk_rdy)`
265			`w_nstate <= S_RF11;`
266			`else`
267			`w_nstate <= S_ERROR;`
268			`end`
269			`S_RF11 :`
270			`begin`
271			`if(i_mk_rdy)`
272			`w_nstate <= S_RF12;`
273			`else`
274			`w_nstate <= S_ERROR;`
275			`end`
276			`S_RF12 :`
277			`begin`
278			`if(i_mk_rdy)`
279			`w_nstate <= S_RF13;`
280			`else`
281			`w_nstate <= S_ERROR;`
282			`end`
283			`S_RF13 :`
284			`begin`
285			`if(i_mk_rdy)`
286			`w_nstate <= S_RF14;`
287			`else`
288			`w_nstate <= S_ERROR;`
289			`end`
290			`S_RF14 :`
291			`begin`
292			`if(i_mk_rdy)`
293			`w_nstate <= S_RF15;`
294			`else`
295			`w_nstate <= S_ERROR;`
296			`end`
297			`S_RF15 :`
298			`begin`
299			`if(i_mk_rdy)`
300			`w_nstate <= S_RF16;`
301			`else`
302			`w_nstate <= S_ERROR;`
303			`end`
304			`S_RF16 :`
305			`begin`
306			`if(i_mk_rdy)`
307			`w_nstate <= S_RF17;`
308			`else`
309			`w_nstate <= S_ERROR;`
310			`end`
311			`S_RF17 :`
312			`begin`
313			`if(i_mk_rdy)`
314			`w_nstate <= S_RF18;`
315			`else`
316			`w_nstate <= S_ERROR;`
317			`end`
318			`S_RF18 :`
319			`begin`
320			`if(i_mk_rdy)`
321			`w_nstate <= S_RF19;`
322			`else`
323			`w_nstate <= S_ERROR;`
324			`end`
325			`S_RF19 :`
326			`begin`
327			`if(i_mk_rdy)`
328			`w_nstate <= S_RF20;`
329			`else`
330			`w_nstate <= S_ERROR;`
331			`end`
332			`S_RF20 :`
333			`begin`
334			`if(i_mk_rdy)`
335			`w_nstate <= S_RF21;`
336			`else`
337			`w_nstate <= S_ERROR;`
338			`end`
339			`S_RF21 :`
340			`begin`
341			`if(i_mk_rdy)`
342			`w_nstate <= S_RF22;`
343			`else`
344			`w_nstate <= S_ERROR;`
345			`end`
346			`S_RF22 :`
347			`begin`
348			`if(i_mk_rdy)`
349			`w_nstate <= S_RF23;`
350			`else`
351			`w_nstate <= S_ERROR;`
352			`end`
353			`S_RF23 :`
354			`begin`
355			`if(i_mk_rdy)`
356			`w_nstate <= S_RF24;`
357			`else`
358			`w_nstate <= S_ERROR;`
359			`end`
360			`S_RF24 :`
361			`begin`
362			`if(i_mk_rdy)`
363			`w_nstate <= S_RF25;`
364			`else`
365			`w_nstate <= S_ERROR;`
366			`end`
367			`S_RF25 :`
368			`begin`
369			`if(i_mk_rdy)`
370			`w_nstate <= S_RF26;`
371			`else`
372			`w_nstate <= S_ERROR;`
373			`end`
374			`S_RF26 :`
375			`begin`
376			`if(i_mk_rdy)`
377			`w_nstate <= S_RF27;`
378			`else`
379			`w_nstate <= S_ERROR;`
380			`end`
381			`S_RF27 :`
382			`begin`
383			`if(i_mk_rdy)`
384			`w_nstate <= S_RF28;`
385			`else`
386			`w_nstate <= S_ERROR;`
387			`end`
388			`S_RF28 :`
389			`begin`
390			`if(i_mk_rdy)`
391			`w_nstate <= S_RF29;`
392			`else`
393			`w_nstate <= S_ERROR;`
394			`end`
395			`S_RF29 :`
396			`begin`
397			`if(i_mk_rdy)`
398			`w_nstate <= S_RF30;`
399			`else`
400			`w_nstate <= S_ERROR;`
401			`end`
402			`S_RF30 :`
403			`begin`
404			`if(i_mk_rdy)`
405			`w_nstate <= S_RF31;`
406			`else`
407			`w_nstate <= S_ERROR;`
408			`end`
409			`S_RF31 :`
410			`begin`
411			`if(i_mk_rdy)`
412			`w_nstate <= S_RF32;`
413			`else`
414			`w_nstate <= S_ERROR;`
415			`end`
416			`S_RF32 :`
417			`begin`
418			`if(i_mk_rdy)`
419			`w_nstate <= S_DONE;`
420			`else`
421			`w_nstate <= S_ERROR;`
422			`end`
423			`S_DONE :`
424			`begin`
425			`if(i_post_rdy)`
426			`if(i_mk_rdy)`
427			`w_nstate <= S_RDY;`
428			`else`
429			`w_nstate <= S_KEY_CONFIG;`
430			`else`
431			`w_nstate <= r_pstate;`
432			`end`
433			`S_ERROR :`
434			`begin`
435			`w_nstate <= S_IDLE;`
436			`end`
437			`default :`
438			`begin`
439			`w_nstate <= S_ERROR;`
440			`end`
441			`endcase`
442
443
444			`// o_rdy`
445			`assign o_rdy = i_mk_rdy & (r_pstate == S_RDY);`
446
447			`// o_text_done`
448			`assign o_text_done = (r_pstate == S_DONE) & i_post_rdy;`
449
450			`// o_xf_sel`
451			`assign o_xf_sel[2] = (r_pstate == S_RDY) & i_text_val;`
452			`assign o_xf_sel[1:0] = ((r_pstate == S_RDY) & i_text_val) ? 2'b01 :`
453			`(((r_pstate != S_RDY) & ~r_pstate[5]) \| (r_pstate == S_RF31)) ? 2'b10 :`
454			`(r_pstate == S_RF32) ? 2'b01 :`
455			`2'b00 ;`
456			`// o_rf_final`
457			`assign o_rf_final = (r_pstate == S_RF31);`
458
459			`// o_key_sel`
460			`assign o_key_sel = ((r_pstate == S_RDY) & i_text_val) \| ((r_pstate != S_RDY) & (~r_pstate[5]));`
461
462			`// o_rnd_idx`
463			`assign o_rnd_idx = r_pstate[4:0];`
464
465			`// o_wf_post_pre`
466			`assign o_wf_post_pre = (r_pstate == S_RF31);`
467
468			`endmodule`
469
470
471
472