| 1 |
2 |
ericw |
/*
|
| 2 |
|
|
--------------------------------------------------------------------------------
|
| 3 |
|
|
|
| 4 |
|
|
Module : op_decode.v
|
| 5 |
|
|
|
| 6 |
|
|
--------------------------------------------------------------------------------
|
| 7 |
|
|
|
| 8 |
|
|
Function:
|
| 9 |
|
|
- Opcode decoder for processor.
|
| 10 |
|
|
|
| 11 |
|
|
Instantiates:
|
| 12 |
|
|
- (2x) vector_sr.v
|
| 13 |
|
|
|
| 14 |
|
|
Notes:
|
| 15 |
|
|
- I/O optionally registered.
|
| 16 |
|
|
- Middle register is always present.
|
| 17 |
|
|
- Operates on the current thread in the stage.
|
| 18 |
|
|
|
| 19 |
|
|
--------------------------------------------------------------------------------
|
| 20 |
|
|
*/
|
| 21 |
|
|
|
| 22 |
|
|
module op_decode
|
| 23 |
|
|
#(
|
| 24 |
|
|
parameter integer REGS_IN = 1, // register option for inputs
|
| 25 |
|
|
parameter integer REGS_OUT = 1, // register option for outputs
|
| 26 |
|
|
parameter integer STACKS = 4, // number of stacks
|
| 27 |
|
|
parameter integer STK_W = 2, // stack selector width
|
| 28 |
|
|
parameter integer DATA_W = 32, // data width
|
| 29 |
|
|
parameter integer IM_DATA_W = 8, // immediate data width
|
| 30 |
|
|
parameter integer IM_ADDR_W = 6, // immediate data width
|
| 31 |
|
|
parameter integer OP_CODE_W = 16, // op code width
|
| 32 |
|
|
parameter integer LG_W = 2 // logical operation width
|
| 33 |
|
|
)
|
| 34 |
|
|
(
|
| 35 |
|
|
// clocks & resets
|
| 36 |
|
|
input wire clk_i, // clock
|
| 37 |
|
|
input wire rst_i, // async. reset, active high
|
| 38 |
|
|
// state I/O
|
| 39 |
|
|
input wire thrd_clr_i, // thread clear
|
| 40 |
|
|
input wire thrd_intr_i, // thread interrupt
|
| 41 |
|
|
input wire [OP_CODE_W-1:0] op_code_i, // op_code
|
| 42 |
|
|
output wire op_code_er_o, // 1=illegal op code encountered
|
| 43 |
|
|
// data I/O
|
| 44 |
|
|
output wire [IM_DATA_W-1:0] im_data_o, // immediate data
|
| 45 |
|
|
output wire [IM_ADDR_W-1:0] im_addr_o, // immediate address (offset)
|
| 46 |
|
|
// pc pipe control
|
| 47 |
|
|
output wire pc_clr_o, // pc clear
|
| 48 |
|
|
output wire lit_o, // 1 : pc=pc++ for lit
|
| 49 |
|
|
output wire jmp_o, // 1 : pc=pc+B for jump (cond)
|
| 50 |
|
|
output wire gto_o, // 1 : pc=B for goto / gosub (cond)
|
| 51 |
|
|
output wire intr_o, // 1 : pc=intr
|
| 52 |
|
|
// conditional masks
|
| 53 |
|
|
output wire tst_eq_o, // = test
|
| 54 |
|
|
output wire tst_lt_o, // < test
|
| 55 |
|
|
output wire tst_gt_o, // > test
|
| 56 |
|
|
output wire tst_ab_o, // 1=a/b test; 0=a/z test
|
| 57 |
|
|
// stacks control
|
| 58 |
|
|
output wire stk_clr_o, // stacks clear
|
| 59 |
|
|
output wire [STACKS-1:0] pop_o, // stacks pop
|
| 60 |
|
|
output wire [STACKS-1:0] push_o, // stacks push
|
| 61 |
|
|
// alu control
|
| 62 |
|
|
output wire [STK_W-1:0] a_sel_o, // stack selector
|
| 63 |
|
|
output wire [STK_W-1:0] b_sel_o, // stack selector
|
| 64 |
|
|
output wire imda_o, // 1=immediate data
|
| 65 |
|
|
output wire imad_o, // 1=immediate address
|
| 66 |
|
|
output wire sgn_o, // 1=signed
|
| 67 |
|
|
output wire ext_o, // 1=extended
|
| 68 |
|
|
output wire [LG_W-1:0] lg_o, // see decode in notes
|
| 69 |
|
|
output wire add_o, // 1=add
|
| 70 |
|
|
output wire sub_o, // 1=subtract
|
| 71 |
|
|
output wire mul_o, // 1=multiply
|
| 72 |
|
|
output wire shl_o, // 1=shift left
|
| 73 |
|
|
output wire cpy_o, // 1=copy b
|
| 74 |
|
|
output wire dm_o, // 1=data mem
|
| 75 |
|
|
output wire rtn_o, // 1=return pc
|
| 76 |
|
|
output wire rd_o, // 1=read
|
| 77 |
|
|
output wire wr_o // 1=write
|
| 78 |
|
|
);
|
| 79 |
|
|
|
| 80 |
|
|
|
| 81 |
|
|
/*
|
| 82 |
|
|
----------------------
|
| 83 |
|
|
-- internal signals --
|
| 84 |
|
|
----------------------
|
| 85 |
|
|
*/
|
| 86 |
|
|
`include "op_encode.h"
|
| 87 |
|
|
wire thrd_clr, thrd_intr;
|
| 88 |
|
|
wire [OP_CODE_W-1:0] op_code;
|
| 89 |
|
|
reg op_ok, op_code_ok_lo, op_code_ok_hi;
|
| 90 |
|
|
wire op_code_er;
|
| 91 |
|
|
//
|
| 92 |
|
|
reg [IM_DATA_W-1:0] im_data;
|
| 93 |
|
|
reg [IM_ADDR_W-1:0] im_addr;
|
| 94 |
|
|
reg pc_clr;
|
| 95 |
|
|
reg intr, gto, jmp, lit;
|
| 96 |
|
|
reg tst_lo, tst_hi, tst_ab, tst_gt, tst_lt, tst_eq;
|
| 97 |
|
|
reg stk_clr;
|
| 98 |
|
|
reg a_pop, b_pop;
|
| 99 |
|
|
reg push_lo, push_hi;
|
| 100 |
|
|
wire [STACKS-1:0] pop, push;
|
| 101 |
|
|
reg [STK_W-1:0] a_sel, b_sel;
|
| 102 |
|
|
reg imad_6b, imad_5b;
|
| 103 |
|
|
reg imda_8b, imda_6b;
|
| 104 |
|
|
wire imad, imda;
|
| 105 |
|
|
reg rtn, dm, cpy, shl, mul, sub, add, ext, sgn;
|
| 106 |
|
|
reg [LG_W-1:0] lg;
|
| 107 |
|
|
reg rd, wr;
|
| 108 |
|
|
|
| 109 |
|
|
|
| 110 |
|
|
|
| 111 |
|
|
/*
|
| 112 |
|
|
================
|
| 113 |
|
|
== code start ==
|
| 114 |
|
|
================
|
| 115 |
|
|
*/
|
| 116 |
|
|
|
| 117 |
|
|
|
| 118 |
|
|
// optional input registers
|
| 119 |
|
|
vector_sr
|
| 120 |
|
|
#(
|
| 121 |
|
|
.REGS ( REGS_IN ),
|
| 122 |
|
|
.DATA_W ( 2+OP_CODE_W ),
|
| 123 |
|
|
.RESET_VAL ( 0 )
|
| 124 |
|
|
)
|
| 125 |
|
|
in_regs
|
| 126 |
|
|
(
|
| 127 |
|
|
.clk_i ( clk_i ),
|
| 128 |
|
|
.rst_i ( rst_i ),
|
| 129 |
|
|
.data_i ( { thrd_clr_i, thrd_intr_i, op_code_i } ),
|
| 130 |
|
|
.data_o ( { thrd_clr, thrd_intr, op_code } )
|
| 131 |
|
|
);
|
| 132 |
|
|
|
| 133 |
|
|
|
| 134 |
|
|
// instantiate & split out op_code fields
|
| 135 |
|
|
wire [1:0] op_code_a_sel = op_code[1:0];
|
| 136 |
|
|
wire [1:0] op_code_b_sel = op_code[3:2];
|
| 137 |
|
|
wire op_code_a_pop = op_code[4];
|
| 138 |
|
|
wire op_code_b_pop = op_code[5];
|
| 139 |
|
|
wire [9:0] op_code_op = op_code[15:6];
|
| 140 |
|
|
wire [2:0] op_code_tst_hi = op_code[14:12];
|
| 141 |
|
|
wire [2:0] op_code_tst_lo = op_code[8:6];
|
| 142 |
|
|
wire [7:0] op_code_im = op_code[13:6];
|
| 143 |
|
|
//
|
| 144 |
|
|
reg [2:0] tst_hi_field, tst_lo_field;
|
| 145 |
|
|
reg [7:0] im_field;
|
| 146 |
|
|
|
| 147 |
|
|
|
| 148 |
|
|
// mid register for immediate and test fields
|
| 149 |
|
|
always @ ( posedge clk_i or posedge rst_i ) begin
|
| 150 |
|
|
if ( rst_i ) begin
|
| 151 |
|
|
tst_hi_field <= 'b0;
|
| 152 |
|
|
tst_lo_field <= 'b0;
|
| 153 |
|
|
im_field <= 'b0;
|
| 154 |
|
|
end else begin
|
| 155 |
|
|
tst_hi_field <= op_code_tst_hi;
|
| 156 |
|
|
tst_lo_field <= op_code_tst_lo;
|
| 157 |
|
|
im_field <= op_code_im;
|
| 158 |
|
|
end
|
| 159 |
|
|
end
|
| 160 |
|
|
|
| 161 |
|
|
// mid register if & case: clear, interrupt, and op_code decode
|
| 162 |
|
|
always @ ( posedge clk_i or posedge rst_i ) begin
|
| 163 |
|
|
if ( rst_i ) begin
|
| 164 |
|
|
op_ok <= 'b0;
|
| 165 |
|
|
op_code_ok_lo <= 'b0;
|
| 166 |
|
|
op_code_ok_hi <= 'b0;
|
| 167 |
|
|
pc_clr <= 'b0;
|
| 168 |
|
|
lit <= 'b0;
|
| 169 |
|
|
jmp <= 'b0;
|
| 170 |
|
|
gto <= 'b0;
|
| 171 |
|
|
intr <= 'b0;
|
| 172 |
|
|
tst_hi <= 'b0;
|
| 173 |
|
|
tst_lo <= 'b0;
|
| 174 |
|
|
tst_ab <= 'b0;
|
| 175 |
|
|
stk_clr <= 'b0;
|
| 176 |
|
|
a_pop <= 'b0;
|
| 177 |
|
|
b_pop <= 'b0;
|
| 178 |
|
|
push_lo <= 'b0;
|
| 179 |
|
|
push_hi <= 'b0;
|
| 180 |
|
|
a_sel <= 'b0;
|
| 181 |
|
|
b_sel <= 'b0;
|
| 182 |
|
|
imad_6b <= 'b0;
|
| 183 |
|
|
imad_5b <= 'b0;
|
| 184 |
|
|
imda_8b <= 'b0;
|
| 185 |
|
|
imda_6b <= 'b0;
|
| 186 |
|
|
sgn <= 'b0;
|
| 187 |
|
|
ext <= 'b0;
|
| 188 |
|
|
lg <= 'b0;
|
| 189 |
|
|
add <= 'b0;
|
| 190 |
|
|
sub <= 'b0;
|
| 191 |
|
|
mul <= 'b0;
|
| 192 |
|
|
shl <= 'b0;
|
| 193 |
|
|
cpy <= 'b0;
|
| 194 |
|
|
dm <= 'b0;
|
| 195 |
|
|
rtn <= 'b0;
|
| 196 |
|
|
rd <= 'b0;
|
| 197 |
|
|
wr <= 'b0;
|
| 198 |
|
|
end else begin
|
| 199 |
|
|
// default values
|
| 200 |
|
|
op_ok <= 'b0; // default is bad op
|
| 201 |
|
|
op_code_ok_lo <= 'b0; // default is bad opcode
|
| 202 |
|
|
op_code_ok_hi <= 'b0; // default is bad opcode
|
| 203 |
|
|
pc_clr <= 'b0; // default is no pc clear
|
| 204 |
|
|
lit <= 'b0; // default is no lit
|
| 205 |
|
|
jmp <= 'b0; // default is no jump
|
| 206 |
|
|
gto <= 'b0; // default is no goto
|
| 207 |
|
|
intr <= 'b0; // default is no interrupt
|
| 208 |
|
|
tst_hi <= 'b0; // default is no test
|
| 209 |
|
|
tst_lo <= 'b0; // default is no test
|
| 210 |
|
|
tst_ab <= 'b0; // default is comparison to zero
|
| 211 |
|
|
stk_clr <= 'b0; // default is no stack clear
|
| 212 |
|
|
a_pop <= op_code_a_pop; // default is op_code directive
|
| 213 |
|
|
b_pop <= op_code_b_pop; // default is op_code directive
|
| 214 |
|
|
push_lo <= 'b0; // default is no push
|
| 215 |
|
|
push_hi <= 'b0; // default is no push
|
| 216 |
|
|
a_sel <= op_code_a_sel; // default is op_code directive
|
| 217 |
|
|
b_sel <= op_code_b_sel; // default is op_code directive
|
| 218 |
|
|
imad_6b <= 'b0; // default is not immediate address
|
| 219 |
|
|
imad_5b <= 'b0; // default is not immediate address
|
| 220 |
|
|
imda_8b <= 'b0; // default is not immediate data
|
| 221 |
|
|
imda_6b <= 'b0; // default is not immediate data
|
| 222 |
|
|
sgn <= 'b1; // default is signed!
|
| 223 |
|
|
ext <= 'b0; // default is unextended
|
| 224 |
|
|
lg <= 'b0; // default is a&b
|
| 225 |
|
|
add <= 'b0; // default is logic
|
| 226 |
|
|
sub <= 'b0; // default is logic
|
| 227 |
|
|
mul <= 'b0; // default is logic
|
| 228 |
|
|
shl <= 'b0; // default is logic
|
| 229 |
|
|
cpy <= 'b0; // default is logic
|
| 230 |
|
|
dm <= 'b0; // default is logic
|
| 231 |
|
|
rtn <= 'b0; // default is logic
|
| 232 |
|
|
rd <= 'b0; // default is don't read
|
| 233 |
|
|
wr <= 'b0; // default is don't write
|
| 234 |
|
|
if ( thrd_clr ) begin
|
| 235 |
|
|
op_ok <= 'b1; // good op
|
| 236 |
|
|
pc_clr <= 'b1; // clear pc
|
| 237 |
|
|
stk_clr <= 'b1; // clear stacks
|
| 238 |
|
|
a_pop <= 'b0; // no pop
|
| 239 |
|
|
b_pop <= 'b0; // no pop
|
| 240 |
|
|
end else if ( thrd_intr ) begin
|
| 241 |
|
|
op_ok <= 'b1; // good op
|
| 242 |
|
|
intr <= 'b1; // don't inc PC
|
| 243 |
|
|
a_pop <= 'b0; // no pop
|
| 244 |
|
|
b_pop <= 'b0; // no pop
|
| 245 |
|
|
push_lo <= 'b1; // push
|
| 246 |
|
|
a_sel <= 'b0; // push return address to stack 0
|
| 247 |
|
|
rtn <= 'b1; // push pc
|
| 248 |
|
|
end else begin
|
| 249 |
|
|
casex ( op_code_op )
|
| 250 |
|
|
///////////////////////////////////////
|
| 251 |
|
|
// immediate read & write - 64 codes //
|
| 252 |
|
|
///////////////////////////////////////
|
| 253 |
|
|
op_rd_i : begin
|
| 254 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 255 |
|
|
push_lo <= 'b1; // push
|
| 256 |
|
|
dm <= 'b1; // dm
|
| 257 |
|
|
rd <= 'b1; // read
|
| 258 |
|
|
end
|
| 259 |
|
|
op_rd_ix : begin
|
| 260 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 261 |
|
|
push_lo <= 'b1; // push
|
| 262 |
|
|
dm <= 'b1; // dm
|
| 263 |
|
|
rd <= 'b1; // read
|
| 264 |
|
|
ext <= 'b1; // extended
|
| 265 |
|
|
end
|
| 266 |
|
|
op_wr_i : begin
|
| 267 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 268 |
|
|
wr <= 'b1; // write
|
| 269 |
|
|
end
|
| 270 |
|
|
op_wr_ix : begin
|
| 271 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 272 |
|
|
wr <= 'b1; // write
|
| 273 |
|
|
ext <= 'b1; // extended
|
| 274 |
|
|
end
|
| 275 |
|
|
////////////////////////////////////////////
|
| 276 |
|
|
// immediate conditional jump - 384 codes //
|
| 277 |
|
|
////////////////////////////////////////////
|
| 278 |
|
|
op_jmp_iez, op_jmp_ilz, op_jmp_ilez : begin
|
| 279 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 280 |
|
|
jmp <= 'b1; // jump
|
| 281 |
|
|
imad_5b <= 'b1; // immediate address
|
| 282 |
|
|
tst_hi <= 'b1; // high field
|
| 283 |
|
|
end
|
| 284 |
|
|
op_jmp_ie, op_jmp_il, op_jmp_ile : begin
|
| 285 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 286 |
|
|
jmp <= 'b1; // jump
|
| 287 |
|
|
imad_5b <= 'b1; // immediate address
|
| 288 |
|
|
tst_hi <= 'b1; // high field
|
| 289 |
|
|
tst_ab <= 'b1; // a & b comparison
|
| 290 |
|
|
end
|
| 291 |
|
|
op_jmp_igz, op_jmp_igez, op_jmp_iglz : begin
|
| 292 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 293 |
|
|
jmp <= 'b1; // jump
|
| 294 |
|
|
imad_5b <= 'b1; // immediate address
|
| 295 |
|
|
tst_hi <= 'b1; // high field
|
| 296 |
|
|
end
|
| 297 |
|
|
op_jmp_iug, op_jmp_iuge, op_jmp_igl : begin // gl is sign neutral
|
| 298 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 299 |
|
|
jmp <= 'b1; // jump
|
| 300 |
|
|
imad_5b <= 'b1; // immediate address
|
| 301 |
|
|
tst_hi <= 'b1; // high field
|
| 302 |
|
|
tst_ab <= 'b1; // a & b comparison
|
| 303 |
|
|
sgn <= 'b0; // unsigned
|
| 304 |
|
|
end
|
| 305 |
|
|
/////////////////////////////////////////////
|
| 306 |
|
|
// immediate unconditional jump - 64 codes //
|
| 307 |
|
|
/////////////////////////////////////////////
|
| 308 |
|
|
op_jmp_i : begin
|
| 309 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 310 |
|
|
jmp <= 'b1; // jump
|
| 311 |
|
|
imad_6b <= 'b1; // immediate address
|
| 312 |
|
|
end
|
| 313 |
|
|
////////////////////////////////
|
| 314 |
|
|
// immediate data - 256 codes //
|
| 315 |
|
|
////////////////////////////////
|
| 316 |
|
|
op_byt_i : begin
|
| 317 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 318 |
|
|
push_lo <= 'b1; // push
|
| 319 |
|
|
imda_8b <= 'b1; // immediate data
|
| 320 |
|
|
cpy <= 'b1; // copy
|
| 321 |
|
|
end
|
| 322 |
|
|
/////////////////////////////////
|
| 323 |
|
|
// immediate shift - 128 codes //
|
| 324 |
|
|
/////////////////////////////////
|
| 325 |
|
|
op_shl_i : begin
|
| 326 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 327 |
|
|
push_lo <= 'b1; // push
|
| 328 |
|
|
imda_6b <= 'b1; // immediate data
|
| 329 |
|
|
shl <= 'b1; // shift left
|
| 330 |
|
|
end
|
| 331 |
|
|
op_shl_iu : begin
|
| 332 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 333 |
|
|
push_lo <= 'b1; // push
|
| 334 |
|
|
imda_6b <= 'b1; // immediate data
|
| 335 |
|
|
shl <= 'b1; // shift left
|
| 336 |
|
|
sgn <= 'b0; // unsigned
|
| 337 |
|
|
end
|
| 338 |
|
|
//////////////////////////////
|
| 339 |
|
|
// immediate add - 64 codes //
|
| 340 |
|
|
//////////////////////////////
|
| 341 |
|
|
op_add_i : begin
|
| 342 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 343 |
|
|
push_hi <= 'b1; // push
|
| 344 |
|
|
imda_6b <= 'b1; // immediate data
|
| 345 |
|
|
add <= 'b1; // add
|
| 346 |
|
|
end
|
| 347 |
|
|
/////////////////////////////////////
|
| 348 |
|
|
// conditional jump - 7 of 8 codes //
|
| 349 |
|
|
/////////////////////////////////////
|
| 350 |
|
|
op_jmp_ez, op_jmp_lz, op_jmp_lez, op_jmp_gz, op_jmp_gez, op_jmp_glz, op_jmp : begin
|
| 351 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 352 |
|
|
jmp <= 'b1; // jump
|
| 353 |
|
|
tst_lo <= 'b1; // low field
|
| 354 |
|
|
end
|
| 355 |
|
|
/////////////////////////////////////
|
| 356 |
|
|
// conditional goto - 7 of 8 codes //
|
| 357 |
|
|
/////////////////////////////////////
|
| 358 |
|
|
op_gto_ez, op_gto_lz, op_gto_lez, op_gto_gz, op_gto_gez, op_gto_glz, op_gto : begin
|
| 359 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 360 |
|
|
gto <= 'b1; // goto
|
| 361 |
|
|
tst_lo <= 'b1; // low field
|
| 362 |
|
|
end
|
| 363 |
|
|
////////////////////////
|
| 364 |
|
|
// singles - 48 codes //
|
| 365 |
|
|
////////////////////////
|
| 366 |
|
|
/////////////
|
| 367 |
|
|
// group 1 //
|
| 368 |
|
|
/////////////
|
| 369 |
|
|
op_add : begin
|
| 370 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 371 |
|
|
push_hi <= 'b1; // push
|
| 372 |
|
|
add <= 'b1; // add
|
| 373 |
|
|
end
|
| 374 |
|
|
op_add_x : begin
|
| 375 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 376 |
|
|
push_hi <= 'b1; // push
|
| 377 |
|
|
add <= 'b1; // add
|
| 378 |
|
|
ext <= 'b1; // extended
|
| 379 |
|
|
end
|
| 380 |
|
|
op_add_ux : begin
|
| 381 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 382 |
|
|
push_hi <= 'b1; // push
|
| 383 |
|
|
add <= 'b1; // add
|
| 384 |
|
|
ext <= 'b1; // extended
|
| 385 |
|
|
sgn <= 'b0; // unsigned
|
| 386 |
|
|
end
|
| 387 |
|
|
op_sub : begin
|
| 388 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 389 |
|
|
push_hi <= 'b1; // push
|
| 390 |
|
|
sub <= 'b1; // sub
|
| 391 |
|
|
end
|
| 392 |
|
|
op_sub_x : begin
|
| 393 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 394 |
|
|
push_hi <= 'b1; // push
|
| 395 |
|
|
sub <= 'b1; // sub
|
| 396 |
|
|
ext <= 'b1; // extended
|
| 397 |
|
|
end
|
| 398 |
|
|
op_sub_ux : begin
|
| 399 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 400 |
|
|
push_hi <= 'b1; // push
|
| 401 |
|
|
sub <= 'b1; // sub
|
| 402 |
|
|
ext <= 'b1; // extended
|
| 403 |
|
|
sgn <= 'b0; // unsigned
|
| 404 |
|
|
end
|
| 405 |
|
|
op_mul : begin
|
| 406 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 407 |
|
|
push_hi <= 'b1; // push
|
| 408 |
|
|
mul <= 'b1; // multiply
|
| 409 |
|
|
end
|
| 410 |
|
|
op_mul_x : begin
|
| 411 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 412 |
|
|
push_hi <= 'b1; // push
|
| 413 |
|
|
mul <= 'b1; // multiply
|
| 414 |
|
|
ext <= 'b1; // extended
|
| 415 |
|
|
end
|
| 416 |
|
|
op_mul_ux : begin
|
| 417 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 418 |
|
|
push_hi <= 'b1; // push
|
| 419 |
|
|
mul <= 'b1; // multiply
|
| 420 |
|
|
ext <= 'b1; // extended
|
| 421 |
|
|
sgn <= 'b0; // unsigned
|
| 422 |
|
|
end
|
| 423 |
|
|
op_shl : begin
|
| 424 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 425 |
|
|
push_hi <= 'b1; // push
|
| 426 |
|
|
shl <= 'b1; // shift left
|
| 427 |
|
|
end
|
| 428 |
|
|
op_shl_u : begin
|
| 429 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 430 |
|
|
push_hi <= 'b1; // push
|
| 431 |
|
|
shl <= 'b1; // shift left
|
| 432 |
|
|
sgn <= 'b0; // unsigned
|
| 433 |
|
|
end
|
| 434 |
|
|
/////////////
|
| 435 |
|
|
// group 2 //
|
| 436 |
|
|
/////////////
|
| 437 |
|
|
op_and : begin
|
| 438 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 439 |
|
|
push_hi <= 'b1; // push
|
| 440 |
|
|
end
|
| 441 |
|
|
op_or : begin
|
| 442 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 443 |
|
|
push_hi <= 'b1; // push
|
| 444 |
|
|
lg <= 'd1;
|
| 445 |
|
|
end
|
| 446 |
|
|
op_xor : begin
|
| 447 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 448 |
|
|
push_hi <= 'b1; // push
|
| 449 |
|
|
lg <= 'd2;
|
| 450 |
|
|
end
|
| 451 |
|
|
op_not : begin
|
| 452 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 453 |
|
|
push_hi <= 'b1; // push
|
| 454 |
|
|
lg <= 'd3;
|
| 455 |
|
|
end
|
| 456 |
|
|
op_and_b : begin
|
| 457 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 458 |
|
|
push_hi <= 'b1; // push
|
| 459 |
|
|
ext <= 'b1; // extended
|
| 460 |
|
|
end
|
| 461 |
|
|
op_or_b : begin
|
| 462 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 463 |
|
|
push_hi <= 'b1; // push
|
| 464 |
|
|
lg <= 'd1;
|
| 465 |
|
|
ext <= 'b1; // extended
|
| 466 |
|
|
end
|
| 467 |
|
|
op_xor_b : begin
|
| 468 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 469 |
|
|
push_hi <= 'b1; // push
|
| 470 |
|
|
lg <= 'd2;
|
| 471 |
|
|
ext <= 'b1; // extended
|
| 472 |
|
|
end
|
| 473 |
|
|
/////////////
|
| 474 |
|
|
// group 3 //
|
| 475 |
|
|
/////////////
|
| 476 |
|
|
op_lit : begin
|
| 477 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 478 |
|
|
push_hi <= 'b1; // push
|
| 479 |
|
|
lit <= 'b1; // lit
|
| 480 |
|
|
dm <= 'b1; // dm
|
| 481 |
|
|
end
|
| 482 |
|
|
op_lit_u : begin
|
| 483 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 484 |
|
|
push_hi <= 'b1; // push
|
| 485 |
|
|
lit <= 'b1; // lit
|
| 486 |
|
|
dm <= 'b1; // dm
|
| 487 |
|
|
sgn <= 'b0; // unsigned
|
| 488 |
|
|
end
|
| 489 |
|
|
op_lit_x : begin
|
| 490 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 491 |
|
|
push_hi <= 'b1; // push
|
| 492 |
|
|
lit <= 'b1; // lit
|
| 493 |
|
|
dm <= 'b1; // dm
|
| 494 |
|
|
ext <= 'b1; // extended
|
| 495 |
|
|
end
|
| 496 |
|
|
op_cpy : begin
|
| 497 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 498 |
|
|
push_hi <= 'b1; // push
|
| 499 |
|
|
cpy <= 'b1; // copy
|
| 500 |
|
|
end
|
| 501 |
|
|
op_pc : begin
|
| 502 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 503 |
|
|
push_hi <= 'b1; // push
|
| 504 |
|
|
rtn <= 'b1; // push pc
|
| 505 |
|
|
end
|
| 506 |
|
|
op_gsb : begin
|
| 507 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 508 |
|
|
push_hi <= 'b1; // push
|
| 509 |
|
|
gto <= 'b1; // goto
|
| 510 |
|
|
rtn <= 'b1; // push pc
|
| 511 |
|
|
end
|
| 512 |
|
|
op_cls : begin
|
| 513 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 514 |
|
|
stk_clr <= 'b1; // stack clear
|
| 515 |
|
|
a_pop <= 'b0; // no pop
|
| 516 |
|
|
b_pop <= 'b0; // no pop
|
| 517 |
|
|
end
|
| 518 |
|
|
op_pop : begin
|
| 519 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 520 |
|
|
end
|
| 521 |
|
|
op_nop : begin
|
| 522 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 523 |
|
|
a_pop <= 'b0; // no pop
|
| 524 |
|
|
b_pop <= 'b0; // no pop
|
| 525 |
|
|
end
|
| 526 |
|
|
default: begin
|
| 527 |
|
|
// nothing here
|
| 528 |
|
|
end
|
| 529 |
|
|
endcase
|
| 530 |
|
|
end
|
| 531 |
|
|
end
|
| 532 |
|
|
end
|
| 533 |
|
|
|
| 534 |
|
|
|
| 535 |
|
|
// decode test
|
| 536 |
|
|
always @ ( * ) begin
|
| 537 |
|
|
casex ( { tst_hi, tst_lo } )
|
| 538 |
|
|
2'b00 : { tst_gt, tst_lt, tst_eq } <= 3'b111; // default is always
|
| 539 |
|
|
2'b01 : { tst_gt, tst_lt, tst_eq } <= tst_lo_field;
|
| 540 |
|
|
2'b1x : { tst_gt, tst_lt, tst_eq } <= tst_hi_field;
|
| 541 |
|
|
endcase
|
| 542 |
|
|
end
|
| 543 |
|
|
|
| 544 |
|
|
// decode immediate data
|
| 545 |
|
|
always @ ( * ) begin
|
| 546 |
|
|
case ( imda_6b )
|
| 547 |
|
|
1'b0 : im_data <= im_field; // byte default
|
| 548 |
|
|
1'b1 : im_data <= $signed( im_field[5:0] ); // signed 6 bit
|
| 549 |
|
|
endcase
|
| 550 |
|
|
end
|
| 551 |
|
|
|
| 552 |
|
|
// decode immediate address
|
| 553 |
|
|
always @ ( * ) begin
|
| 554 |
|
|
case ( imad_5b )
|
| 555 |
|
|
1'b0 : im_addr <= im_field[IM_ADDR_W-1:0]; // 6 bit default
|
| 556 |
|
|
1'b1 : im_addr <= $signed( im_field[4:0] ); // signed 5 bit
|
| 557 |
|
|
endcase
|
| 558 |
|
|
end
|
| 559 |
|
|
|
| 560 |
|
|
// decode control
|
| 561 |
|
|
assign imda = imda_8b | imda_6b;
|
| 562 |
|
|
assign imad = imad_6b | imad_5b;
|
| 563 |
|
|
|
| 564 |
|
|
// decode pop & push
|
| 565 |
|
|
assign pop = ( a_pop << a_sel ) | ( b_pop << b_sel );
|
| 566 |
|
|
assign push = ( ( push_lo | push_hi ) << a_sel );
|
| 567 |
|
|
|
| 568 |
|
|
// decode errors
|
| 569 |
|
|
assign op_code_er = ~( op_ok | op_code_ok_lo | op_code_ok_hi );
|
| 570 |
|
|
|
| 571 |
|
|
|
| 572 |
|
|
// optional output registers
|
| 573 |
|
|
vector_sr
|
| 574 |
|
|
#(
|
| 575 |
|
|
.REGS ( REGS_OUT ),
|
| 576 |
|
|
.DATA_W ( 1+IM_ADDR_W+IM_DATA_W+10+STACKS+STACKS+STK_W+STK_W+9+LG_W+4 ),
|
| 577 |
|
|
.RESET_VAL ( 0 )
|
| 578 |
|
|
)
|
| 579 |
|
|
out_regs
|
| 580 |
|
|
(
|
| 581 |
|
|
.clk_i ( clk_i ),
|
| 582 |
|
|
.rst_i ( rst_i ),
|
| 583 |
|
|
.data_i ( { op_code_er, im_addr, im_data, pc_clr, intr, gto, jmp, lit, tst_gt, tst_lt, tst_eq, tst_ab, stk_clr, pop, push, a_sel, b_sel, imda, imad, rtn, dm, cpy, shl, mul, sub, add, lg, ext, sgn, rd, wr } ),
|
| 584 |
|
|
.data_o ( { op_code_er_o, im_addr_o, im_data_o, pc_clr_o, intr_o, gto_o, jmp_o, lit_o, tst_gt_o, tst_lt_o, tst_eq_o, tst_ab_o, stk_clr_o, pop_o, push_o, a_sel_o, b_sel_o, imda_o, imad_o, rtn_o, dm_o, cpy_o, shl_o, mul_o, sub_o, add_o, lg_o, ext_o, sgn_o, rd_o, wr_o } )
|
| 585 |
|
|
);
|
| 586 |
|
|
|
| 587 |
|
|
|
| 588 |
|
|
endmodule
|
