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[/] [hive/] [trunk/] [v01.09/] [reg_set.v] - Blame information for rev 2

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/*
--------------------------------------------------------------------------------
 
Module: reg_set.v
 
Function:
- Internal register set for a processor.
 
Instantiates:
- (8x) proc_reg.v
- (2x) vector_sr.v
 
Notes:
- Processor bus IN/OUT optionally registered.
 
Decode:
- 0x0 : Core version register - ver_reg
- 0x1 : Thread ID register - thrd_id_reg
- 0x2 : Clear register - clr_reg
- 0x3 : Interrupt enable register - intr_en_reg
- 0x4 : Opcode error register - op_er_reg
- 0x5 : Stack error register - stk_er_reg
- 0x6 - 0x7 : UNUSED
- 0x8 : I/O low register - io_lo_reg
- 0x9 : I/O high register - io_hi_reg
- 0xA - 0xF : UNUSED
 
 
================================================================================
- 0x0 : Core version register - ver_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
  7-0  ver_min[7:0]         minor version info
 15-8  ver_maj[7:0]         major version info
 
Notes:
- Read-only.
- Nibbles S/B BCD (0-9; no A-F) to be easily human readable,
  and to eliminate confusion between decimal and hex here.
- Major version changes when op_code binary decode changes (incompatibilty).
 
================================================================================
- 0x1 : Thread ID register - thrd_id_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
  2-0  thrd_id[2:0]         thread ID
 15-3  -                    0000000000000
 
Notes:
- Read-only.
- Threads can read this to discover their thread ID.
 
================================================================================
- 0x2 : Clear register - clr_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
  7-0  clr[7:0]             0=>1 clear thread; 1=>0 no effect;
 15-8  -                    00000000
 
Notes:
- Read / write.
- Per thread clearing.
- All bits cleared on async reset.
 
================================================================================
- 0x3 : Interrupt enable register - intr_en_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
  7-0  intr_en[7:0]         1=thread interrupt enable; 0=disable
 15-8  -                    00000000
 
Notes:
- Read / write.
- Per thread enabling of interrupts.
- All bits cleared on async reset.
 
================================================================================
- 0x4 : Opcode error register - op_er_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
  7-0  op_er[7:0]           1=opcode error; 0=OK
 15-8  -                    00000000
 
Notes:
- Clear on write one.
- Per thread opcode error reporting.
 
================================================================================
- 0x5 : Stack error register - stk_er_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
  7-0  pop_er[7:0]          1=lifo pop when empty; 0=OK
 15-8  push_er[7:0]         1=lifo push when full; 0=OK
 
Notes:
- Clear on write one.
- Per thread LIFO stack error reporting.
 
================================================================================
- 0x6 - 0x7 : UNUSED
================================================================================
- 0x8 : I/O low register - io_lo_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
 15-0  io_lo[15:0]          I/O data
 
Notes:
- Separate read / write.
- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
  read io_hi_reg for contiguous wide (32 bit) data reads.
- Writes function normally.
 
================================================================================
- 0x9 : I/O high register - io_hi_reg
--------------------------------------------------------------------------------
 
  bit  name                 description
-----  ----                 -----------
 15-0  io_hi[15:0]          I/O data
 
Notes:
- Separate read / write.
- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
  read io_hi_reg for contiguous wide (32 bit) data reads.
- Writes function normally.
 
================================================================================
- 0xA - 0xF : UNUSED
================================================================================
*/
 
module reg_set
        #(
        parameter       integer                                                 REGS_IN                 = 1,            // bus in register option
        parameter       integer                                                 REGS_OUT                        = 1,            // bus out register option
        parameter       integer                                                 DATA_W                  = 16,           // data width (bits)
        parameter       integer                                                 ADDR_W                  = 4,            // address width (bits)
        parameter       integer                                                 THREADS                 = 8,            // threads
        parameter       integer                                                 THRD_W                  = 3,            // thread selector width
        parameter       integer                                                 STACKS                  = 4,            // stacks
        parameter       integer                                                 STK_W                           = 2,            // stack selector width
        //
        parameter       [DATA_W/2-1:0]                                   VER_MAJ                 = 'h1,  // core version
        parameter       [DATA_W/2-1:0]                                   VER_MIN                 = 'h0
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // bus interface
        input                   wire    [ADDR_W-1:0]                     addr_i,                                         // address
        input                   wire                                                            wr_i,                                                   // data write enable, active high
        input                   wire                                                            rd_i,                                                   // data read enable, active high
        input                   wire    [DATA_W-1:0]                     data_i,                                         // write data
        output          wire    [DATA_W-1:0]                     data_o,                                         // read data
        // data memory interface
        input                   wire    [DATA_W-1:0]                     dm_data_i,                                      // dm read data
        // clear
        output          wire    [THREADS-1:0]                    clr_req_o,                                      // clr request, active high
        // interrupt
        output          wire    [THREADS-1:0]                    intr_en_o,                                      // interrupt enable, active high
        // errors
        input                   wire    [THRD_W-1:0]                     thrd_0_i,                                       // thread
        input                   wire                                                            op_code_er_i,                           // 1=illegal op code encountered
        input                   wire    [THRD_W-1:0]                     thrd_2_i,                                       // thread
        input                   wire    [STACKS-1:0]                     pop_er_i,                                       // pop when empty, active high 
        input                   wire    [THRD_W-1:0]                     thrd_3_i,                                       // thread
        input                   wire    [STACKS-1:0]                     push_er_i,                                      // push when full, active high
        // I/O
        input                   wire    [DATA_W-1:0]                     io_lo_i,                                                // gpio linked to io_hi_i
        input                   wire    [DATA_W-1:0]                     io_hi_i,
        output          wire    [DATA_W-1:0]                     io_lo_o,                                                // unlinked gpio
        output          wire    [DATA_W-1:0]                     io_hi_o
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        `include "reg_set_addr.h"
        //
        wire                                    [ADDR_W-1:0]                     addr;
        wire                                                                                            en, reg_en, wr, rd;
        wire                                    [DATA_W-1:0]                     rd_data, wr_data, reg_rd_data;
        wire                                    [DATA_W-1:0]                     ver_data,
                                                                                                                thrd_id_data,
                                                                                                                clr_data,
                                                                                                                intr_en_data,
                                                                                                                op_er_data,
                                                                                                                stk_er_data,
                                                                                                                io_lo_data,
                                                                                                                io_hi_data;
        //
        wire                                                                                            io_lo_reg_rd;
        wire                                    [THREADS-1:0]                    op_code_errors, push_errors, pop_errors;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
 
        // optional bus input regs
        vector_sr
        #(
        .REGS                   ( REGS_IN ),
        .DATA_W         ( ADDR_W+2+DATA_W ),
        .RESET_VAL      ( 0 )
        )
        in_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { addr_i, wr_i, rd_i, data_i } ),
        .data_o         ( { addr, wr, rd, wr_data } )
        );
 
 
        // big ORing of read data
        assign rd_data =
                ver_data |
                thrd_id_data |
                clr_data |
                intr_en_data |
                op_er_data |
                stk_er_data |
                io_lo_data |
                io_hi_data;
 
        // decode enable
        assign en = ( rd | wr );
 
 
        // optional output regs
        vector_sr
        #(
        .REGS                   ( REGS_OUT ),
        .DATA_W         ( 1+DATA_W ),
        .RESET_VAL      ( 0 )
        )
        out_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { en, rd_data } ),
        .data_o         ( { reg_en, reg_rd_data } )
        );
 
 
        // output mux
        assign data_o = ( reg_en ) ? reg_rd_data : dm_data_i;
 
 
 
        /*
        -------------
        -- ver_reg --
        -------------
        */
 
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( VER_ADDR ),
        .OUT_MODE               ( "ZERO" ),
        .READ_MODE              ( "THRU" )
        )
        ver_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( ver_data ),
        .reg_data_i             ( { VER_MAJ, VER_MIN } )
        );
 
 
        /*
        -----------------
        -- thrd_id_reg --
        -----------------
        */
 
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( THRD_ID_ADDR ),
        .OUT_MODE               ( "ZERO" ),
        .READ_MODE              ( "THRU" ),
        .LIVE_MASK              ( { THRD_W{ 1'b1 } } )
        )
        thrd_id_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( thrd_id_data ),
        .reg_data_i             ( thrd_3_i )
        );
 
 
        /*
        -------------
        -- clr_reg --
        -------------
        */
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( CLR_ADDR ),
        .OUT_MODE               ( "LTCH" ),
        .READ_MODE              ( "OUT" ),
        .LIVE_MASK              ( { THREADS{ 1'b1 } } )
        )
        clr_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( clr_data ),
        .reg_data_o             ( clr_req_o )
        );
 
 
        /*
        -----------------
        -- intr_en_reg --
        -----------------
        */
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( INTR_EN_ADDR ),
        .OUT_MODE               ( "LTCH" ),
        .READ_MODE              ( "OUT" ),
        .LIVE_MASK              ( { THREADS{ 1'b1 } } )
        )
        intr_en_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( intr_en_data ),
        .reg_data_o             ( intr_en_o )
        );
 
 
        /*
        ---------------
        -- op_er_reg --
        ---------------
        */
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( OP_ER_ADDR ),
        .OUT_MODE               ( "ZERO" ),
        .READ_MODE              ( "COW1" ),
        .LIVE_MASK              ( { THREADS{ 1'b1 } } )
        )
        op_er_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( op_er_data ),
        .reg_data_i             ( op_code_errors )
        );
 
        // decode errors
        assign op_code_errors = op_code_er_i << thrd_0_i;
 
 
        /*
        ----------------
        -- stk_er_reg --
        ----------------
        */
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( STK_ER_ADDR ),
        .OUT_MODE               ( "ZERO" ),
        .READ_MODE              ( "COW1" ),
        .LIVE_MASK              ( { (THREADS+THREADS){ 1'b1 } } )
        )
        stk_er_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( stk_er_data ),
        .reg_data_i             ( { push_errors, pop_errors } )
        );
 
        // decode errors
        assign push_errors = |push_er_i << thrd_3_i;
        assign pop_errors = |pop_er_i << thrd_2_i;
 
 
        /*
        ---------------
        -- io_lo_reg --
        ---------------
        */
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( IO_LO_ADDR ),
        .OUT_MODE               ( "LTCH" ),
        .READ_MODE              ( "THRU" )
        )
        io_lo_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( io_lo_data ),
        .reg_rd_o               ( io_lo_reg_rd ),
        .reg_data_i             ( io_lo_i ),
        .reg_data_o             ( io_lo_o )
        );
 
 
        /*
        ---------------
        -- io_hi_reg --
        ---------------
        */
        proc_reg
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .ADDRESS                        ( IO_HI_ADDR ),
        .OUT_MODE               ( "LTCH" ),
        .READ_MODE              ( "DFFE" )
        )
        io_hi_reg
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .addr_i                 ( addr ),
        .wr_i                           ( wr ),
        .rd_i                           ( rd ),
        .data_i                 ( wr_data ),
        .data_o                 ( io_hi_data ),
        .reg_en_i               ( io_lo_reg_rd ),  // enable on lo read
        .reg_data_i             ( io_hi_i ),
        .reg_data_o             ( io_hi_o )
        );
 
 
endmodule

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[/] [hive/] [trunk/] [v01.09/] [reg_set.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module: reg_set.v`
5
6			`Function:`
7			`- Internal register set for a processor.`
8
9			`Instantiates:`
10			`- (8x) proc_reg.v`
11			`- (2x) vector_sr.v`
12
13			`Notes:`
14			`- Processor bus IN/OUT optionally registered.`
15
16			`Decode:`
17			`- 0x0 : Core version register - ver_reg`
18			`- 0x1 : Thread ID register - thrd_id_reg`
19			`- 0x2 : Clear register - clr_reg`
20			`- 0x3 : Interrupt enable register - intr_en_reg`
21			`- 0x4 : Opcode error register - op_er_reg`
22			`- 0x5 : Stack error register - stk_er_reg`
23			`- 0x6 - 0x7 : UNUSED`
24			`- 0x8 : I/O low register - io_lo_reg`
25			`- 0x9 : I/O high register - io_hi_reg`
26			`- 0xA - 0xF : UNUSED`
27
28
29			`================================================================================`
30			`- 0x0 : Core version register - ver_reg`
31			`--------------------------------------------------------------------------------`
32
33			`bit name description`
34			`----- ---- -----------`
35			`7-0 ver_min[7:0] minor version info`
36			`15-8 ver_maj[7:0] major version info`
37
38			`Notes:`
39			`- Read-only.`
40			`- Nibbles S/B BCD (0-9; no A-F) to be easily human readable,`
41			`and to eliminate confusion between decimal and hex here.`
42			`- Major version changes when op_code binary decode changes (incompatibilty).`
43
44			`================================================================================`
45			`- 0x1 : Thread ID register - thrd_id_reg`
46			`--------------------------------------------------------------------------------`
47
48			`bit name description`
49			`----- ---- -----------`
50			`2-0 thrd_id[2:0] thread ID`
51			`15-3 - 0000000000000`
52
53			`Notes:`
54			`- Read-only.`
55			`- Threads can read this to discover their thread ID.`
56
57			`================================================================================`
58			`- 0x2 : Clear register - clr_reg`
59			`--------------------------------------------------------------------------------`
60
61			`bit name description`
62			`----- ---- -----------`
63			`7-0 clr[7:0] 0=>1 clear thread; 1=>0 no effect;`
64			`15-8 - 00000000`
65
66			`Notes:`
67			`- Read / write.`
68			`- Per thread clearing.`
69			`- All bits cleared on async reset.`
70
71			`================================================================================`
72			`- 0x3 : Interrupt enable register - intr_en_reg`
73			`--------------------------------------------------------------------------------`
74
75			`bit name description`
76			`----- ---- -----------`
77			`7-0 intr_en[7:0] 1=thread interrupt enable; 0=disable`
78			`15-8 - 00000000`
79
80			`Notes:`
81			`- Read / write.`
82			`- Per thread enabling of interrupts.`
83			`- All bits cleared on async reset.`
84
85			`================================================================================`
86			`- 0x4 : Opcode error register - op_er_reg`
87			`--------------------------------------------------------------------------------`
88
89			`bit name description`
90			`----- ---- -----------`
91			`7-0 op_er[7:0] 1=opcode error; 0=OK`
92			`15-8 - 00000000`
93
94			`Notes:`
95			`- Clear on write one.`
96			`- Per thread opcode error reporting.`
97
98			`================================================================================`
99			`- 0x5 : Stack error register - stk_er_reg`
100			`--------------------------------------------------------------------------------`
101
102			`bit name description`
103			`----- ---- -----------`
104			`7-0 pop_er[7:0] 1=lifo pop when empty; 0=OK`
105			`15-8 push_er[7:0] 1=lifo push when full; 0=OK`
106
107			`Notes:`
108			`- Clear on write one.`
109			`- Per thread LIFO stack error reporting.`
110
111			`================================================================================`
112			`- 0x6 - 0x7 : UNUSED`
113			`================================================================================`
114			`- 0x8 : I/O low register - io_lo_reg`
115			`--------------------------------------------------------------------------------`
116
117			`bit name description`
118			`----- ---- -----------`
119			`15-0 io_lo[15:0] I/O data`
120
121			`Notes:`
122			`- Separate read / write.`
123			`- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then`
124			`read io_hi_reg for contiguous wide (32 bit) data reads.`
125			`- Writes function normally.`
126
127			`================================================================================`
128			`- 0x9 : I/O high register - io_hi_reg`
129			`--------------------------------------------------------------------------------`
130
131			`bit name description`
132			`----- ---- -----------`
133			`15-0 io_hi[15:0] I/O data`
134
135			`Notes:`
136			`- Separate read / write.`
137			`- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then`
138			`read io_hi_reg for contiguous wide (32 bit) data reads.`
139			`- Writes function normally.`
140
141			`================================================================================`
142			`- 0xA - 0xF : UNUSED`
143			`================================================================================`
144			`*/`
145
146			`module reg_set`
147			`#(`
148			`parameter integer REGS_IN = 1, // bus in register option`
149			`parameter integer REGS_OUT = 1, // bus out register option`
150			`parameter integer DATA_W = 16, // data width (bits)`
151			`parameter integer ADDR_W = 4, // address width (bits)`
152			`parameter integer THREADS = 8, // threads`
153			`parameter integer THRD_W = 3, // thread selector width`
154			`parameter integer STACKS = 4, // stacks`
155			`parameter integer STK_W = 2, // stack selector width`
156			`//`
157			`parameter [DATA_W/2-1:0] VER_MAJ = 'h1, // core version`
158			`parameter [DATA_W/2-1:0] VER_MIN = 'h0`
159			`)`
160			`(`
161			`// clocks & resets`
162			`input wire clk_i, // clock`
163			`input wire rst_i, // async. reset, active high`
164			`// bus interface`
165			`input wire [ADDR_W-1:0] addr_i, // address`
166			`input wire wr_i, // data write enable, active high`
167			`input wire rd_i, // data read enable, active high`
168			`input wire [DATA_W-1:0] data_i, // write data`
169			`output wire [DATA_W-1:0] data_o, // read data`
170			`// data memory interface`
171			`input wire [DATA_W-1:0] dm_data_i, // dm read data`
172			`// clear`
173			`output wire [THREADS-1:0] clr_req_o, // clr request, active high`
174			`// interrupt`
175			`output wire [THREADS-1:0] intr_en_o, // interrupt enable, active high`
176			`// errors`
177			`input wire [THRD_W-1:0] thrd_0_i, // thread`
178			`input wire op_code_er_i, // 1=illegal op code encountered`
179			`input wire [THRD_W-1:0] thrd_2_i, // thread`
180			`input wire [STACKS-1:0] pop_er_i, // pop when empty, active high`
181			`input wire [THRD_W-1:0] thrd_3_i, // thread`
182			`input wire [STACKS-1:0] push_er_i, // push when full, active high`
183			`// I/O`
184			`input wire [DATA_W-1:0] io_lo_i, // gpio linked to io_hi_i`
185			`input wire [DATA_W-1:0] io_hi_i,`
186			`output wire [DATA_W-1:0] io_lo_o, // unlinked gpio`
187			`output wire [DATA_W-1:0] io_hi_o`
188			`);`
189
190
191			`/*`
192			`----------------------`
193			`-- internal signals --`
194			`----------------------`
195			`*/`
196			`include "reg_set_addr.h"
197			`//`
198			`wire [ADDR_W-1:0] addr;`
199			`wire en, reg_en, wr, rd;`
200			`wire [DATA_W-1:0] rd_data, wr_data, reg_rd_data;`
201			`wire [DATA_W-1:0] ver_data,`
202			`thrd_id_data,`
203			`clr_data,`
204			`intr_en_data,`
205			`op_er_data,`
206			`stk_er_data,`
207			`io_lo_data,`
208			`io_hi_data;`
209			`//`
210			`wire io_lo_reg_rd;`
211			`wire [THREADS-1:0] op_code_errors, push_errors, pop_errors;`
212
213
214
215			`/*`
216			`================`
217			`== code start ==`
218			`================`
219			`*/`
220
221
222
223			`// optional bus input regs`
224			`vector_sr`
225			`#(`
226			`.REGS ( REGS_IN ),`
227			`.DATA_W ( ADDR_W+2+DATA_W ),`
228			`.RESET_VAL ( 0 )`
229			`)`
230			`in_regs`
231			`(`
232			`.clk_i ( clk_i ),`
233			`.rst_i ( rst_i ),`
234			`.data_i ( { addr_i, wr_i, rd_i, data_i } ),`
235			`.data_o ( { addr, wr, rd, wr_data } )`
236			`);`
237
238
239			`// big ORing of read data`
240			`assign rd_data =`
241			`ver_data \|`
242			`thrd_id_data \|`
243			`clr_data \|`
244			`intr_en_data \|`
245			`op_er_data \|`
246			`stk_er_data \|`
247			`io_lo_data \|`
248			`io_hi_data;`
249
250			`// decode enable`
251			`assign en = ( rd \| wr );`
252
253
254			`// optional output regs`
255			`vector_sr`
256			`#(`
257			`.REGS ( REGS_OUT ),`
258			`.DATA_W ( 1+DATA_W ),`
259			`.RESET_VAL ( 0 )`
260			`)`
261			`out_regs`
262			`(`
263			`.clk_i ( clk_i ),`
264			`.rst_i ( rst_i ),`
265			`.data_i ( { en, rd_data } ),`
266			`.data_o ( { reg_en, reg_rd_data } )`
267			`);`
268
269
270			`// output mux`
271			`assign data_o = ( reg_en ) ? reg_rd_data : dm_data_i;`
272
273
274
275			`/*`
276			`-------------`
277			`-- ver_reg --`
278			`-------------`
279			`*/`
280
281			`proc_reg`
282			`#(`
283			`.DATA_W ( DATA_W ),`
284			`.ADDR_W ( ADDR_W ),`
285			`.ADDRESS ( VER_ADDR ),`
286			`.OUT_MODE ( "ZERO" ),`
287			`.READ_MODE ( "THRU" )`
288			`)`
289			`ver_reg`
290			`(`
291			`.clk_i ( clk_i ),`
292			`.rst_i ( rst_i ),`
293			`.addr_i ( addr ),`
294			`.wr_i ( wr ),`
295			`.rd_i ( rd ),`
296			`.data_i ( wr_data ),`
297			`.data_o ( ver_data ),`
298			`.reg_data_i ( { VER_MAJ, VER_MIN } )`
299			`);`
300
301
302			`/*`
303			`-----------------`
304			`-- thrd_id_reg --`
305			`-----------------`
306			`*/`
307
308			`proc_reg`
309			`#(`
310			`.DATA_W ( DATA_W ),`
311			`.ADDR_W ( ADDR_W ),`
312			`.ADDRESS ( THRD_ID_ADDR ),`
313			`.OUT_MODE ( "ZERO" ),`
314			`.READ_MODE ( "THRU" ),`
315			`.LIVE_MASK ( { THRD_W{ 1'b1 } } )`
316			`)`
317			`thrd_id_reg`
318			`(`
319			`.clk_i ( clk_i ),`
320			`.rst_i ( rst_i ),`
321			`.addr_i ( addr ),`
322			`.wr_i ( wr ),`
323			`.rd_i ( rd ),`
324			`.data_i ( wr_data ),`
325			`.data_o ( thrd_id_data ),`
326			`.reg_data_i ( thrd_3_i )`
327			`);`
328
329
330			`/*`
331			`-------------`
332			`-- clr_reg --`
333			`-------------`
334			`*/`
335			`proc_reg`
336			`#(`
337			`.DATA_W ( DATA_W ),`
338			`.ADDR_W ( ADDR_W ),`
339			`.ADDRESS ( CLR_ADDR ),`
340			`.OUT_MODE ( "LTCH" ),`
341			`.READ_MODE ( "OUT" ),`
342			`.LIVE_MASK ( { THREADS{ 1'b1 } } )`
343			`)`
344			`clr_reg`
345			`(`
346			`.clk_i ( clk_i ),`
347			`.rst_i ( rst_i ),`
348			`.addr_i ( addr ),`
349			`.wr_i ( wr ),`
350			`.rd_i ( rd ),`
351			`.data_i ( wr_data ),`
352			`.data_o ( clr_data ),`
353			`.reg_data_o ( clr_req_o )`
354			`);`
355
356
357			`/*`
358			`-----------------`
359			`-- intr_en_reg --`
360			`-----------------`
361			`*/`
362			`proc_reg`
363			`#(`
364			`.DATA_W ( DATA_W ),`
365			`.ADDR_W ( ADDR_W ),`
366			`.ADDRESS ( INTR_EN_ADDR ),`
367			`.OUT_MODE ( "LTCH" ),`
368			`.READ_MODE ( "OUT" ),`
369			`.LIVE_MASK ( { THREADS{ 1'b1 } } )`
370			`)`
371			`intr_en_reg`
372			`(`
373			`.clk_i ( clk_i ),`
374			`.rst_i ( rst_i ),`
375			`.addr_i ( addr ),`
376			`.wr_i ( wr ),`
377			`.rd_i ( rd ),`
378			`.data_i ( wr_data ),`
379			`.data_o ( intr_en_data ),`
380			`.reg_data_o ( intr_en_o )`
381			`);`
382
383
384			`/*`
385			`---------------`
386			`-- op_er_reg --`
387			`---------------`
388			`*/`
389			`proc_reg`
390			`#(`
391			`.DATA_W ( DATA_W ),`
392			`.ADDR_W ( ADDR_W ),`
393			`.ADDRESS ( OP_ER_ADDR ),`
394			`.OUT_MODE ( "ZERO" ),`
395			`.READ_MODE ( "COW1" ),`
396			`.LIVE_MASK ( { THREADS{ 1'b1 } } )`
397			`)`
398			`op_er_reg`
399			`(`
400			`.clk_i ( clk_i ),`
401			`.rst_i ( rst_i ),`
402			`.addr_i ( addr ),`
403			`.wr_i ( wr ),`
404			`.rd_i ( rd ),`
405			`.data_i ( wr_data ),`
406			`.data_o ( op_er_data ),`
407			`.reg_data_i ( op_code_errors )`
408			`);`
409
410			`// decode errors`
411			`assign op_code_errors = op_code_er_i << thrd_0_i;`
412
413
414			`/*`
415			`----------------`
416			`-- stk_er_reg --`
417			`----------------`
418			`*/`
419			`proc_reg`
420			`#(`
421			`.DATA_W ( DATA_W ),`
422			`.ADDR_W ( ADDR_W ),`
423			`.ADDRESS ( STK_ER_ADDR ),`
424			`.OUT_MODE ( "ZERO" ),`
425			`.READ_MODE ( "COW1" ),`
426			`.LIVE_MASK ( { (THREADS+THREADS){ 1'b1 } } )`
427			`)`
428			`stk_er_reg`
429			`(`
430			`.clk_i ( clk_i ),`
431			`.rst_i ( rst_i ),`
432			`.addr_i ( addr ),`
433			`.wr_i ( wr ),`
434			`.rd_i ( rd ),`
435			`.data_i ( wr_data ),`
436			`.data_o ( stk_er_data ),`
437			`.reg_data_i ( { push_errors, pop_errors } )`
438			`);`
439
440			`// decode errors`
441			`assign push_errors = \|push_er_i << thrd_3_i;`
442			`assign pop_errors = \|pop_er_i << thrd_2_i;`
443
444
445			`/*`
446			`---------------`
447			`-- io_lo_reg --`
448			`---------------`
449			`*/`
450			`proc_reg`
451			`#(`
452			`.DATA_W ( DATA_W ),`
453			`.ADDR_W ( ADDR_W ),`
454			`.ADDRESS ( IO_LO_ADDR ),`
455			`.OUT_MODE ( "LTCH" ),`
456			`.READ_MODE ( "THRU" )`
457			`)`
458			`io_lo_reg`
459			`(`
460			`.clk_i ( clk_i ),`
461			`.rst_i ( rst_i ),`
462			`.addr_i ( addr ),`
463			`.wr_i ( wr ),`
464			`.rd_i ( rd ),`
465			`.data_i ( wr_data ),`
466			`.data_o ( io_lo_data ),`
467			`.reg_rd_o ( io_lo_reg_rd ),`
468			`.reg_data_i ( io_lo_i ),`
469			`.reg_data_o ( io_lo_o )`
470			`);`
471
472
473			`/*`
474			`---------------`
475			`-- io_hi_reg --`
476			`---------------`
477			`*/`
478			`proc_reg`
479			`#(`
480			`.DATA_W ( DATA_W ),`
481			`.ADDR_W ( ADDR_W ),`
482			`.ADDRESS ( IO_HI_ADDR ),`
483			`.OUT_MODE ( "LTCH" ),`
484			`.READ_MODE ( "DFFE" )`
485			`)`
486			`io_hi_reg`
487			`(`
488			`.clk_i ( clk_i ),`
489			`.rst_i ( rst_i ),`
490			`.addr_i ( addr ),`
491			`.wr_i ( wr ),`
492			`.rd_i ( rd ),`
493			`.data_i ( wr_data ),`
494			`.data_o ( io_hi_data ),`
495			`.reg_en_i ( io_lo_reg_rd ), // enable on lo read`
496			`.reg_data_i ( io_hi_i ),`
497			`.reg_data_o ( io_hi_o )`
498			`);`
499
500
501			`endmodule`