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[/] [hive/] [trunk/] [v01.10/] [alu_add_sub.v] - Blame information for rev 3

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/*
--------------------------------------------------------------------------------
 
Module : alu_add_sub.v
 
--------------------------------------------------------------------------------
 
Function:
- Add & subtract unit for a processor ALU.
 
Instantiates:
- (4x) vector_sr.v
 
Notes:
- IN/MID/OUT/FLG optionally registered.
 
--------------------------------------------------------------------------------
*/
 
module alu_add_sub
        #(
        parameter       integer                                                 REGS_IN                 = 1,            // in register option
        parameter       integer                                                 REGS_MID                        = 1,            // mid register option
        parameter       integer                                                 REGS_OUT                        = 1,            // out register option
        parameter       integer                                                 REGS_FLG                        = 1,            // flag register option
        parameter       integer                                                 DATA_W                  = 3             // data width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire                                                            sgn_i,                                          // 1=signed
        input                   wire                                                            ext_i,                                          // 1=extended result
        input                   wire                                                            sub_i,                                          // 1=subtract; 0=add
        // data I/O
        input                   wire    [DATA_W-1:0]                     a_i,                                                    // operand
        input                   wire    [DATA_W-1:0]                     b_i,                                                    // operand
        output          wire    [DATA_W-1:0]                     result_o,                                       // = ( a +/- b )
        // flags
        output          wire                                                            ltz_o,                                          //      a < 0
        output          wire                                                            lt_o                                                    //      a < b
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        localparam      integer                                                 ZSX_W                           = DATA_W+1;  // +1 extra bit
        localparam      integer                                                 ADD_W                           = DATA_W+2;  // +2 extra bits
        localparam      integer                                                 DBL_W                           = DATA_W*2;  // double width
        //
        wire                                                                                            sgn, sub, ext, sub_r, ext_r;
        wire    signed          [DATA_W-1:0]                     a, b;
        wire    signed          [ZSX_W-1:0]                              a_zsx, b_zsx;
        wire    signed          [ADD_W-1:0]                              ab_add, ab_sub, ab_add_r, ab_sub_r;
        reg     signed          [DBL_W-1:0]                              res_dbl;
        reg     signed          [DATA_W-1:0]                     result;
        wire                                                                                            ltz, lt;
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // optional input regs
        vector_sr
        #(
        .REGS                   ( REGS_IN ),
        .DATA_W         ( DATA_W+DATA_W+3 ),
        .RESET_VAL      ( 0 )
        )
        in_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { a_i, b_i, sub_i, ext_i, sgn_i } ),
        .data_o         ( { a,   b,   sub,   ext,   sgn } )
        );
 
 
        // zero|sign extend results
        assign a_zsx = { ( sgn & a[DATA_W-1] ), a };
        assign b_zsx = { ( sgn & b[DATA_W-1] ), b };
 
        // arithmetic results (signed)
        assign ab_add = a_zsx + b_zsx;
        assign ab_sub = a_zsx - b_zsx;
 
        // flags
        assign ltz = a[DATA_W-1];
        assign lt = ab_sub[ZSX_W-1];
 
 
        // optional flag regs
        vector_sr
        #(
        .REGS                   ( REGS_FLG ),
        .DATA_W         ( 2 ),
        .RESET_VAL      ( 0 )
        )
        regs_flags
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { ltz,   lt } ),
        .data_o         ( { ltz_o, lt_o } )
        );
 
 
        // optional mid regs
        vector_sr
        #(
        .REGS                   ( REGS_MID ),
        .DATA_W         ( ADD_W+ADD_W+2 ),
        .RESET_VAL      ( 0 )
        )
        mid_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { ab_sub,   ab_add,   sub,   ext } ),
        .data_o         ( { ab_sub_r, ab_add_r, sub_r, ext_r } )
        );
 
 
        // multiplex
        always @ ( * ) begin
                case ( sub_r )
                        'b0 : res_dbl <= ab_add_r;
                        'b1 : res_dbl <= ab_sub_r;
                endcase
        end
 
        // multiplex & extend
        always @ ( * ) begin
                case ( ext_r )
                        'b0 : result <= res_dbl[DATA_W-1:0];
                        'b1 : result <= res_dbl[DBL_W-1:DATA_W];
                endcase
        end
 
 
        // optional output regs
        vector_sr
        #(
        .REGS                   ( REGS_OUT ),
        .DATA_W         ( DATA_W ),
        .RESET_VAL      ( 0 )
        )
        out_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( result ),
        .data_o         ( result_o )
        );
 
 
endmodule

Line No.	Rev	Author	Line
1	3	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : alu_add_sub.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Add & subtract unit for a processor ALU.`
10
11			`Instantiates:`
12			`- (4x) vector_sr.v`
13
14			`Notes:`
15			`- IN/MID/OUT/FLG optionally registered.`
16
17			`--------------------------------------------------------------------------------`
18			`*/`
19
20			`module alu_add_sub`
21			`#(`
22			`parameter integer REGS_IN = 1, // in register option`
23			`parameter integer REGS_MID = 1, // mid register option`
24			`parameter integer REGS_OUT = 1, // out register option`
25			`parameter integer REGS_FLG = 1, // flag register option`
26			`parameter integer DATA_W = 3 // data width`
27			`)`
28			`(`
29			`// clocks & resets`
30			`input wire clk_i, // clock`
31			`input wire rst_i, // async. reset, active high`
32			`// control I/O`
33			`input wire sgn_i, // 1=signed`
34			`input wire ext_i, // 1=extended result`
35			`input wire sub_i, // 1=subtract; 0=add`
36			`// data I/O`
37			`input wire [DATA_W-1:0] a_i, // operand`
38			`input wire [DATA_W-1:0] b_i, // operand`
39			`output wire [DATA_W-1:0] result_o, // = ( a +/- b )`
40			`// flags`
41			`output wire ltz_o, // a < 0`
42			`output wire lt_o // a < b`
43			`);`
44
45
46			`/*`
47			`----------------------`
48			`-- internal signals --`
49			`----------------------`
50			`*/`
51			`localparam integer ZSX_W = DATA_W+1; // +1 extra bit`
52			`localparam integer ADD_W = DATA_W+2; // +2 extra bits`
53			`localparam integer DBL_W = DATA_W*2; // double width`
54			`//`
55			`wire sgn, sub, ext, sub_r, ext_r;`
56			`wire signed [DATA_W-1:0] a, b;`
57			`wire signed [ZSX_W-1:0] a_zsx, b_zsx;`
58			`wire signed [ADD_W-1:0] ab_add, ab_sub, ab_add_r, ab_sub_r;`
59			`reg signed [DBL_W-1:0] res_dbl;`
60			`reg signed [DATA_W-1:0] result;`
61			`wire ltz, lt;`
62
63
64			`/*`
65			`================`
66			`== code start ==`
67			`================`
68			`*/`
69
70
71			`// optional input regs`
72			`vector_sr`
73			`#(`
74			`.REGS ( REGS_IN ),`
75			`.DATA_W ( DATA_W+DATA_W+3 ),`
76			`.RESET_VAL ( 0 )`
77			`)`
78			`in_regs`
79			`(`
80			`.clk_i ( clk_i ),`
81			`.rst_i ( rst_i ),`
82			`.data_i ( { a_i, b_i, sub_i, ext_i, sgn_i } ),`
83			`.data_o ( { a, b, sub, ext, sgn } )`
84			`);`
85
86
87			`// zero\|sign extend results`
88			`assign a_zsx = { ( sgn & a[DATA_W-1] ), a };`
89			`assign b_zsx = { ( sgn & b[DATA_W-1] ), b };`
90
91			`// arithmetic results (signed)`
92			`assign ab_add = a_zsx + b_zsx;`
93			`assign ab_sub = a_zsx - b_zsx;`
94
95			`// flags`
96			`assign ltz = a[DATA_W-1];`
97			`assign lt = ab_sub[ZSX_W-1];`
98
99
100			`// optional flag regs`
101			`vector_sr`
102			`#(`
103			`.REGS ( REGS_FLG ),`
104			`.DATA_W ( 2 ),`
105			`.RESET_VAL ( 0 )`
106			`)`
107			`regs_flags`
108			`(`
109			`.clk_i ( clk_i ),`
110			`.rst_i ( rst_i ),`
111			`.data_i ( { ltz, lt } ),`
112			`.data_o ( { ltz_o, lt_o } )`
113			`);`
114
115
116			`// optional mid regs`
117			`vector_sr`
118			`#(`
119			`.REGS ( REGS_MID ),`
120			`.DATA_W ( ADD_W+ADD_W+2 ),`
121			`.RESET_VAL ( 0 )`
122			`)`
123			`mid_regs`
124			`(`
125			`.clk_i ( clk_i ),`
126			`.rst_i ( rst_i ),`
127			`.data_i ( { ab_sub, ab_add, sub, ext } ),`
128			`.data_o ( { ab_sub_r, ab_add_r, sub_r, ext_r } )`
129			`);`
130
131
132			`// multiplex`
133			`always @ ( * ) begin`
134			`case ( sub_r )`
135			`'b0 : res_dbl <= ab_add_r;`
136			`'b1 : res_dbl <= ab_sub_r;`
137			`endcase`
138			`end`
139
140			`// multiplex & extend`
141			`always @ ( * ) begin`
142			`case ( ext_r )`
143			`'b0 : result <= res_dbl[DATA_W-1:0];`
144			`'b1 : result <= res_dbl[DBL_W-1:DATA_W];`
145			`endcase`
146			`end`
147
148
149			`// optional output regs`
150			`vector_sr`
151			`#(`
152			`.REGS ( REGS_OUT ),`
153			`.DATA_W ( DATA_W ),`
154			`.RESET_VAL ( 0 )`
155			`)`
156			`out_regs`
157			`(`
158			`.clk_i ( clk_i ),`
159			`.rst_i ( rst_i ),`
160			`.data_i ( result ),`
161			`.data_o ( result_o )`
162			`);`
163
164
165			`endmodule`

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[/] [hive/] [trunk/] [v01.10/] [alu_add_sub.v] - Blame information for rev 3