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[/] [hive/] [trunk/] [v01.10/] [alu_logical.v] - Blame information for rev 3

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/*
--------------------------------------------------------------------------------
 
Module : alu_logical.v
 
--------------------------------------------------------------------------------
 
Function:
- Logic unit for a processor ALU.
 
Instantiates:
- (4x) vector_sr.v
 
Notes:
- IN/MID/OUT/FLG optionally registered.
- lg_i / result_o decode:
 
 lg   result
---   --
 00   a and b
 01   a or b
 10   a xor b
 11   not( b )
 
 lg   result (ext)
---   -----
 00   and( b ) bit reduction
 01   or( b ) bit reduction
 1x   xor( b ) bit reduction
 
--------------------------------------------------------------------------------
*/
 
module alu_logical
        #(
        parameter       integer                                                 REGS_IN                 = 1,            // register option for inputs
        parameter       integer                                                 REGS_MID                        = 1,            // mid register option
        parameter       integer                                                 REGS_OUT                        = 1,            // register option for outputs
        parameter       integer                                                 REGS_FLG                        = 1,            // register option for flag outputs
        parameter       integer                                                 DATA_W                  = 2,            // data width
        parameter       integer                                                 LG_W                            = 2             // operation width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire                                                            ext_i,                                          // 1=extended result
        input                   wire    [LG_W-1:0]                               lg_i,                                                   // see decode in notes above
        // data I/O
        input                   wire    [DATA_W-1:0]                     a_i,                                                    // operand
        input                   wire    [DATA_W-1:0]                     b_i,                                                    // operand
        output          wire    [DATA_W-1:0]                     result_o,                                       // logical result
        // flags
        output          wire                                                            nez_o,                                          //      a != 0
        output          wire                                                            ne_o                                                    //      a != b
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                                                                            ext, ext_r;
        wire                                    [LG_W-1:0]                               lg;
        wire                                    [DATA_W-1:0]                     a, b;
        reg                                     [DATA_W-1:0]                     res;
        wire                                    [DATA_W-1:0]                     res_r;
        reg                                                                                             res_bit;
        wire                                                                                            res_bit_r;
        reg                                     [DATA_W-1:0]                     result;
        wire                                    [DATA_W-1:0]                     a_xor_b;
        wire                                                                                            nez, ne;
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // optional input registers
        vector_sr
        #(
        .REGS                   ( REGS_IN ),
        .DATA_W         ( DATA_W+DATA_W+LG_W+1 ),
        .RESET_VAL      ( 0 )
        )
        in_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { a_i, b_i, lg_i, ext_i } ),
        .data_o         ( { a,   b,   lg,   ext } )
        );
 
 
        // some intermediate results
        assign a_xor_b = a ^ b;
 
        // flags
        assign nez = |a;
        assign ne = |a_xor_b;
 
        // multiplex results
        always @ ( * ) begin
                case ( lg )
                        'b00 : res <= a & b;
                        'b01 : res <= a | b;
                        'b10 : res <= a_xor_b;
                        'b11 : res <= ~b;
                endcase
        end
 
        // multiplex results
        always @ ( * ) begin
                casex ( lg )
                        'b00 : res_bit <= &b;
                        'b01 : res_bit <= |b;
                        'b1x : res_bit <= ^b;
                endcase
        end
 
 
        // optional flag regs
        vector_sr
        #(
        .REGS                   ( REGS_FLG ),
        .DATA_W         ( 2 ),
        .RESET_VAL      ( 0 )
        )
        regs_flags
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { nez,   ne } ),
        .data_o         ( { nez_o, ne_o } )
        );
 
 
        // optional mid regs
        vector_sr
        #(
        .REGS                   ( REGS_MID ),
        .DATA_W         ( DATA_W+2 ),
        .RESET_VAL      ( 0 )
        )
        mid_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { res,   res_bit,   ext } ),
        .data_o         ( { res_r, res_bit_r, ext_r } )
        );
 
 
        // multiplex
        always @ ( * ) begin
                case ( ext_r )
                        'b0 : result <= res_r;
                        'b1 : result <= { DATA_W{ res_bit_r } };
                endcase
        end
 
 
        // optional output regs
        vector_sr
        #(
        .REGS                   ( REGS_OUT ),
        .DATA_W         ( DATA_W ),
        .RESET_VAL      ( 0 )
        )
        out_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( result ),
        .data_o         ( result_o )
        );
 
 
endmodule

Line No.	Rev	Author	Line
1	3	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : alu_logical.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Logic unit for a processor ALU.`
10
11			`Instantiates:`
12			`- (4x) vector_sr.v`
13
14			`Notes:`
15			`- IN/MID/OUT/FLG optionally registered.`
16			`- lg_i / result_o decode:`
17
18			`lg result`
19			`--- --`
20			`00 a and b`
21			`01 a or b`
22			`10 a xor b`
23			`11 not( b )`
24
25			`lg result (ext)`
26			`--- -----`
27			`00 and( b ) bit reduction`
28			`01 or( b ) bit reduction`
29			`1x xor( b ) bit reduction`
30
31			`--------------------------------------------------------------------------------`
32			`*/`
33
34			`module alu_logical`
35			`#(`
36			`parameter integer REGS_IN = 1, // register option for inputs`
37			`parameter integer REGS_MID = 1, // mid register option`
38			`parameter integer REGS_OUT = 1, // register option for outputs`
39			`parameter integer REGS_FLG = 1, // register option for flag outputs`
40			`parameter integer DATA_W = 2, // data width`
41			`parameter integer LG_W = 2 // operation width`
42			`)`
43			`(`
44			`// clocks & resets`
45			`input wire clk_i, // clock`
46			`input wire rst_i, // async. reset, active high`
47			`// control I/O`
48			`input wire ext_i, // 1=extended result`
49			`input wire [LG_W-1:0] lg_i, // see decode in notes above`
50			`// data I/O`
51			`input wire [DATA_W-1:0] a_i, // operand`
52			`input wire [DATA_W-1:0] b_i, // operand`
53			`output wire [DATA_W-1:0] result_o, // logical result`
54			`// flags`
55			`output wire nez_o, // a != 0`
56			`output wire ne_o // a != b`
57			`);`
58
59
60			`/*`
61			`----------------------`
62			`-- internal signals --`
63			`----------------------`
64			`*/`
65			`wire ext, ext_r;`
66			`wire [LG_W-1:0] lg;`
67			`wire [DATA_W-1:0] a, b;`
68			`reg [DATA_W-1:0] res;`
69			`wire [DATA_W-1:0] res_r;`
70			`reg res_bit;`
71			`wire res_bit_r;`
72			`reg [DATA_W-1:0] result;`
73			`wire [DATA_W-1:0] a_xor_b;`
74			`wire nez, ne;`
75
76
77			`/*`
78			`================`
79			`== code start ==`
80			`================`
81			`*/`
82
83
84			`// optional input registers`
85			`vector_sr`
86			`#(`
87			`.REGS ( REGS_IN ),`
88			`.DATA_W ( DATA_W+DATA_W+LG_W+1 ),`
89			`.RESET_VAL ( 0 )`
90			`)`
91			`in_regs`
92			`(`
93			`.clk_i ( clk_i ),`
94			`.rst_i ( rst_i ),`
95			`.data_i ( { a_i, b_i, lg_i, ext_i } ),`
96			`.data_o ( { a, b, lg, ext } )`
97			`);`
98
99
100			`// some intermediate results`
101			`assign a_xor_b = a ^ b;`
102
103			`// flags`
104			`assign nez = \|a;`
105			`assign ne = \|a_xor_b;`
106
107			`// multiplex results`
108			`always @ ( * ) begin`
109			`case ( lg )`
110			`'b00 : res <= a & b;`
111			`'b01 : res <= a \| b;`
112			`'b10 : res <= a_xor_b;`
113			`'b11 : res <= ~b;`
114			`endcase`
115			`end`
116
117			`// multiplex results`
118			`always @ ( * ) begin`
119			`casex ( lg )`
120			`'b00 : res_bit <= &b;`
121			`'b01 : res_bit <= \|b;`
122			`'b1x : res_bit <= ^b;`
123			`endcase`
124			`end`
125
126
127			`// optional flag regs`
128			`vector_sr`
129			`#(`
130			`.REGS ( REGS_FLG ),`
131			`.DATA_W ( 2 ),`
132			`.RESET_VAL ( 0 )`
133			`)`
134			`regs_flags`
135			`(`
136			`.clk_i ( clk_i ),`
137			`.rst_i ( rst_i ),`
138			`.data_i ( { nez, ne } ),`
139			`.data_o ( { nez_o, ne_o } )`
140			`);`
141
142
143			`// optional mid regs`
144			`vector_sr`
145			`#(`
146			`.REGS ( REGS_MID ),`
147			`.DATA_W ( DATA_W+2 ),`
148			`.RESET_VAL ( 0 )`
149			`)`
150			`mid_regs`
151			`(`
152			`.clk_i ( clk_i ),`
153			`.rst_i ( rst_i ),`
154			`.data_i ( { res, res_bit, ext } ),`
155			`.data_o ( { res_r, res_bit_r, ext_r } )`
156			`);`
157
158
159			`// multiplex`
160			`always @ ( * ) begin`
161			`case ( ext_r )`
162			`'b0 : result <= res_r;`
163			`'b1 : result <= { DATA_W{ res_bit_r } };`
164			`endcase`
165			`end`
166
167
168			`// optional output regs`
169			`vector_sr`
170			`#(`
171			`.REGS ( REGS_OUT ),`
172			`.DATA_W ( DATA_W ),`
173			`.RESET_VAL ( 0 )`
174			`)`
175			`out_regs`
176			`(`
177			`.clk_i ( clk_i ),`
178			`.rst_i ( rst_i ),`
179			`.data_i ( result ),`
180			`.data_o ( result_o )`
181			`);`
182
183
184			`endmodule`

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[/] [hive/] [trunk/] [v01.10/] [alu_logical.v] - Blame information for rev 3