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[/] [hive/] [trunk/] [v01.10/] [alu_mux.v] - Blame information for rev 3

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/*
--------------------------------------------------------------------------------
 
Module : alu_mux.v
 
--------------------------------------------------------------------------------
 
Function:
- Multiplexer for processor ALU.
 
Instantiates:
- (4x) vector_sr.v
 
Notes:
- I/M/O optionally registered.
 
--------------------------------------------------------------------------------
*/
 
module alu_mux
        #(
        parameter       integer                                                 REGS_IN_A               = 0,             // reg option input to mux a
        parameter       integer                                                 REGS_A_B                        = 0,             // reg option mux a to mux b
        parameter       integer                                                 REGS_B_C                        = 0,             // reg option mux b to mux c
        parameter       integer                                                 REGS_C_D                        = 0,             // reg option mux c to mux d
        parameter       integer                                                 REGS_D_OUT              = 0,             // reg option mux d to output
        parameter       integer                                                 DATA_W                  = 8,            // data width
        parameter       integer                                                 ADDR_W                  = 4             // address width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire                                                            sgn_i,                                          // 1=signed
        input                   wire                                                            ext_i,                                          // 1=extended
        input                   wire                                                            as_i,                                                   // 1=add/subtract
        input                   wire                                                            dm_i,                                                   // 1=read data
        input                   wire                                                            rtn_i,                                          // 1=return pc
        input                   wire                                                            ms_i,                                                   // 1=multiply
        // data I/O
        input                   wire    [DATA_W/2-1:0]                   a_lo_i,                                         // operand
        input                   wire    [DATA_W-1:0]                     res_lg_i,                                       // logical result
        input                   wire    [DATA_W-1:0]                     res_as_i,                                       // add/subtract result
        input                   wire    [DATA_W-1:0]                     res_ms_i,                                       // multiply/shift result
        input                   wire    [DATA_W/2-1:0]                   dm_data_i,                                      // dmem read data
        input                   wire    [ADDR_W-1:0]                     pc_i,                                                   // program counter
        output          wire    [DATA_W-1:0]                     result_o                                                // selected result
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                                                                            ms_a, rtn_a, dm_a, as_a, ext_a, sgn_a;
        wire                                                                                            ms_b, rtn_b, dm_b, as_b, ext_b, sgn_b;
        wire                                                                                            ms_c, dm_c, as_c, ext_c, sgn_c;
        wire                                                                                            ms_d;
        wire                                    [DATA_W/2-1:0]                   a_lo_a;
        reg                                     [DATA_W-1:0]                     mux_a, mux_b, mux_c, mux_d;
        wire                                    [DATA_W-1:0]                     mux_a_b, mux_b_c, mux_c_d;
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // input to mux a regs
        vector_sr
        #(
        .REGS                   ( REGS_IN_A ),
        .DATA_W         ( DATA_W/2+6 ),
        .RESET_VAL      ( 0 )
        )
        in_a_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { a_lo_i, ms_i, rtn_i, dm_i, as_i, ext_i, sgn_i } ),
        .data_o         ( { a_lo_a, ms_a, rtn_a, dm_a, as_a, ext_a, sgn_a } )
        );
 
 
        // mux a
        always @ ( * ) begin
                casex ( { dm_a, as_a } )
                        'b00 : mux_a <= res_lg_i;
                        'b01 : mux_a <= res_as_i;
                        'b1x : mux_a <= a_lo_a;
                endcase
        end
 
 
        // mux a to mux b regs
        vector_sr
        #(
        .REGS                   ( REGS_A_B ),
        .DATA_W         ( DATA_W+5 ),
        .RESET_VAL      ( 0 )
        )
        a_b_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { mux_a,   ms_a, rtn_a, dm_a, ext_a, sgn_a } ),
        .data_o         ( { mux_a_b, ms_b, rtn_b, dm_b, ext_b, sgn_b } )
        );
 
 
        // mux b
        always @ ( * ) begin
                case ( rtn_b )
                        'b0 : mux_b <= mux_a_b;
                        'b1 : mux_b <= pc_i;
                endcase
        end
 
 
        // mux b to mux c regs
        vector_sr
        #(
        .REGS                   ( REGS_B_C ),
        .DATA_W         ( DATA_W+4 ),
        .RESET_VAL      ( 0 )
        )
        b_c_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { mux_b,   ms_b, dm_b, ext_b, sgn_b } ),
        .data_o         ( { mux_b_c, ms_c, dm_c, ext_c, sgn_c } )
        );
 
 
        // mux c
        always @ ( * ) begin
                casex ( { dm_c, ext_c, sgn_c } )
                        'b0xx : mux_c <= mux_b_c;
                        'b100 : mux_c <= dm_data_i;
                        'b101 : mux_c <= $signed( dm_data_i );
                        'b11x : mux_c <= { dm_data_i, mux_b_c[DATA_W/2-1:0] };
                endcase
        end
 
 
        // mux c to mux d regs
        vector_sr
        #(
        .REGS                   ( REGS_C_D ),
        .DATA_W         ( DATA_W+1 ),
        .RESET_VAL      ( 0 )
        )
        c_d_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { mux_c,   ms_c } ),
        .data_o         ( { mux_c_d, ms_d } )
        );
 
 
        // mux c
        always @ ( * ) begin
                case ( ms_d )
                        'b0 : mux_d <= mux_c_d;
                        'b1 : mux_d <= res_ms_i;
                endcase
        end
 
 
        // mux d to output regs
        vector_sr
        #(
        .REGS                   ( REGS_D_OUT ),
        .DATA_W         ( DATA_W ),
        .RESET_VAL      ( 0 )
        )
        d_out_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( mux_d ),
        .data_o         ( result_o )
        );
 
 
endmodule

Line No.	Rev	Author	Line
1	3	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : alu_mux.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Multiplexer for processor ALU.`
10
11			`Instantiates:`
12			`- (4x) vector_sr.v`
13
14			`Notes:`
15			`- I/M/O optionally registered.`
16
17			`--------------------------------------------------------------------------------`
18			`*/`
19
20			`module alu_mux`
21			`#(`
22			`parameter integer REGS_IN_A = 0, // reg option input to mux a`
23			`parameter integer REGS_A_B = 0, // reg option mux a to mux b`
24			`parameter integer REGS_B_C = 0, // reg option mux b to mux c`
25			`parameter integer REGS_C_D = 0, // reg option mux c to mux d`
26			`parameter integer REGS_D_OUT = 0, // reg option mux d to output`
27			`parameter integer DATA_W = 8, // data width`
28			`parameter integer ADDR_W = 4 // address width`
29			`)`
30			`(`
31			`// clocks & resets`
32			`input wire clk_i, // clock`
33			`input wire rst_i, // async. reset, active high`
34			`// control I/O`
35			`input wire sgn_i, // 1=signed`
36			`input wire ext_i, // 1=extended`
37			`input wire as_i, // 1=add/subtract`
38			`input wire dm_i, // 1=read data`
39			`input wire rtn_i, // 1=return pc`
40			`input wire ms_i, // 1=multiply`
41			`// data I/O`
42			`input wire [DATA_W/2-1:0] a_lo_i, // operand`
43			`input wire [DATA_W-1:0] res_lg_i, // logical result`
44			`input wire [DATA_W-1:0] res_as_i, // add/subtract result`
45			`input wire [DATA_W-1:0] res_ms_i, // multiply/shift result`
46			`input wire [DATA_W/2-1:0] dm_data_i, // dmem read data`
47			`input wire [ADDR_W-1:0] pc_i, // program counter`
48			`output wire [DATA_W-1:0] result_o // selected result`
49			`);`
50
51
52			`/*`
53			`----------------------`
54			`-- internal signals --`
55			`----------------------`
56			`*/`
57			`wire ms_a, rtn_a, dm_a, as_a, ext_a, sgn_a;`
58			`wire ms_b, rtn_b, dm_b, as_b, ext_b, sgn_b;`
59			`wire ms_c, dm_c, as_c, ext_c, sgn_c;`
60			`wire ms_d;`
61			`wire [DATA_W/2-1:0] a_lo_a;`
62			`reg [DATA_W-1:0] mux_a, mux_b, mux_c, mux_d;`
63			`wire [DATA_W-1:0] mux_a_b, mux_b_c, mux_c_d;`
64
65
66			`/*`
67			`================`
68			`== code start ==`
69			`================`
70			`*/`
71
72
73			`// input to mux a regs`
74			`vector_sr`
75			`#(`
76			`.REGS ( REGS_IN_A ),`
77			`.DATA_W ( DATA_W/2+6 ),`
78			`.RESET_VAL ( 0 )`
79			`)`
80			`in_a_regs`
81			`(`
82			`.clk_i ( clk_i ),`
83			`.rst_i ( rst_i ),`
84			`.data_i ( { a_lo_i, ms_i, rtn_i, dm_i, as_i, ext_i, sgn_i } ),`
85			`.data_o ( { a_lo_a, ms_a, rtn_a, dm_a, as_a, ext_a, sgn_a } )`
86			`);`
87
88
89			`// mux a`
90			`always @ ( * ) begin`
91			`casex ( { dm_a, as_a } )`
92			`'b00 : mux_a <= res_lg_i;`
93			`'b01 : mux_a <= res_as_i;`
94			`'b1x : mux_a <= a_lo_a;`
95			`endcase`
96			`end`
97
98
99			`// mux a to mux b regs`
100			`vector_sr`
101			`#(`
102			`.REGS ( REGS_A_B ),`
103			`.DATA_W ( DATA_W+5 ),`
104			`.RESET_VAL ( 0 )`
105			`)`
106			`a_b_regs`
107			`(`
108			`.clk_i ( clk_i ),`
109			`.rst_i ( rst_i ),`
110			`.data_i ( { mux_a, ms_a, rtn_a, dm_a, ext_a, sgn_a } ),`
111			`.data_o ( { mux_a_b, ms_b, rtn_b, dm_b, ext_b, sgn_b } )`
112			`);`
113
114
115			`// mux b`
116			`always @ ( * ) begin`
117			`case ( rtn_b )`
118			`'b0 : mux_b <= mux_a_b;`
119			`'b1 : mux_b <= pc_i;`
120			`endcase`
121			`end`
122
123
124			`// mux b to mux c regs`
125			`vector_sr`
126			`#(`
127			`.REGS ( REGS_B_C ),`
128			`.DATA_W ( DATA_W+4 ),`
129			`.RESET_VAL ( 0 )`
130			`)`
131			`b_c_regs`
132			`(`
133			`.clk_i ( clk_i ),`
134			`.rst_i ( rst_i ),`
135			`.data_i ( { mux_b, ms_b, dm_b, ext_b, sgn_b } ),`
136			`.data_o ( { mux_b_c, ms_c, dm_c, ext_c, sgn_c } )`
137			`);`
138
139
140			`// mux c`
141			`always @ ( * ) begin`
142			`casex ( { dm_c, ext_c, sgn_c } )`
143			`'b0xx : mux_c <= mux_b_c;`
144			`'b100 : mux_c <= dm_data_i;`
145			`'b101 : mux_c <= $signed( dm_data_i );`
146			`'b11x : mux_c <= { dm_data_i, mux_b_c[DATA_W/2-1:0] };`
147			`endcase`
148			`end`
149
150
151			`// mux c to mux d regs`
152			`vector_sr`
153			`#(`
154			`.REGS ( REGS_C_D ),`
155			`.DATA_W ( DATA_W+1 ),`
156			`.RESET_VAL ( 0 )`
157			`)`
158			`c_d_regs`
159			`(`
160			`.clk_i ( clk_i ),`
161			`.rst_i ( rst_i ),`
162			`.data_i ( { mux_c, ms_c } ),`
163			`.data_o ( { mux_c_d, ms_d } )`
164			`);`
165
166
167			`// mux c`
168			`always @ ( * ) begin`
169			`case ( ms_d )`
170			`'b0 : mux_d <= mux_c_d;`
171			`'b1 : mux_d <= res_ms_i;`
172			`endcase`
173			`end`
174
175
176			`// mux d to output regs`
177			`vector_sr`
178			`#(`
179			`.REGS ( REGS_D_OUT ),`
180			`.DATA_W ( DATA_W ),`
181			`.RESET_VAL ( 0 )`
182			`)`
183			`d_out_regs`
184			`(`
185			`.clk_i ( clk_i ),`
186			`.rst_i ( rst_i ),`
187			`.data_i ( mux_d ),`
188			`.data_o ( result_o )`
189			`);`
190
191
192			`endmodule`

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[/] [hive/] [trunk/] [v01.10/] [alu_mux.v] - Blame information for rev 3