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[/] [hive/] [trunk/] [v01.10/] [alu_top.v] - Blame information for rev 3

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1 3 ericw
/*
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--------------------------------------------------------------------------------
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Module : alu_top.v
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--------------------------------------------------------------------------------
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Function:
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- Processor ALU top level.
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Instantiates:
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- (2x) vector_sr.v
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- (1x) alu_logical.v
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  - (4x) vector_sr.v
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- (1x) alu_add_sub.v
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  - (4x) vector_sr.v
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- (1x) alu_mult_shift.v
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  - (3x) vector_sr.v
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  - (1x) alu_multiply.v
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    - (1x) vector_sr.v (debug mode only)
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- (1x) alu_mux.v
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  - (4x) vector_sr.v
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Notes:
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- I/O optionally registered.
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- 5 stage pipeline w/ 4 mid registers (not counting I/O registering).
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--------------------------------------------------------------------------------
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*/
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module alu_top
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        #(
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        parameter       integer                                                 REGS_IN                 = 1,            // register option for control and a & b inputs
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        parameter       integer                                                 REGS_OUT                        = 1,            // register option for outputs
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        parameter       integer                                                 REGS_FLG                        = 1,            // register option for flag outputs
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        parameter       integer                                                 DATA_W                  = 32,           // data width
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        parameter       integer                                                 ADDR_W                  = 16,           // address width
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        parameter       integer                                                 LG_W                            = 2             // operation width
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        )
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        (
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        // clocks & resets
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        input                   wire                                                            clk_i,                                          // clock
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        input                   wire                                                            rst_i,                                          // async. reset, active high
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        // control I/O
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        input                   wire                                                            sgn_i,                                          // 1=signed
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        input                   wire                                                            ext_i,                                          // 1=extended result
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        input                   wire    [LG_W-1:0]                               lg_i,                                                   // see decode in notes above
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        input                   wire                                                            add_i,                                          // 1=add
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        input                   wire                                                            sub_i,                                          // 1=subtract
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        input                   wire                                                            mul_i,                                          // 1=multiply
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        input                   wire                                                            shl_i,                                          // 1=shift left
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        input                   wire                                                            cpy_i,                                          // 1=copy b
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        input                   wire                                                            dm_i,                                                   // 1=data mem
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        input                   wire                                                            rtn_i,                                          // 1=return pc
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        // data I/O
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        input                   wire    [DATA_W-1:0]                     a_i,                                                    // operand
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        input                   wire    [DATA_W-1:0]                     b_i,                                                    // operand
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        input                   wire    [DATA_W/2-1:0]                   dm_data_i,                                      // dmem read data
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        input                   wire    [ADDR_W-1:0]                     pc_3_i,                                         // program counter
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        output          wire    [DATA_W-1:0]                     result_o,                                       // result
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        // flags
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        output          wire                                                            nez_o,                                          //      a != 0
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        output          wire                                                            ne_o,                                                   //      a != b
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        output          wire                                                            ltz_o,                                          //      a < 0
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        output          wire                                                            lt_o                                                    //      a < b
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        );
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        /*
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        ----------------------
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        -- internal signals --
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        ----------------------
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        */
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        wire                                                                                            rtn, dm, cpy, shl, mul, sub, add, ext, sgn;
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        wire                                    [LG_W-1:0]                               lg;
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        wire                                    [DATA_W-1:0]                     a, b;
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        wire                                    [DATA_W-1:0]                     res_lg, res_as, res_mid, res_ms;
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        /*
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        ================
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        == code start ==
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        ================
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        */
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        // optional input regs
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        vector_sr
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        #(
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        .REGS                   ( REGS_IN ),
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        .DATA_W         ( DATA_W+DATA_W+7+LG_W+2 ),
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        .RESET_VAL      ( 0 )
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        )
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        in_regs
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        (
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        .clk_i          ( clk_i ),
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        .rst_i          ( rst_i ),
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        .data_i         ( { a_i, b_i, rtn_i, dm_i, cpy_i, shl_i, mul_i, sub_i, add_i, lg_i, ext_i, sgn_i } ),
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        .data_o         ( { a,   b,   rtn,   dm,   cpy,   shl,   mul,   sub,   add,   lg,   ext,   sgn } )
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        );
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        // logical unit
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        alu_logical
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        #(
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        .REGS_IN                        ( 0 ),
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        .REGS_MID               ( 1 ),
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        .REGS_OUT               ( 0 ),
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        .REGS_FLG               ( REGS_FLG ),
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        .DATA_W                 ( DATA_W ),
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        .LG_W                           ( LG_W )
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        )
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        alu_logical
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .ext_i                  ( ext ),
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        .lg_i                           ( lg ),
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        .a_i                            ( a ),
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        .b_i                            ( b ),
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        .result_o               ( res_lg ),
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        .nez_o                  ( nez_o ),
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        .ne_o                           ( ne_o )
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        );
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        // add & subtract unit
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        alu_add_sub
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        #(
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        .REGS_IN                        ( 0 ),
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        .REGS_MID               ( 1 ),
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        .REGS_OUT               ( 0 ),
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        .REGS_FLG               ( REGS_FLG ),
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        .DATA_W                 ( DATA_W )
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        )
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        alu_add_sub
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .sgn_i                  ( sgn ),
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        .ext_i                  ( ext ),
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        .sub_i                  ( sub ),
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        .a_i                            ( a ),
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        .b_i                            ( b ),
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        .result_o               ( res_as ),
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        .ltz_o                  ( ltz_o ),
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        .lt_o                           ( lt_o )
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        );
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        // multiply & shift unit
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        alu_mult_shift
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        #(
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        .REGS_IN                        ( 0 ),
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        .REGS_OUT               ( 0 ),
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        .DATA_W                 ( DATA_W )
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        )
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        alu_mult_shift
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .sgn_i                  ( sgn ),
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        .ext_i                  ( ext ),
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        .shl_i                  ( shl ),
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        .cpy_i                  ( cpy ),
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        .a_i                            ( a ),
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        .b_i                            ( b ),
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        .result_o               ( res_ms )
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        );
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        // multiplexer
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        alu_mux
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        #(
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        .REGS_IN_A              ( 1 ),
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        .REGS_A_B               ( 1 ),
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        .REGS_B_C               ( 1 ),
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        .REGS_C_D               ( 1 ),
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        .REGS_D_OUT             ( REGS_OUT ),
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        .DATA_W                 ( DATA_W ),
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        .ADDR_W                 ( ADDR_W )
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        )
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        alu_mux
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .sgn_i                  ( sgn ),
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        .ext_i                  ( ext ),
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        .as_i                           ( sub | add ),
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        .dm_i                           ( dm ),
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        .rtn_i                  ( rtn ),
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        .ms_i                           ( cpy | shl | mul ),
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        .a_lo_i                 ( a[DATA_W/2-1:0] ),
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        .res_ms_i               ( res_ms ),
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        .res_lg_i               ( res_lg ),
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        .res_as_i               ( res_as ),
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        .dm_data_i              ( dm_data_i ),
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        .pc_i                           ( pc_3_i ),
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        .result_o               ( result_o )
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        );
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endmodule

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