OpenCores
URL https://opencores.org/ocsvn/hive/hive/trunk

Subversion Repositories hive

[/] [hive/] [trunk/] [v01.10/] [boot_code/] [boot_code_v_io.h] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 ericw 
/*
2 
--------------------------------------------------------------------------------
3 
 
4 
Module : boot_code.h
5 
 
6 
--------------------------------------------------------------------------------
7 
 
8 
Function:
9 
- Boot code for a processor core.
10 
 
11 
Instantiates:
12 
- Nothing.
13 
 
14 
Notes:
15 
- For testing (@ core.v):
16 
  CLR_BASE              = 'h0;
17 
  CLR_SPAN              = 2;  // gives 4 instructions
18 
  INTR_BASE             = 'h20;  // 'd32
19 
  INTR_SPAN             = 2;  // gives 4 instructions
20 
 
21 
 
22 
--------------------------------------------------------------------------------
23 
*/
24 
 
25 
        /*
26 
        -------------------------
27 
        -- external parameters --
28 
        -------------------------
29 
        */
30 
        `include "op_encode.h"
31 
        `include "reg_set_addr.h"
32 
 
33 
        /*
34 
        ------------------------------------------------------------
35 
        -- defines that make programming code more human readable --
36 
        ------------------------------------------------------------
37 
        */
38 
        `define s0                              2'd0
39 
        `define s1                              2'd1
40 
        `define s2                              2'd2
41 
        `define s3                              2'd3
42 
        `define _                               1'b0
43 
        `define P                               1'b1
44 
        //
45 
        `define op_rd_i         op_rd_i[9:4]
46 
        `define op_rd_ix                op_rd_ix[9:4]
47 
        //
48 
        `define op_jmp_iez      op_jmp_iez[9:5]
49 
        `define op_jmp_ilz      op_jmp_ilz[9:5]
50 
        `define op_jmp_ilez     op_jmp_ilez[9:5]
51 
        `define op_jmp_igz      op_jmp_igz[9:5]
52 
        `define op_jmp_igez     op_jmp_igez[9:5]
53 
        `define op_jmp_iglz     op_jmp_iglz[9:5]
54 
        `define op_jmp_i                op_jmp_i[9:5]
55 
        //
56 
        `define op_wr_i         op_wr_i[9:4]
57 
        `define op_wr_ix                op_wr_ix[9:4]
58 
        //
59 
        `define op_jmp_ie               op_jmp_ie[9:5]
60 
        `define op_jmp_il               op_jmp_il[9:5]
61 
        `define op_jmp_ile      op_jmp_ile[9:5]
62 
        `define op_jmp_iug      op_jmp_iug[9:5]
63 
        `define op_jmp_iuge     op_jmp_iuge[9:5]
64 
        `define op_jmp_igl      op_jmp_igl[9:5]
65 
        //
66 
        `define op_byt_i                op_byt_i[9:8]
67 
        //
68 
        `define op_shl_i                op_shl_i[9:6]
69 
        `define op_shl_iu               op_shl_iu[9:6]
70 
        `define op_add_i                op_add_i[9:6]
71 
 
72 
        /*
73 
        ----------------------------------------
74 
        -- initialize: fill with default data --
75 
        ----------------------------------------
76 
        */
77 
        integer i;
78 
 
79 
        initial begin
80 
 
81 
/*      // fill with nop (some compilers need this)
82 
        for ( i = 0; i < CAPACITY; i = i+1 ) begin
83 
                ram[i] = { op_nop, `_, `_, `s0, `s0 };
84 
        end
85 
*/
86 
 
87 
        /*
88 
        ---------------
89 
        -- boot code --
90 
        ---------------
91 
        */
92 
 
93 
 
94 
        // Thread 0 : test I/O functions
95 
        // All other threads : loop forever
96 
 
97 
        ///////////////
98 
        // clr space //
99 
        ///////////////
100 
 
101 
        // thread 0
102 
        i='h0;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
103 
        i=i+1;   ram[i] = 16'h100                                     ;  // addr
104 
        i=i+1;   ram[i] = {  op_gto,                `P, `_, `s2, `s0 };  // goto, pop s2 (addr)
105 
        // and the rest (are here on Gilligan's Isle)
106 
        i='h4;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
107 
        i=i+4;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
108 
        i=i+4;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
109 
        i=i+4;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
110 
        i=i+4;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
111 
        i=i+4;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
112 
        i=i+4;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
113 
 
114 
 
115 
        ////////////////
116 
        // intr space //
117 
        ////////////////
118 
 
119 
        ///////////////////////
120 
        // code & data space //
121 
        ///////////////////////
122 
 
123 
 
124 
        // test I/O functions, result in s0
125 
        // Correct functioning is s0 = 'd9 ('h9).
126 
        //
127 
        // s0 : final test result
128 
        // s1 : test value
129 
        // s2 : test value
130 
        // s3 : running test result, subroutine return address
131 
        //
132 
        // setup running test result:
133 
        i='h100; ram[i] = { `op_byt_i,        8'd0, `_, `_, `s0, `s3 };  // 0=>s3
134 
        // PC
135 
        i=i+1;   ram[i] = {  op_pc,                 `_, `_, `s0, `s1 };  // PC => s1
136 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s0 };  // lit => s0
137 
        i=i+1;   ram[i] = 16'h102                                     ;  // value
138 
        i=i+1;   ram[i] = { `op_jmp_ie,       5'd1, `P, `P, `s1, `s0 };  // (s0==s1) ? skip, pop both
139 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
140 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
141 
        // setup test value:
142 
        i=i+1;   ram[i] = {  op_lit,                `_, `_, `s1, `s1 };  // lit => s1
143 
        i=i+1;   ram[i] = 16'ha53c                                    ;  // lo data
144 
        i=i+1;   ram[i] = {  op_lit_x,              `_, `P, `s1, `s1 };  // lit => s1, pop combine
145 
        i=i+1;   ram[i] = 16'h36c9                                    ;  // hi data
146 
        // WR_IX & RD_IX
147 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
148 
        i=i+1;   ram[i] = 16'ha00                                     ;  // addr
149 
        i=i+1;   ram[i] = { `op_wr_i,         4'd0, `_, `_, `s2, `s1 };  // write s1=>(s2+offset)
150 
        i=i+1;   ram[i] = { `op_wr_ix,        4'd1, `_, `_, `s2, `s1 };  // write s1=>(s2+offset)
151 
        i=i+1;   ram[i] = { `op_rd_i,         4'd0, `_, `_, `s2, `s0 };  // read (s2+offset)=>s0
152 
        i=i+1;   ram[i] = { `op_rd_ix,        4'd1, `P, `P, `s2, `s0 };  // read (s2+offset)=>s0, pop both
153 
        i=i+1;   ram[i] = { `op_jmp_ie,       5'd1, `_, `P, `s1, `s0 };  // (s0==s1) ? skip, pop s0
154 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
155 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
156 
        // RD_I (signed)
157 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
158 
        i=i+1;   ram[i] = 16'ha00                                     ;  // addr
159 
        i=i+1;   ram[i] = { `op_wr_i,         4'd0, `_, `_, `s2, `s1 };  // write s1=>(s2+offset)
160 
        i=i+1;   ram[i] = { `op_rd_i,         4'd0, `P, `_, `s2, `s0 };  // read (s2+offset)=>s0, pop s2
161 
        i=i+1;   ram[i] = { `op_shl_i,       6'd16, `_, `_, `s1, `s1 };  // s1<<16=>s1
162 
        i=i+1;   ram[i] = { `op_shl_i,      -6'd16, `_, `P, `s1, `s1 };  // s1>>16=>s1, pop s1
163 
        i=i+1;   ram[i] = { `op_jmp_ie,       5'd1, `P, `P, `s1, `s0 };  // (s0==s1) ? skip, pop both
164 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
165 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
166 
        // RD_I (unsigned)
167 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
168 
        i=i+1;   ram[i] = 16'ha00                                     ;  // addr
169 
        i=i+1;   ram[i] = { `op_wr_ix,        4'd0, `_, `_, `s2, `s1 };  // write s1=>(s2+offset)
170 
        i=i+1;   ram[i] = { `op_rd_i,         4'd0, `P, `_, `s2, `s0 };  // read (s2+offset)=>s0, pop s2
171 
        i=i+1;   ram[i] = { `op_shl_iu,     -6'd16, `_, `_, `s1, `s1 };  // s1>>16=>s1
172 
        i=i+1;   ram[i] = { `op_jmp_ie,       5'd1, `P, `P, `s1, `s0 };  // (s0==s1) ? skip, pop both
173 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
174 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
175 
        // LIT (signed)
176 
        i=i+1;   ram[i] = {  op_lit,                `_, `_, `s0, `s0 };  // lit => s0
177 
        i=i+1;   ram[i] = 16'ha53c                                    ;  // lo data
178 
        i=i+1;   ram[i] = { `op_shl_i,       6'd16, `_, `_, `s1, `s1 };  // s1<<16=>s1
179 
        i=i+1;   ram[i] = { `op_shl_i,      -6'd16, `_, `P, `s1, `s1 };  // s1>>16=>s1, pop s1
180 
        i=i+1;   ram[i] = { `op_jmp_ie,       5'd1, `P, `P, `s1, `s0 };  // (s0==s1) ? skip, pop both
181 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
182 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
183 
        // LIT (unsigned)
184 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s0 };  // lit => s0
185 
        i=i+1;   ram[i] = 16'ha53c                                    ;  // lo data
186 
        i=i+1;   ram[i] = { `op_shl_i,       6'd16, `_, `_, `s1, `s1 };  // s1<<16=>s1
187 
        i=i+1;   ram[i] = { `op_shl_iu,     -6'd16, `_, `P, `s1, `s1 };  // s1>>16=>s1, pop s1
188 
        i=i+1;   ram[i] = { `op_jmp_ie,       5'd1, `P, `P, `s1, `s0 };  // (s0==s1) ? skip, pop both
189 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
190 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
191 
        // CPY
192 
        i=i+1;   ram[i] = {  op_cpy,                `_, `_, `s1, `s0 };  // s1=>s0
193 
        i=i+1;   ram[i] = { `op_jmp_ie,       5'd1, `_, `P, `s1, `s0 };  // (s0==s1) ? skip, pop s0
194 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
195 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
196 
        // check for no opcode errors
197 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
198 
        i=i+1;   ram[i] = 16'h900                                     ;  // addr
199 
        i=i+1;   ram[i] = {  op_gsb,                `P, `_, `s2, `s3 };  // gsb, pop s2 (addr)
200 
        i=i+1;   ram[i] = { `op_jmp_iez,      5'd1, `_, `P, `s0, `s0 };  // (s0==0) ? skip, pop s0
201 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
202 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
203 
        // check for no stack errors
204 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
205 
        i=i+1;   ram[i] = 16'h910                                     ;  // addr
206 
        i=i+1;   ram[i] = {  op_gsb,                `P, `_, `s2, `s3 };  // gsb, pop s2 (addr)
207 
        i=i+1;   ram[i] = { `op_jmp_iez,      5'd1, `_, `P, `s0, `s0 };  // (s0==0) ? skip, pop s0
208 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s3 };  // s3-1=>s3, pop s3
209 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s3 };  // s3+1=>s3, pop s3
210 
        // s3=>s0, loop forever
211 
        i=i+1;   ram[i] = {  op_cpy,                `P, `_, `s3, `s0 };  // s3=>s0, pop s3
212 
        i=i+1;   ram[i] = { `op_jmp_i,       -5'h1, `_, `_, `s0, `s0 };  // loop forever
213 
 
214 
 
215 
 
216 
 
217 
 
218 
        /////////////////
219 
        // subroutines //
220 
        /////////////////
221 
 
222 
 
223 
        // sub : read & clear opcode errors for this thread => s0, return to (s3)
224 
        i='h900; ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
225 
        i=i+1;   ram[i] = REG_BASE_ADDR                               ;  // reg base addr
226 
        i=i+1;   ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 };  // read (s2+offset)=>s0
227 
        i=i+1;   ram[i] = {  op_shl_u,              `_, `P, `s0, `s0 };  // 1<<s0=>s0, pop s0
228 
        i=i+1;   ram[i] = { `op_rd_i,   OP_ER_ADDR, `_, `_, `s2, `s3 };  // read (s2+offset)=>s3
229 
        i=i+1;   ram[i] = {  op_and,                `P, `P, `s3, `s0 };  // s0&s3=>s0, pop both
230 
        i=i+1;   ram[i] = { `op_wr_i,   OP_ER_ADDR, `P, `_, `s2, `s0 };  // write s0=>(s2+offset), pop s2
231 
        i=i+1;   ram[i] = {  op_gto,                `P, `_, `s3, `s0 };  // return to (s3), pop s3
232 
 
233 
 
234 
        // sub : read & clear stack errors for this thread => s0, return to (s3)
235 
        i='h910; ram[i] = {  op_lit_u,              `_, `_, `s0, `s2 };  // lit => s2
236 
        i=i+1;   ram[i] = REG_BASE_ADDR                               ;  // reg base addr
237 
        i=i+1;   ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 };  // read (s2+offset)=>s0
238 
        i=i+1;   ram[i] = {  op_shl_u,              `_, `P, `s0, `s0 };  // 1<<s0=>s0, pop s0
239 
        i=i+1;   ram[i] = {  op_cpy,                `_, `_, `s0, `s3 };  // s0=>s3
240 
        i=i+1;   ram[i] = { `op_shl_i,        6'd8, `_, `P, `s0, `s3 };  // s3<<8=>s3, pop s3
241 
        i=i+1;   ram[i] = {  op_or,                 `P, `P, `s3, `s0 };  // s0|s3=>s0, pop both
242 
        i=i+1;   ram[i] = { `op_rd_i,  STK_ER_ADDR, `_, `_, `s2, `s3 };  // read (s2+offset)=>s3
243 
        i=i+1;   ram[i] = {  op_and,                `P, `P, `s3, `s0 };  // s0&s3=>s0, pop both
244 
        i=i+1;   ram[i] = { `op_wr_i,  STK_ER_ADDR, `P, `_, `s2, `s0 };  // write s0=>(s2+offset), pop s2
245 
        i=i+1;   ram[i] = {  op_gto,                `P, `_, `s3, `s0 };  // return to (s3), pop s3
246 
 
247 
 
248 
 
249 
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.