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ericw |
/*
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--------------------------------------------------------------------------------
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Module : core.v
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--------------------------------------------------------------------------------
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Function:
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- Processor core with 8 stage pipeline, 8 threads, and 4 stacks per thread.
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Instantiates:
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- control_ring.v
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- data_ring.v
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- reg_set.v
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- reg_set_shim.v
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- dp_ram_infer.v
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--------------------
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- Revision History -
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--------------------
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v01.10 - 2013-07-06
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- Shuffled opcode encoding again:
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- Unused jmp_iz never houses rd_i ops.
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- Unused jmp_i never houses wr_i ops.
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- jmp_i always immediate field reduced to 5 bits for consistency,
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which leaves an unused 32 code gap.
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- Edited boot code tests to work with this new encoding.
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v01.09 (cont) - 2013-06-25
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- Passes boot code verification for:
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- All I/O ops.
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v01.09 - 2013-06-24
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- First public release.
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- Shuffled opcode encoding again:
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- Unused never jmp_i fits read/write perfectly.
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- Unused always jmp_i zero comparison allows for 1 bit immediate field
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expansion of jmp_i(gle/z).
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- Removed all skip instructions (redundant w/ jmp_i).
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- All the above allows add_i immediate field expansion to 6 bits.
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- Opcode encoding is now more straightforward with fewer immediate field sizes.
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- Worked on pc_ring.v and pointer_ring.v, now use simple loops rather than
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generate, the logic produced better tracks the module paramters.
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- Removed "skp" control bit from pc_ring.v, op_decode.v, control_ring.v.
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- Removed intr_ack_o from core I/O.
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- Renamed "register_set*" => "reg_set*".
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- (Considering adding a leading zero count opcode, it doesn't take many LEs.)
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- Seeing a write to thread 7 stack 0 memory at startup, don't think it
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means anything due to clearing.
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- Passes boot code verification for:
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- Interrupts.
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- Stack ops, depth, error reporting (all threads).
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- All branch / conditional ops.
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- All logical / arithmetic / shift ops.
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v01.08 - 2013-06-14
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- Added parameter options for stack pointer error protections & brought them
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to the top level.
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- The unsigned restoring division subroutine works!
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v01.07 - 2013-06-11
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- Changed opcodes to make swapping of (A?B) operands cover all logical needs:
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- op_skp_ul => op_skp_l
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- op_skp_ge => op_skp_uge
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- op_jmp_iul => op_jmp_il
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- op_jmp_ige => op_jmp_iuge
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- Changed verification boot code tests to reflect above (passes).
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v01.06 - 2013-06-10
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- Fixed latency of test fields in op_decode.v (were only registered 1x, s/b 2x).
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- Fixed subtle immediate address offset sign issue in pc_ring.v.
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- Fixed subtle immediate data sign issue in stacks_mux.v.
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- Minor style edits to visually align port names @ vector_sr.v instances.
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- The log2 subroutine works!
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v01.05 - 2013-06-07
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- Put the skip instructions back (for convenience & clarity).
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- Changes to op_decode.v, separate immediate data and address decodes,
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misc. edits to improve speed.
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- Renamed "op_codes.h" => "op_encode.h".
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- Lots of minor edits at the higher levels.
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- Added "copyright.txt" to directory.
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v01.04 - 2013-06-06
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- Added op_jmp_i (A?B) instructions.
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- Removed all skip instructions (redundant).
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v01.03 - 2013-06-04
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- Changed op_jmp_i to be conditional (A?0).
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- Renamed "addr_regs.h" => "register_set_addr.h".
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- New boot code does log2.
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v01.02 (cont) - 2013-05-23
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- Old boot code file renamed: "boot_code.h" => "boot_code_00.h".
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- New boot code file tests all op_codes and gives final report.
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v01.02 - 2013-05-22
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- Memory writes now work, the fix was to swap pc/op_code ROM side A with
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data RW side B of main memory "dp_ram_infer.v". It seems side A is
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incorrectly used as the master mode for both ports.
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- Renamed "alu_input_mux.v" => "stacks_mux.v".
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- Removed enable from "register_set.v" and "register_set_shim.v".
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- Monkeyed with "register_set_shim.v" a bit.
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- Removed async resets from "dp_ram_infer.v" and "dq_ram_infer.v".
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- Passes boot code tests 0, 1, 2, 3, 4.
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v01.01 - 2013-05-22
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- Added clear and interrupt BASE and SPAN parameters.
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- Because BASE is a simple MSB concatenation, for it to be effective
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make BASE >= 2^(THRD_W+SPAN). BASE LSBs below this point are ignored.
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- Individual clear and interrupt address interspacing = 2^SPAN.
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- Example:
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CLR_BASE ='h0 positions thread 0 clear @ 0.
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CLR_SPAN =2 positions thread 1 clear @ 4, thread 2 @ 8, etc.
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INTR_BASE='h20 positions thread 0 interrupt @ 'd32.
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INTR_SPAN=2 positions thread 1 interrupt @ 'd36, thread 2 @ 'd40, etc.
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- Moved most core top port parameters to localparam.
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- Modified boot code tests accordingly.
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- Passes boot code tests 0, 1, 2.
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- Memory writes still don't work!
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v01.00 - 2013-05-21 - born
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- EP3C5E144C8: ~180MHz, ~1785 LEs (34% of logic).
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- Fixed immediate value bug (was only registered 1x in op_decode.v, s/b 2x).
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- Passes boot code tests 0, 1, 2.
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- Memory writes don't work!
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--------------------------------------------------------------------------------
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*/
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module core
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#(
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parameter integer DATA_W = 32, // data width
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parameter integer THREADS = 8, // threads
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parameter [DATA_W/4-1:0] VER_MAJ = 'h01, // core version
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parameter [DATA_W/4-1:0] VER_MIN = 'h10 // core version
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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//
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input wire [THREADS-1:0] intr_req_i, // event request, active high
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//
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input wire [DATA_W-1:0] io_i, // gpio
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output wire [DATA_W-1:0] io_o
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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`include "functions.h" // for clog2()
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//
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localparam integer ADDR_W = 16; // address width
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localparam integer PNTR_W = 5; // stack pointer width
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localparam integer MEM_ADDR_W = 13; // main memory width
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localparam [ADDR_W-1:0] CLR_BASE = 'h0; // clear address base (concat)
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localparam integer CLR_SPAN = 2; // clear address span (2^n)
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localparam [ADDR_W-1:0] INTR_BASE = 'h20; // interrupt address base (concat)
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localparam integer INTR_SPAN = 2; // interrupt address span (2^n)
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localparam integer THRD_W = clog2( THREADS );
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localparam integer STACKS = 4; // number of stacks
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localparam integer STK_W = clog2( STACKS );
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localparam integer IM_DATA_W = 8; // immediate data width
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localparam integer IM_ADDR_W = 5; // immediate address width
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localparam integer LG_W = 2;
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localparam integer OP_CODE_W = DATA_W/2;
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localparam integer REG_ADDR_W = 4;
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localparam integer IM_RW_W = 4;
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localparam integer POP_PROT = 1; // 1=error protection, 0=none
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localparam integer PUSH_PROT = 1; // 1=error protection, 0=none
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//
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wire [THREADS-1:0] clr_req;
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wire [THREADS-1:0] intr_en;
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wire [OP_CODE_W-1:0] op_code;
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wire op_code_er;
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wire [STK_W-1:0] a_sel, b_sel;
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wire imda, sgn, ext;
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wire [LG_W-1:0] lg;
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wire add, sub, mul, shl, cpy, dm, rtn, rd, wr;
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wire stk_clr;
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wire [STACKS-1:0] pop, push, pop_er, push_er;
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wire [DATA_W-1:0] a, b;
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wire [IM_DATA_W-1:0] im_data;
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wire [IM_ADDR_W-1:0] im_addr;
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wire nez, ne, ltz, lt;
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wire [THRD_W-1:0] thrd_0, thrd_2, thrd_3, thrd_6;
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wire [ADDR_W-1:0] pc_1, pc_3, pc_4;
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wire [DATA_W/2-1:0] dm_rd_data;
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wire [DATA_W/2-1:0] rd_data, wr_data;
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wire [ADDR_W-1:0] addr;
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wire regs_wr, regs_rd, dm_wr;
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/*
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================
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== code start ==
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================
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*/
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// the control ring
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control_ring
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#(
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.DATA_W ( DATA_W ),
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.ADDR_W ( ADDR_W ),
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.THREADS ( THREADS ),
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.THRD_W ( THRD_W ),
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.STACKS ( STACKS ),
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.STK_W ( STK_W ),
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.IM_DATA_W ( IM_DATA_W ),
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.IM_ADDR_W ( IM_ADDR_W ),
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.OP_CODE_W ( OP_CODE_W ),
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.LG_W ( LG_W ),
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.CLR_BASE ( CLR_BASE ),
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.CLR_SPAN ( CLR_SPAN ),
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.INTR_BASE ( INTR_BASE ),
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.INTR_SPAN ( INTR_SPAN )
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)
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control_ring
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.clr_req_i ( clr_req ),
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.clr_ack_o ( ), // unused
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.intr_en_i ( intr_en ),
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.intr_req_i ( intr_req_i ),
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.intr_ack_o ( ), // unused
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.op_code_i ( op_code ),
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.op_code_er_o ( op_code_er ),
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.b_lo_i ( b[DATA_W/2-1:0] ),
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.im_data_o ( im_data ),
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.a_sel_o ( a_sel ),
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.b_sel_o ( b_sel ),
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.imda_o ( imda ),
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.sgn_o ( sgn ),
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.ext_o ( ext ),
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.lg_o ( lg ),
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.add_o ( add ),
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.sub_o ( sub ),
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.mul_o ( mul ),
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.shl_o ( shl ),
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.cpy_o ( cpy ),
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.dm_o ( dm ),
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.rtn_o ( rtn ),
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.rd_o ( rd ),
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.wr_o ( wr ),
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.stk_clr_o ( stk_clr ),
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.pop_o ( pop ),
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.push_o ( push ),
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.nez_i ( nez ),
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.ne_i ( ne ),
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.ltz_i ( ltz ),
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.lt_i ( lt ),
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.thrd_0_o ( thrd_0 ),
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.thrd_2_o ( thrd_2 ),
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.thrd_3_o ( thrd_3 ),
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.thrd_6_o ( thrd_6 ),
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.im_addr_o ( im_addr ),
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.pc_1_o ( pc_1 ),
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.pc_3_o ( pc_3 ),
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.pc_4_o ( pc_4 )
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);
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// the data ring
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data_ring
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#(
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.DATA_W ( DATA_W ),
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.ADDR_W ( ADDR_W ),
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.THREADS ( THREADS ),
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.THRD_W ( THRD_W ),
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.STACKS ( STACKS ),
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.STK_W ( STK_W ),
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.PNTR_W ( PNTR_W ),
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.IM_DATA_W ( IM_DATA_W ),
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.LG_W ( LG_W ),
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.POP_PROT ( POP_PROT ),
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.PUSH_PROT ( PUSH_PROT )
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)
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data_ring
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.a_sel_i ( a_sel ),
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.b_sel_i ( b_sel ),
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.imda_i ( imda ),
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.sgn_i ( sgn ),
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.ext_i ( ext ),
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.lg_i ( lg ),
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.add_i ( add ),
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.sub_i ( sub ),
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.mul_i ( mul ),
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.shl_i ( shl ),
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.cpy_i ( cpy ),
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.dm_i ( dm ),
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.rtn_i ( rtn ),
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.stk_clr_i ( stk_clr ),
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.pop_i ( pop ),
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.push_i ( push ),
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.thrd_6_i ( thrd_6 ),
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.im_data_i ( im_data ),
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.dm_data_i ( rd_data ),
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.pc_3_i ( pc_3 ),
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.a_o ( a ),
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.b_o ( b ),
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.nez_o ( nez ),
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.ne_o ( ne ),
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.ltz_o ( ltz ),
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.lt_o ( lt ),
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.pop_er_o ( pop_er ),
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.push_er_o ( push_er )
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);
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| 319 |
|
|
|
| 320 |
|
|
|
| 321 |
|
|
// shim for memory and register set access
|
| 322 |
|
|
reg_set_shim
|
| 323 |
|
|
#(
|
| 324 |
|
|
.REGS_IN ( 1 ),
|
| 325 |
|
|
.REGS_OUT ( 1 ),
|
| 326 |
|
|
.DATA_W ( DATA_W ),
|
| 327 |
|
|
.ADDR_W ( ADDR_W ),
|
| 328 |
|
|
.REG_ADDR_W ( REG_ADDR_W ),
|
| 329 |
|
|
.IM_ADDR_W ( IM_RW_W )
|
| 330 |
|
|
)
|
| 331 |
|
|
reg_set_shim
|
| 332 |
|
|
(
|
| 333 |
|
|
.clk_i ( clk_i ),
|
| 334 |
|
|
.rst_i ( rst_i ),
|
| 335 |
|
|
.a_i ( a ),
|
| 336 |
|
|
.ext_i ( ext ),
|
| 337 |
|
|
.wr_data_o ( wr_data ),
|
| 338 |
|
|
.b_lo_i ( b[DATA_W/2-1:0] ),
|
| 339 |
|
|
.im_addr_i ( im_addr[IM_RW_W-1:0] ),
|
| 340 |
|
|
.pc_1_i ( pc_1 ),
|
| 341 |
|
|
.addr_o ( addr ),
|
| 342 |
|
|
.wr_i ( wr ),
|
| 343 |
|
|
.rd_i ( rd ),
|
| 344 |
|
|
.regs_wr_o ( regs_wr ),
|
| 345 |
|
|
.regs_rd_o ( regs_rd ),
|
| 346 |
|
|
.dm_wr_o ( dm_wr )
|
| 347 |
|
|
);
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
// internal register set
|
| 351 |
|
|
reg_set
|
| 352 |
|
|
#(
|
| 353 |
|
|
.REGS_IN ( 1 ),
|
| 354 |
|
|
.REGS_OUT ( 1 ),
|
| 355 |
|
|
.DATA_W ( DATA_W/2 ),
|
| 356 |
|
|
.ADDR_W ( REG_ADDR_W ),
|
| 357 |
|
|
.THREADS ( THREADS ),
|
| 358 |
|
|
.THRD_W ( THRD_W ),
|
| 359 |
|
|
.STACKS ( STACKS ),
|
| 360 |
|
|
.STK_W ( STK_W ),
|
| 361 |
|
|
.VER_MAJ ( VER_MAJ ),
|
| 362 |
|
|
.VER_MIN ( VER_MIN )
|
| 363 |
|
|
)
|
| 364 |
|
|
reg_set
|
| 365 |
|
|
(
|
| 366 |
|
|
.clk_i ( clk_i ),
|
| 367 |
|
|
.rst_i ( rst_i ),
|
| 368 |
|
|
.addr_i ( addr[REG_ADDR_W-1:0] ),
|
| 369 |
|
|
.wr_i ( regs_wr ),
|
| 370 |
|
|
.rd_i ( regs_rd ),
|
| 371 |
|
|
.data_i ( wr_data ),
|
| 372 |
|
|
.data_o ( rd_data ),
|
| 373 |
|
|
.dm_data_i ( dm_rd_data ),
|
| 374 |
|
|
.clr_req_o ( clr_req ),
|
| 375 |
|
|
.intr_en_o ( intr_en ),
|
| 376 |
|
|
.thrd_0_i ( thrd_0 ),
|
| 377 |
|
|
.op_code_er_i ( op_code_er ),
|
| 378 |
|
|
.thrd_2_i ( thrd_2 ),
|
| 379 |
|
|
.pop_er_i ( pop_er ),
|
| 380 |
|
|
.thrd_3_i ( thrd_3 ),
|
| 381 |
|
|
.push_er_i ( push_er ),
|
| 382 |
|
|
.io_lo_i ( io_i[DATA_W/2-1:0] ),
|
| 383 |
|
|
.io_hi_i ( io_i[DATA_W-1:DATA_W/2] ),
|
| 384 |
|
|
.io_lo_o ( io_o[DATA_W/2-1:0] ),
|
| 385 |
|
|
.io_hi_o ( io_o[DATA_W-1:DATA_W/2] )
|
| 386 |
|
|
);
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
// instruction and data memory
|
| 390 |
|
|
dp_ram_infer
|
| 391 |
|
|
#(
|
| 392 |
|
|
.REG_A_OUT ( 1 ),
|
| 393 |
|
|
.REG_B_OUT ( 1 ),
|
| 394 |
|
|
.DATA_W ( OP_CODE_W ),
|
| 395 |
|
|
.ADDR_W ( MEM_ADDR_W ),
|
| 396 |
|
|
.RD_MODE ( "WR_DATA" ) // functional don't care
|
| 397 |
|
|
)
|
| 398 |
|
|
main_mem
|
| 399 |
|
|
(
|
| 400 |
|
|
.a_clk_i ( clk_i ),
|
| 401 |
|
|
.a_addr_i ( addr ),
|
| 402 |
|
|
.a_wr_i ( dm_wr ),
|
| 403 |
|
|
.a_data_i ( wr_data ),
|
| 404 |
|
|
.a_data_o ( dm_rd_data ),
|
| 405 |
|
|
.b_clk_i ( clk_i ),
|
| 406 |
|
|
.b_addr_i ( pc_4 ),
|
| 407 |
|
|
.b_wr_i ( 1'b0 ), // unused
|
| 408 |
|
|
.b_data_i ( ), // unused
|
| 409 |
|
|
.b_data_o ( op_code )
|
| 410 |
|
|
);
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
endmodule
|
