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[/] [hive/] [trunk/] [v01.10/] [dp_ram_infer.v] - Blame information for rev 3

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/*
--------------------------------------------------------------------------------
 
Module: dp_ram_infer.v
 
Function:
- Infers a parameterized dual port synchronous RAM.
 
Instantiates:
- Nothing (block RAM will most likely be synthesized).
 
Notes:
- A & B sides are separate clock domains.
- Writes accept data after the address & write enable on the clock.
- Reads present data after the address on the clock.
- Configurable read-during-write mode (for the same port).
- Optional output data registering (likely an internal BRAM resource).
 
--------------------------------------------------------------------------------
*/
 
module dp_ram_infer
        #(
        parameter               integer                                         REG_A_OUT               = 1,  // 1=enable A output registering
        parameter               integer                                         REG_B_OUT               = 1,  // 1=enable B output registering
        parameter               integer                                         DATA_W                  = 16,
        parameter               integer                                         ADDR_W                  = 8,
        parameter                                                                               RD_MODE                         = "WR_DATA"  // options here are "MEM_DATA" and "WR_DATA"
        )
        (
        // A side
        input                   wire                                                            a_clk_i,                                // A clock
        input                   wire    [ADDR_W-1:0]                     a_addr_i,                       // A address
        input                   wire                                                            a_wr_i,                         // A write enable, active high
        input                   wire    [DATA_W-1:0]                     a_data_i,                       // A write data
        output          wire    [DATA_W-1:0]                     a_data_o,                       // A read data
        // B side
        input                   wire                                                            b_clk_i,                                // B clock
        input                   wire    [ADDR_W-1:0]                     b_addr_i,                       // B address
        input                   wire                                                            b_wr_i,                         // B write enable, active high
        input                   wire    [DATA_W-1:0]                     b_data_i,                       // B write data
        output          wire    [DATA_W-1:0]                     b_data_o                                // B read data
        );
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        localparam              integer                                         CAPACITY                        = 2**ADDR_W;    // total words possible to store
        reg                                     [DATA_W-1:0]                     ram[0:CAPACITY-1];  // memory
        reg                                     [DATA_W-1:0]                     a_data, b_data;
        `include "boot_code.h"
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
 
        /*
        ------------
        -- side A --
        ------------
        */
 
        // write
        always @ ( posedge a_clk_i ) begin
                if ( a_wr_i ) begin
                        ram[a_addr_i] <= a_data_i;
                end
        end
 
        // read
        always @ ( posedge a_clk_i ) begin
                if ( a_wr_i & RD_MODE == "WR_DATA" ) begin
                        a_data <= a_data_i;
                end else begin
                        a_data <= ram[a_addr_i];
                end
        end
 
        // optional output reg
        generate
                if ( REG_A_OUT ) begin
                        reg [DATA_W-1:0] a_data_r;
                        always @ ( posedge a_clk_i ) begin
                                a_data_r <= a_data;
                        end
                        assign a_data_o = a_data_r;
                end else begin
                        assign a_data_o = a_data;
                end
        endgenerate
 
 
        /*
        ------------
        -- side B --
        ------------
        */
 
        // write
        always @ ( posedge b_clk_i ) begin
                if ( b_wr_i ) begin
                        ram[b_addr_i] <= b_data_i;
                end
        end
 
        // read
        always @ ( posedge b_clk_i ) begin
                if ( b_wr_i & RD_MODE == "WR_DATA" ) begin
                        b_data <= b_data_i;
                end else begin
                        b_data <= ram[b_addr_i];
                end
        end
 
        // optional output reg
        generate
                if ( REG_B_OUT ) begin
                        reg [DATA_W-1:0] b_data_r;
                        always @ ( posedge b_clk_i ) begin
                                b_data_r <= b_data;
                        end
                        assign b_data_o = b_data_r;
                end else begin
                        assign b_data_o = b_data;
                end
        endgenerate
 
 
endmodule

Line No.	Rev	Author	Line
1	3	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module: dp_ram_infer.v`
5
6			`Function:`
7			`- Infers a parameterized dual port synchronous RAM.`
8
9			`Instantiates:`
10			`- Nothing (block RAM will most likely be synthesized).`
11
12			`Notes:`
13			`- A & B sides are separate clock domains.`
14			`- Writes accept data after the address & write enable on the clock.`
15			`- Reads present data after the address on the clock.`
16			`- Configurable read-during-write mode (for the same port).`
17			`- Optional output data registering (likely an internal BRAM resource).`
18
19			`--------------------------------------------------------------------------------`
20			`*/`
21
22			`module dp_ram_infer`
23			`#(`
24			`parameter integer REG_A_OUT = 1, // 1=enable A output registering`
25			`parameter integer REG_B_OUT = 1, // 1=enable B output registering`
26			`parameter integer DATA_W = 16,`
27			`parameter integer ADDR_W = 8,`
28			`parameter RD_MODE = "WR_DATA" // options here are "MEM_DATA" and "WR_DATA"`
29			`)`
30			`(`
31			`// A side`
32			`input wire a_clk_i, // A clock`
33			`input wire [ADDR_W-1:0] a_addr_i, // A address`
34			`input wire a_wr_i, // A write enable, active high`
35			`input wire [DATA_W-1:0] a_data_i, // A write data`
36			`output wire [DATA_W-1:0] a_data_o, // A read data`
37			`// B side`
38			`input wire b_clk_i, // B clock`
39			`input wire [ADDR_W-1:0] b_addr_i, // B address`
40			`input wire b_wr_i, // B write enable, active high`
41			`input wire [DATA_W-1:0] b_data_i, // B write data`
42			`output wire [DATA_W-1:0] b_data_o // B read data`
43			`);`
44
45			`/*`
46			`----------------------`
47			`-- internal signals --`
48			`----------------------`
49			`*/`
50			`localparam integer CAPACITY = 2**ADDR_W; // total words possible to store`
51			`reg [DATA_W-1:0] ram[0:CAPACITY-1]; // memory`
52			`reg [DATA_W-1:0] a_data, b_data;`
53			`include "boot_code.h"
54
55
56
57			`/*`
58			`================`
59			`== code start ==`
60			`================`
61			`*/`
62
63
64
65			`/*`
66			`------------`
67			`-- side A --`
68			`------------`
69			`*/`
70
71			`// write`
72			`always @ ( posedge a_clk_i ) begin`
73			`if ( a_wr_i ) begin`
74			`ram[a_addr_i] <= a_data_i;`
75			`end`
76			`end`
77
78			`// read`
79			`always @ ( posedge a_clk_i ) begin`
80			`if ( a_wr_i & RD_MODE == "WR_DATA" ) begin`
81			`a_data <= a_data_i;`
82			`end else begin`
83			`a_data <= ram[a_addr_i];`
84			`end`
85			`end`
86
87			`// optional output reg`
88			`generate`
89			`if ( REG_A_OUT ) begin`
90			`reg [DATA_W-1:0] a_data_r;`
91			`always @ ( posedge a_clk_i ) begin`
92			`a_data_r <= a_data;`
93			`end`
94			`assign a_data_o = a_data_r;`
95			`end else begin`
96			`assign a_data_o = a_data;`
97			`end`
98			`endgenerate`
99
100
101			`/*`
102			`------------`
103			`-- side B --`
104			`------------`
105			`*/`
106
107			`// write`
108			`always @ ( posedge b_clk_i ) begin`
109			`if ( b_wr_i ) begin`
110			`ram[b_addr_i] <= b_data_i;`
111			`end`
112			`end`
113
114			`// read`
115			`always @ ( posedge b_clk_i ) begin`
116			`if ( b_wr_i & RD_MODE == "WR_DATA" ) begin`
117			`b_data <= b_data_i;`
118			`end else begin`
119			`b_data <= ram[b_addr_i];`
120			`end`
121			`end`
122
123			`// optional output reg`
124			`generate`
125			`if ( REG_B_OUT ) begin`
126			`reg [DATA_W-1:0] b_data_r;`
127			`always @ ( posedge b_clk_i ) begin`
128			`b_data_r <= b_data;`
129			`end`
130			`assign b_data_o = b_data_r;`
131			`end else begin`
132			`assign b_data_o = b_data;`
133			`end`
134			`endgenerate`
135
136
137			`endmodule`

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[/] [hive/] [trunk/] [v01.10/] [dp_ram_infer.v] - Blame information for rev 3