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[/] [hive/] [trunk/] [v01.10/] [event_ctrl.v] - Blame information for rev 3

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/*
--------------------------------------------------------------------------------
 
Module: event_ctrl.v
 
Function:
- Event (clear & interrupt) controller for multi-threaded processor.
 
Instantiates:
- (1x) vector_sr.v
 
Notes:
- Request is latched and acked until serviced.
- Event output is valid for the stage following this one.
- Optional req regs & resync.
- Optional req level / edge operation.
- For automatic clearing @ async reset, set RESET_VAL to 1.
 
--------------------------------------------------------------------------------
*/
 
module event_ctrl
        #(
        parameter       integer                                                 REGS_REQ                        = 2,            // input registers option
        parameter       integer                                                 EDGE_REQ                        = 0,             // edge/level input option
        parameter       integer                                                 RESET_VAL               = 1,            // async reset value option
        parameter       integer                                                 THREADS                 = 4,            // number of threads
        parameter       integer                                                 THRD_W                  = 2             // thread width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // I/O
        input                   wire            [THRD_W-1:0]             thrd_i,                                         // thread
        input                   wire            [THREADS-1:0]            en_i,                                                   // event enable, active high
        input                   wire            [THREADS-1:0]            req_i,                                          // event request, active high
        output          reg             [THREADS-1:0]            ack_o,                                          // event ack, active high until serviced
        output          reg                                                             event_o                                         // event, active high for one clock
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                    [THREADS-1:0]                                    req_0, req_2, thread_flag;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // optional input req regs
        vector_sr
        #(
        .REGS                   ( REGS_REQ ),
        .DATA_W         ( THREADS ),
        .RESET_VAL      ( 0 )
        )
        req_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( req_i ),
        .data_o         ( req_0 )
        );
 
 
        // optional input req edge detect
        generate
                if ( EDGE_REQ ) begin
                        reg [THREADS-1:0] req_1;
                        always @ ( posedge clk_i or posedge rst_i ) begin
                                if ( rst_i ) begin
                                        req_1 <= 'b0;
                                end else begin
                                        req_1 <= req_0;
                                end
                        end
                        assign req_2 = req_0 & ~req_1;
                end else begin
                        assign req_2 = req_0;
                end
        endgenerate
 
        // decode thread flags (one hot)
        assign thread_flag = 1'b1 << thrd_i;
 
        // register & latch events
        always @ ( posedge clk_i or posedge rst_i ) begin
                if ( rst_i ) begin
                        ack_o <= { THREADS{ RESET_VAL[0] } };
                end else begin
                        ack_o <= ( en_i & req_2 ) | ( ack_o & ~thread_flag );
                end
        end
 
        // output event (use in following stage)
        always @ ( posedge clk_i or posedge rst_i ) begin
                if ( rst_i ) begin
                        event_o <= 'b0;
                end else begin
                        event_o <= |( ack_o & thread_flag );
                end
        end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module: event_ctrl.v`
5
6			`Function:`
7			`- Event (clear & interrupt) controller for multi-threaded processor.`
8
9			`Instantiates:`
10			`- (1x) vector_sr.v`
11
12			`Notes:`
13			`- Request is latched and acked until serviced.`
14			`- Event output is valid for the stage following this one.`
15			`- Optional req regs & resync.`
16			`- Optional req level / edge operation.`
17			`- For automatic clearing @ async reset, set RESET_VAL to 1.`
18
19			`--------------------------------------------------------------------------------`
20			`*/`
21
22			`module event_ctrl`
23			`#(`
24			`parameter integer REGS_REQ = 2, // input registers option`
25			`parameter integer EDGE_REQ = 0, // edge/level input option`
26			`parameter integer RESET_VAL = 1, // async reset value option`
27			`parameter integer THREADS = 4, // number of threads`
28			`parameter integer THRD_W = 2 // thread width`
29			`)`
30			`(`
31			`// clocks & resets`
32			`input wire clk_i, // clock`
33			`input wire rst_i, // async. reset, active high`
34			`// I/O`
35			`input wire [THRD_W-1:0] thrd_i, // thread`
36			`input wire [THREADS-1:0] en_i, // event enable, active high`
37			`input wire [THREADS-1:0] req_i, // event request, active high`
38			`output reg [THREADS-1:0] ack_o, // event ack, active high until serviced`
39			`output reg event_o // event, active high for one clock`
40			`);`
41
42
43			`/*`
44			`----------------------`
45			`-- internal signals --`
46			`----------------------`
47			`*/`
48			`wire [THREADS-1:0] req_0, req_2, thread_flag;`
49
50
51
52			`/*`
53			`================`
54			`== code start ==`
55			`================`
56			`*/`
57
58
59			`// optional input req regs`
60			`vector_sr`
61			`#(`
62			`.REGS ( REGS_REQ ),`
63			`.DATA_W ( THREADS ),`
64			`.RESET_VAL ( 0 )`
65			`)`
66			`req_regs`
67			`(`
68			`.clk_i ( clk_i ),`
69			`.rst_i ( rst_i ),`
70			`.data_i ( req_i ),`
71			`.data_o ( req_0 )`
72			`);`
73
74
75			`// optional input req edge detect`
76			`generate`
77			`if ( EDGE_REQ ) begin`
78			`reg [THREADS-1:0] req_1;`
79			`always @ ( posedge clk_i or posedge rst_i ) begin`
80			`if ( rst_i ) begin`
81			`req_1 <= 'b0;`
82			`end else begin`
83			`req_1 <= req_0;`
84			`end`
85			`end`
86			`assign req_2 = req_0 & ~req_1;`
87			`end else begin`
88			`assign req_2 = req_0;`
89			`end`
90			`endgenerate`
91
92			`// decode thread flags (one hot)`
93			`assign thread_flag = 1'b1 << thrd_i;`
94
95			`// register & latch events`
96			`always @ ( posedge clk_i or posedge rst_i ) begin`
97			`if ( rst_i ) begin`
98			`ack_o <= { THREADS{ RESET_VAL[0] } };`
99			`end else begin`
100			`ack_o <= ( en_i & req_2 ) \| ( ack_o & ~thread_flag );`
101			`end`
102			`end`
103
104			`// output event (use in following stage)`
105			`always @ ( posedge clk_i or posedge rst_i ) begin`
106			`if ( rst_i ) begin`
107			`event_o <= 'b0;`
108			`end else begin`
109			`event_o <= \|( ack_o & thread_flag );`
110			`end`
111			`end`
112
113
114			`endmodule`

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[/] [hive/] [trunk/] [v01.10/] [event_ctrl.v] - Blame information for rev 3