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ericw |
/*
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Module : pointer_ring.v
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--------------------------------------------------------------------------------
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Function:
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- Processor stack pointer storage ring.
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Instantiates:
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- (1x) vector_sr.v
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Notes:
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- 8 stage pointer storage ring for four BRAM based LIFOs:
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1 : pop applied
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2 : push applied; pop errors output
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3 : push errors output
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6 : pointers & writes output
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- Logic assumes pop | push will not be issued simultaneously with clear.
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- Externally concatenate thread 6 & pointers to form stack memory addresses.
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- Level width is PTR_W+1 to accomodate 0 to 2^n levels (1 + 2n states).
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- Empty push is to address 1, full push is to address 0.
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- Combo pop/push is accomodated with no net fullness/pointer change.
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- Pop when empty is a pop error.
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- Push when full is a push error.
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- Pop/push when full is NOT an error.
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- Pop/push when empty is a pop error ONLY.
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- Parameterized stack error handling. If the associated protection is turned on
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then pop/push errors are reported but otherwise not acted upon, i.e. errors
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will not corrupt fullness/pointers.
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--------------------------------------------------------------------------------
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*/
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module pointer_ring
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#(
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parameter integer THREADS = 8, // threads
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parameter integer STACKS = 4, // stacks
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parameter integer PNTR_W = 5, // stack pointer width
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parameter integer POP_PROT = 1, // 1=error protection, 0=none
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parameter integer PUSH_PROT = 1 // 1=error protection, 0=none
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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// control I/O
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input wire clr_i, // stacks clear
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input wire [STACKS-1:0] pop_i, // stacks pop
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input wire [STACKS-1:0] push_i, // stacks push
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// pointers
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output wire [PNTR_W-1:0] pntr0_o, // stack pointer
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output wire [PNTR_W-1:0] pntr1_o, // stack pointer
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output wire [PNTR_W-1:0] pntr2_o, // stack pointer
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output wire [PNTR_W-1:0] pntr3_o, // stack pointer
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// write enables
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output wire [STACKS-1:0] wr_o, // write enables
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// errors
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output wire [STACKS-1:0] pop_er_o, // pop when empty, active high
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output wire [STACKS-1:0] push_er_o // push when full, active high
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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localparam integer LEVEL_W = PNTR_W+1; // +1 extra bit
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localparam [LEVEL_W-1:0] EMPTY_VAL = 'b0; // empty value
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localparam [LEVEL_W-1:0] FULL_VAL = 1'b1 << PNTR_W; // full value
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//
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integer s, t;
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//
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reg [LEVEL_W-1:0] level[0:STACKS-1][0:THREADS-1];
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//
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reg [STACKS-1:0] pop_1, push_1, push_2;
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reg [STACKS-1:0] empty_1, full_2;
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wire [STACKS-1:0] dec_1, inc_2;
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reg [STACKS-1:0] pop_er_2, push_er_3;
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/*
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================
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== code start ==
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================
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*/
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// pipeline control signals
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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pop_1 <= 'b0;
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push_1 <= 'b0;
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push_2 <= 'b0;
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end else begin
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pop_1 <= pop_i;
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push_1 <= push_i;
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push_2 <= push_1;
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end
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end
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// decode watermarks
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always @ ( * ) begin
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for ( s=0; s<STACKS; s=s+1 ) begin
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empty_1[s] <= ( level[s][1] == EMPTY_VAL );
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full_2[s] <= ( level[s][2] == FULL_VAL );
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end
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end
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// prohibit pointer changes @ errors if configured to do so
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assign dec_1 = ( POP_PROT ) ? pop_1 & ~empty_1 : pop_1;
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assign inc_2 = ( PUSH_PROT ) ? push_2 & ~full_2 : push_2;
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// decode & register errors - pop when empty, push when full
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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pop_er_2 <= 'b0;
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push_er_3 <= 'b0;
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end else begin
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pop_er_2 <= pop_1 & empty_1;
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push_er_3 <= push_2 & full_2;
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end
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end
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// decode & pipeline levels
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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for ( s=0; s<STACKS; s=s+1 ) begin
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for ( t=0; t<THREADS; t=t+1 ) begin
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level[s][t] <= 'b0;
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end
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end
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end else begin
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for ( s=0; s<STACKS; s=s+1 ) begin
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for ( t=0; t<THREADS; t=t+1 ) begin
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if ( t == 0 ) level[s][t] <= level[s][THREADS-1]; // wrap around
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else if ( t == 1 ) level[s][t] <= ( clr_i ) ? 1'b0 : level[s][t-1]; // clear
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else if ( t == 2 ) level[s][t] <= ( dec_1[s] ) ? level[s][t-1] - 1'b1 : level[s][t-1]; // pop
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else if ( t == 3 ) level[s][t] <= ( inc_2[s] ) ? level[s][t-1] + 1'b1 : level[s][t-1]; // push
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else level[s][t] <= level[s][t-1];
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end
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end
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end
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end
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// decode & pipeline write enables
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vector_sr
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#(
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.REGS ( 4 ),
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.DATA_W ( STACKS ),
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.RESET_VAL ( 0 )
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)
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wr_pipe
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.data_i ( inc_2 ),
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.data_o ( wr_o )
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);
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// output pointers
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assign pntr0_o = level[0][6][PNTR_W-1:0];
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assign pntr1_o = level[1][6][PNTR_W-1:0];
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assign pntr2_o = level[2][6][PNTR_W-1:0];
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assign pntr3_o = level[3][6][PNTR_W-1:0];
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// output errors
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assign pop_er_o = pop_er_2;
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assign push_er_o = push_er_3;
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endmodule
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