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[/] [hive/] [trunk/] [v04.05/] [alu_logical.v] - Blame information for rev 4

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/*
--------------------------------------------------------------------------------
 
Module : alu_logical.v
 
--------------------------------------------------------------------------------
 
Function:
- Logic unit for a processor ALU.
 
Instantiates:
- (4x) pipe.v
- (1x) lg_sel_encode.h
 
Notes:
- IN/MID/OUT/FLG optionally registered.
- Default path through is copy.
 
--------------------------------------------------------------------------------
*/
 
module alu_logical
        #(
        parameter       integer                                                 REGS_IN                 = 1,            // register option for inputs
        parameter       integer                                                 REGS_MID                        = 1,            // mid register option
        parameter       integer                                                 REGS_OUT                        = 1,            // register option for outputs
        parameter       integer                                                 REGS_FLG                        = 1,            // register option for flag outputs
        parameter       integer                                                 DATA_W                  = 32,           // data width
        parameter       integer                                                 LG_SEL_W                        = 4             // operation width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire    [LG_SEL_W-1:0]                   lg_sel_i,                                       // operation (see lg_sel_encode.h)
        // data I/O
        input                   wire    [DATA_W-1:0]                     a_i,                                                    // operand
        input                   wire    [DATA_W-1:0]                     b_i,                                                    // operand
        output          wire    [DATA_W-1:0]                     result_o,                                       // logical result
        // flags
        output          wire                                                            flg_nz_o,                                       //      a != 0
        output          wire                                                            flg_lz_o                                                //      a < 0
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        `include "lg_sel_encode.h"
        `include "functions.h"  // for clog2(), flip_32(), lzc_32()
        localparam      integer                                                 LZC_W                   = clog2( DATA_W ) + 1;
        //
        wire                                    [LG_SEL_W-1:0]                   lg_sel, lg_sel_m;
        wire                                    [DATA_W-1:0]                     a, b;
        reg                                     [DATA_W-1:0]                     res_1op, res_2op;
        wire                                    [DATA_W-1:0]                     res_1op_m, res_2op_m;
        reg                                                                                             res_br;
        wire                                                                                            res_br_m;
        reg                                     [DATA_W-1:0]                     result;
        wire                                                                                            flg_nz, flg_lz;
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // optional input registers
        pipe
        #(
        .DEPTH          ( REGS_IN ),
        .WIDTH          ( LG_SEL_W+DATA_W+DATA_W ),
        .RESET_VAL      ( 0 )
        )
        in_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { lg_sel_i, b_i, a_i,  } ),
        .data_o         ( { lg_sel,   b,   a     } )
        );
 
 
        // flags
        assign flg_nz = |a;
        assign flg_lz = a[DATA_W-1];
 
        // multiplex one operand results
        always @ ( * ) begin
                case ( lg_sel )
                        `lg_nsg : res_1op <= { ~b[DATA_W-1], b[DATA_W-2:0] };
                        `lg_not : res_1op <= ~b;
                        `lg_flp : res_1op <= flip_32( b );
                        `lg_lzc : res_1op <= lzc_32( b );
                        default : res_1op <= b;  // default is copy
                endcase
        end
 
        // multiplex one operand bit reduction results
        always @ ( * ) begin
                case ( lg_sel )
                        `lg_bro : res_br <= |b;
                        `lg_brx : res_br <= ^b;
                        default : res_br <= &b;
                endcase
        end
 
        // multiplex two operand results
        always @ ( * ) begin
                case ( lg_sel )
                        `lg_orr : res_2op <= a | b;
                        `lg_xor : res_2op <= a ^ b;
                        default : res_2op <= a & b;
                endcase
        end
 
 
        // optional flag regs
        pipe
        #(
        .DEPTH          ( REGS_FLG ),
        .WIDTH          ( 2 ),
        .RESET_VAL      ( 0 )
        )
        regs_flags
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { flg_nz,   flg_lz,  } ),
        .data_o         ( { flg_nz_o, flg_lz_o } )
        );
 
 
        // optional mid regs
        pipe
        #(
        .DEPTH          ( REGS_MID ),
        .WIDTH          ( LG_SEL_W+1+DATA_W+DATA_W ),
        .RESET_VAL      ( 0 )
        )
        mid_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { lg_sel,   res_br,   res_2op,   res_1op   } ),
        .data_o         ( { lg_sel_m, res_br_m, res_2op_m, res_1op_m } )
        );
 
 
        // multiplex
        always @ ( * ) begin
                case ( lg_sel_m )
                        `lg_bra, `lg_bro, `lg_brx : result <= { DATA_W{ res_br_m } };
                        `lg_and, `lg_orr, `lg_xor : result <= res_2op_m;
                        default                   : result <= res_1op_m;  // default is copy
                endcase
        end
 
 
        // optional output regs
        pipe
        #(
        .DEPTH          ( REGS_OUT ),
        .WIDTH          ( DATA_W ),
        .RESET_VAL      ( 0 )
        )
        out_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( result ),
        .data_o         ( result_o )
        );
 
 
endmodule

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : alu_logical.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Logic unit for a processor ALU.`
10
11			`Instantiates:`
12			`- (4x) pipe.v`
13			`- (1x) lg_sel_encode.h`
14
15			`Notes:`
16			`- IN/MID/OUT/FLG optionally registered.`
17			`- Default path through is copy.`
18
19			`--------------------------------------------------------------------------------`
20			`*/`
21
22			`module alu_logical`
23			`#(`
24			`parameter integer REGS_IN = 1, // register option for inputs`
25			`parameter integer REGS_MID = 1, // mid register option`
26			`parameter integer REGS_OUT = 1, // register option for outputs`
27			`parameter integer REGS_FLG = 1, // register option for flag outputs`
28			`parameter integer DATA_W = 32, // data width`
29			`parameter integer LG_SEL_W = 4 // operation width`
30			`)`
31			`(`
32			`// clocks & resets`
33			`input wire clk_i, // clock`
34			`input wire rst_i, // async. reset, active high`
35			`// control I/O`
36			`input wire [LG_SEL_W-1:0] lg_sel_i, // operation (see lg_sel_encode.h)`
37			`// data I/O`
38			`input wire [DATA_W-1:0] a_i, // operand`
39			`input wire [DATA_W-1:0] b_i, // operand`
40			`output wire [DATA_W-1:0] result_o, // logical result`
41			`// flags`
42			`output wire flg_nz_o, // a != 0`
43			`output wire flg_lz_o // a < 0`
44			`);`
45
46
47			`/*`
48			`----------------------`
49			`-- internal signals --`
50			`----------------------`
51			`*/`
52			`include "lg_sel_encode.h"
53			`include "functions.h" // for clog2(), flip_32(), lzc_32()
54			`localparam integer LZC_W = clog2( DATA_W ) + 1;`
55			`//`
56			`wire [LG_SEL_W-1:0] lg_sel, lg_sel_m;`
57			`wire [DATA_W-1:0] a, b;`
58			`reg [DATA_W-1:0] res_1op, res_2op;`
59			`wire [DATA_W-1:0] res_1op_m, res_2op_m;`
60			`reg res_br;`
61			`wire res_br_m;`
62			`reg [DATA_W-1:0] result;`
63			`wire flg_nz, flg_lz;`
64
65
66			`/*`
67			`================`
68			`== code start ==`
69			`================`
70			`*/`
71
72
73			`// optional input registers`
74			`pipe`
75			`#(`
76			`.DEPTH ( REGS_IN ),`
77			`.WIDTH ( LG_SEL_W+DATA_W+DATA_W ),`
78			`.RESET_VAL ( 0 )`
79			`)`
80			`in_regs`
81			`(`
82			`.clk_i ( clk_i ),`
83			`.rst_i ( rst_i ),`
84			`.data_i ( { lg_sel_i, b_i, a_i, } ),`
85			`.data_o ( { lg_sel, b, a } )`
86			`);`
87
88
89			`// flags`
90			`assign flg_nz = \|a;`
91			`assign flg_lz = a[DATA_W-1];`
92
93			`// multiplex one operand results`
94			`always @ ( * ) begin`
95			`case ( lg_sel )`
96			`lg_nsg : res_1op <= { ~b[DATA_W-1], b[DATA_W-2:0] };
97			`lg_not : res_1op <= ~b;
98			`lg_flp : res_1op <= flip_32( b );
99			`lg_lzc : res_1op <= lzc_32( b );
100			`default : res_1op <= b; // default is copy`
101			`endcase`
102			`end`
103
104			`// multiplex one operand bit reduction results`
105			`always @ ( * ) begin`
106			`case ( lg_sel )`
107			`lg_bro : res_br <= \|b;
108			`lg_brx : res_br <= ^b;
109			`default : res_br <= &b;`
110			`endcase`
111			`end`
112
113			`// multiplex two operand results`
114			`always @ ( * ) begin`
115			`case ( lg_sel )`
116			`lg_orr : res_2op <= a \| b;
117			`lg_xor : res_2op <= a ^ b;
118			`default : res_2op <= a & b;`
119			`endcase`
120			`end`
121
122
123			`// optional flag regs`
124			`pipe`
125			`#(`
126			`.DEPTH ( REGS_FLG ),`
127			`.WIDTH ( 2 ),`
128			`.RESET_VAL ( 0 )`
129			`)`
130			`regs_flags`
131			`(`
132			`.clk_i ( clk_i ),`
133			`.rst_i ( rst_i ),`
134			`.data_i ( { flg_nz, flg_lz, } ),`
135			`.data_o ( { flg_nz_o, flg_lz_o } )`
136			`);`
137
138
139			`// optional mid regs`
140			`pipe`
141			`#(`
142			`.DEPTH ( REGS_MID ),`
143			`.WIDTH ( LG_SEL_W+1+DATA_W+DATA_W ),`
144			`.RESET_VAL ( 0 )`
145			`)`
146			`mid_regs`
147			`(`
148			`.clk_i ( clk_i ),`
149			`.rst_i ( rst_i ),`
150			`.data_i ( { lg_sel, res_br, res_2op, res_1op } ),`
151			`.data_o ( { lg_sel_m, res_br_m, res_2op_m, res_1op_m } )`
152			`);`
153
154
155			`// multiplex`
156			`always @ ( * ) begin`
157			`case ( lg_sel_m )`
158			`lg_bra, `lg_bro, `lg_brx : result <= { DATA_W{ res_br_m } };
159			`lg_and, `lg_orr, `lg_xor : result <= res_2op_m;
160			`default : result <= res_1op_m; // default is copy`
161			`endcase`
162			`end`
163
164
165			`// optional output regs`
166			`pipe`
167			`#(`
168			`.DEPTH ( REGS_OUT ),`
169			`.WIDTH ( DATA_W ),`
170			`.RESET_VAL ( 0 )`
171			`)`
172			`out_regs`
173			`(`
174			`.clk_i ( clk_i ),`
175			`.rst_i ( rst_i ),`
176			`.data_i ( result ),`
177			`.data_o ( result_o )`
178			`);`
179
180
181			`endmodule`

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[/] [hive/] [trunk/] [v04.05/] [alu_logical.v] - Blame information for rev 4