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[/] [hive/] [trunk/] [v04.05/] [alu_mux.v] - Blame information for rev 4

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/*
--------------------------------------------------------------------------------
 
Module : alu_mux.v
 
--------------------------------------------------------------------------------
 
Function:
- Multiplexer for processor ALU.
 
Instantiates:
- (5x) pipe.v
 
Notes:
- Inputs at stage 1, outputs at stage 6.
- Default behavior is pass-thru.
 
--------------------------------------------------------------------------------
*/
 
module alu_mux
        #(
        parameter       integer                                                 DATA_W                  = 8,            // data width
        parameter       integer                                                 ADDR_W                  = 4             // address width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire                                                            sgn_1_i,                                                // 1=signed
        input                   wire                                                            hgh_1_i,                                                // 1=high
        input                   wire                                                            as_1_i,                                         // 1=add/subtract
        input                   wire                                                            ms_1_i,                                         // 1=multiply/shift
        input                   wire                                                            rtn_1_i,                                                // 1=return pc
        input                   wire                                                            dm_rd_1_i,                                      // 1=read
        input                   wire                                                            rg_rd_1_i,                                      // 1=read
        // data I/O
        input                   wire    [DATA_W-1:0]                     res_lg_2_i,                                     // logical result
        input                   wire    [DATA_W-1:0]                     res_as_2_i,                                     // add/subtract result
        input                   wire    [ADDR_W-1:0]                     pc_3_i,                                         // program counter
        input                   wire    [DATA_W/2-1:0]                   dm_rd_data_4_i,                 // dmem read data
        input                   wire    [DATA_W/2-1:0]                   rg_rd_data_4_i,                 // regs read data
        input                   wire    [DATA_W-1:0]                     res_ms_5_i,                                     // multiply/shift result
        output          wire    [DATA_W-1:0]                     data_6_o                                                // data out
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                                                                            as_2, rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2;
        wire                                                                                                  rtn_3, sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3;
        wire                                                                                                         sgn_4, rg_rd_4, dm_rd_4, hgh_4, ms_4;
        wire                                                                                                                                         ms_5;
        wire                                    [DATA_W-1:0]                             data_3, data_4, data_5;
        reg                                     [DATA_W-1:0]                     mux_2,  mux_3,  mux_4,  mux_5;
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // 1 to 2 regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( 7 ),
        .RESET_VAL      ( 0 )
        )
        regs_1_2
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { as_1_i, rtn_1_i, sgn_1_i, rg_rd_1_i, dm_rd_1_i, hgh_1_i, ms_1_i } ),
        .data_o         ( { as_2,   rtn_2,   sgn_2,   rg_rd_2,   dm_rd_2,   hgh_2,   ms_2   } )
        );
 
 
        // mux 2
        always @ ( * ) begin
                casex ( as_2 )
                        'b1     : mux_2 <= res_as_2_i;
                        default : mux_2 <= res_lg_2_i;  // default is thru
                endcase
        end
 
 
        // 2 to 3 regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( 6+DATA_W ),
        .RESET_VAL      ( 0 )
        )
        regs_2_3
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2, mux_2  } ),
        .data_o         ( { rtn_3, sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3, data_3 } )
        );
 
 
        // mux 3
        always @ ( * ) begin
                casex ( rtn_3 )
                        'b1     : mux_3 <= pc_3_i;  // unsigned
                        default : mux_3 <= data_3;  // default is thru
                endcase
        end
 
 
        // 3 to 4 regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( 5+DATA_W ),
        .RESET_VAL      ( 0 )
        )
        regs_3_4
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3, mux_3  } ),
        .data_o         ( { sgn_4, rg_rd_4, dm_rd_4, hgh_4, ms_4, data_4 } )
        );
 
 
        // mux 4
        always @ ( * ) begin
                casex ( { rg_rd_4, dm_rd_4, hgh_4, sgn_4 } )
                        'b0100  : mux_4 <= dm_rd_data_4_i;
                        'b0101  : mux_4 <= $signed( dm_rd_data_4_i );
                        'b011x  : mux_4 <= { dm_rd_data_4_i, data_4[DATA_W/2-1:0] };
                        'b1x0x  : mux_4 <= $signed( rg_rd_data_4_i );
                        'b1x1x  : mux_4 <= { rg_rd_data_4_i, data_4[DATA_W/2-1:0] };
                        default : mux_4 <= data_4;  // default is thru
                endcase
        end
 
 
        // 4 to 5 regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( 1+DATA_W ),
        .RESET_VAL      ( 0 )
        )
        regs_4_5
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { ms_4, mux_4  } ),
        .data_o         ( { ms_5, data_5 } )
        );
 
 
        // mux 5
        always @ ( * ) begin
                casex ( ms_5 )
                        'b1     : mux_5 <= res_ms_5_i;
                        default : mux_5 <= data_5;  // default is thru
                endcase
        end
 
 
        // 5 to 6 regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( DATA_W ),
        .RESET_VAL      ( 0 )
        )
        d_out_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( mux_5 ),
        .data_o         ( data_6_o )
        );
 
 
endmodule

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : alu_mux.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Multiplexer for processor ALU.`
10
11			`Instantiates:`
12			`- (5x) pipe.v`
13
14			`Notes:`
15			`- Inputs at stage 1, outputs at stage 6.`
16			`- Default behavior is pass-thru.`
17
18			`--------------------------------------------------------------------------------`
19			`*/`
20
21			`module alu_mux`
22			`#(`
23			`parameter integer DATA_W = 8, // data width`
24			`parameter integer ADDR_W = 4 // address width`
25			`)`
26			`(`
27			`// clocks & resets`
28			`input wire clk_i, // clock`
29			`input wire rst_i, // async. reset, active high`
30			`// control I/O`
31			`input wire sgn_1_i, // 1=signed`
32			`input wire hgh_1_i, // 1=high`
33			`input wire as_1_i, // 1=add/subtract`
34			`input wire ms_1_i, // 1=multiply/shift`
35			`input wire rtn_1_i, // 1=return pc`
36			`input wire dm_rd_1_i, // 1=read`
37			`input wire rg_rd_1_i, // 1=read`
38			`// data I/O`
39			`input wire [DATA_W-1:0] res_lg_2_i, // logical result`
40			`input wire [DATA_W-1:0] res_as_2_i, // add/subtract result`
41			`input wire [ADDR_W-1:0] pc_3_i, // program counter`
42			`input wire [DATA_W/2-1:0] dm_rd_data_4_i, // dmem read data`
43			`input wire [DATA_W/2-1:0] rg_rd_data_4_i, // regs read data`
44			`input wire [DATA_W-1:0] res_ms_5_i, // multiply/shift result`
45			`output wire [DATA_W-1:0] data_6_o // data out`
46			`);`
47
48
49			`/*`
50			`----------------------`
51			`-- internal signals --`
52			`----------------------`
53			`*/`
54			`wire as_2, rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2;`
55			`wire rtn_3, sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3;`
56			`wire sgn_4, rg_rd_4, dm_rd_4, hgh_4, ms_4;`
57			`wire ms_5;`
58			`wire [DATA_W-1:0] data_3, data_4, data_5;`
59			`reg [DATA_W-1:0] mux_2, mux_3, mux_4, mux_5;`
60
61
62			`/*`
63			`================`
64			`== code start ==`
65			`================`
66			`*/`
67
68
69			`// 1 to 2 regs`
70			`pipe`
71			`#(`
72			`.DEPTH ( 1 ),`
73			`.WIDTH ( 7 ),`
74			`.RESET_VAL ( 0 )`
75			`)`
76			`regs_1_2`
77			`(`
78			`.clk_i ( clk_i ),`
79			`.rst_i ( rst_i ),`
80			`.data_i ( { as_1_i, rtn_1_i, sgn_1_i, rg_rd_1_i, dm_rd_1_i, hgh_1_i, ms_1_i } ),`
81			`.data_o ( { as_2, rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2 } )`
82			`);`
83
84
85			`// mux 2`
86			`always @ ( * ) begin`
87			`casex ( as_2 )`
88			`'b1 : mux_2 <= res_as_2_i;`
89			`default : mux_2 <= res_lg_2_i; // default is thru`
90			`endcase`
91			`end`
92
93
94			`// 2 to 3 regs`
95			`pipe`
96			`#(`
97			`.DEPTH ( 1 ),`
98			`.WIDTH ( 6+DATA_W ),`
99			`.RESET_VAL ( 0 )`
100			`)`
101			`regs_2_3`
102			`(`
103			`.clk_i ( clk_i ),`
104			`.rst_i ( rst_i ),`
105			`.data_i ( { rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2, mux_2 } ),`
106			`.data_o ( { rtn_3, sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3, data_3 } )`
107			`);`
108
109
110			`// mux 3`
111			`always @ ( * ) begin`
112			`casex ( rtn_3 )`
113			`'b1 : mux_3 <= pc_3_i; // unsigned`
114			`default : mux_3 <= data_3; // default is thru`
115			`endcase`
116			`end`
117
118
119			`// 3 to 4 regs`
120			`pipe`
121			`#(`
122			`.DEPTH ( 1 ),`
123			`.WIDTH ( 5+DATA_W ),`
124			`.RESET_VAL ( 0 )`
125			`)`
126			`regs_3_4`
127			`(`
128			`.clk_i ( clk_i ),`
129			`.rst_i ( rst_i ),`
130			`.data_i ( { sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3, mux_3 } ),`
131			`.data_o ( { sgn_4, rg_rd_4, dm_rd_4, hgh_4, ms_4, data_4 } )`
132			`);`
133
134
135			`// mux 4`
136			`always @ ( * ) begin`
137			`casex ( { rg_rd_4, dm_rd_4, hgh_4, sgn_4 } )`
138			`'b0100 : mux_4 <= dm_rd_data_4_i;`
139			`'b0101 : mux_4 <= $signed( dm_rd_data_4_i );`
140			`'b011x : mux_4 <= { dm_rd_data_4_i, data_4[DATA_W/2-1:0] };`
141			`'b1x0x : mux_4 <= $signed( rg_rd_data_4_i );`
142			`'b1x1x : mux_4 <= { rg_rd_data_4_i, data_4[DATA_W/2-1:0] };`
143			`default : mux_4 <= data_4; // default is thru`
144			`endcase`
145			`end`
146
147
148			`// 4 to 5 regs`
149			`pipe`
150			`#(`
151			`.DEPTH ( 1 ),`
152			`.WIDTH ( 1+DATA_W ),`
153			`.RESET_VAL ( 0 )`
154			`)`
155			`regs_4_5`
156			`(`
157			`.clk_i ( clk_i ),`
158			`.rst_i ( rst_i ),`
159			`.data_i ( { ms_4, mux_4 } ),`
160			`.data_o ( { ms_5, data_5 } )`
161			`);`
162
163
164			`// mux 5`
165			`always @ ( * ) begin`
166			`casex ( ms_5 )`
167			`'b1 : mux_5 <= res_ms_5_i;`
168			`default : mux_5 <= data_5; // default is thru`
169			`endcase`
170			`end`
171
172
173			`// 5 to 6 regs`
174			`pipe`
175			`#(`
176			`.DEPTH ( 1 ),`
177			`.WIDTH ( DATA_W ),`
178			`.RESET_VAL ( 0 )`
179			`)`
180			`d_out_regs`
181			`(`
182			`.clk_i ( clk_i ),`
183			`.rst_i ( rst_i ),`
184			`.data_i ( mux_5 ),`
185			`.data_o ( data_6_o )`
186			`);`
187
188
189			`endmodule`

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[/] [hive/] [trunk/] [v04.05/] [alu_mux.v] - Blame information for rev 4